RFU Based Computational Unit Design For Reconfigurable Processors
Authors: M. Aqeel Iqbal
Fully customized hardware based technology provides high performance and low power consumption by specializing the tasks in hardware but lacks design flexibility since any kind of changes require re-design and re-fabrication. Software based solutions operate with software instructions due to which a great flexibility is achieved from the easy development and maintenance of the software code. But this execution of instructions introduces a high overhead in performance and area consumption. In past few decades the reconfigurable computing domain has been introduced which overcomes the traditional trades-off between flexibility and performance and is able to achieve high performance while maintaining a good flexibility. The dramatic gains in terms of chip performance and design flexibility achieved through the reconfigurable computing systems are greatly dependent on the design of their computational units being integrated with reconfigurable logic resources. The computational unit of any reconfigurable system plays vital role in defining its strength. In this research paper an RFU based computational unit design has been presented using the tightly coupled, multi-threaded reconfigurable cores. The proposed design has been simulated for VLIW based architectures and a high gain in performance has been observed as compared to the conventional computing systems.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1060391Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1475
 M. Aqeel Iqbal and Uzma Saeed Awan, ÔÇÿReconfigurable Instruction Set Processor Design Using Software Based Configuration-, Proceedings of IEEE computer society, IEEE International Conference on Advanced Computer Theory and Engineering 2008 (ICACTE-2008), December 20-22, 2008, Phuket Island, Thailand.
 M. Aqeel Iqbal, Shoab A. Khan and Uzma Saeed Awan, 'RISP Design with Most Optimal Configuration Overhead for VLIW Based Architectures', Proceedings of IEEE computer society, 2nd IEEE International Conference on Electrical Engineering 2008 (ICEE-2008), March 25-26, 2008, UET Lahore, Pakistan.
 Aziz-Ur-Rehman, Dr. Aqeel A. Syed and M. Aqeel Iqbal, ÔÇÿIntelligent Reconfigurable Instruction Set Processor (IRISP) Design-, Proceedings of IEEE computer society, 11th IEEE International Multi-topic Conference 2007 (INMIC-2007), Dec 28-30, 2007, COMSATS Lahore, Pakistan.
 Ye, Z. A., Moshovos, A., Hauck, S., and Banerjee, P., "CHIMAERA: A High-Performance Architecture With a Tightly-Coupled Reconfigurable Functional Unit," Proceedings of the 27th International Symposium on Computer Architecture, pp. 225-235, 2000.
 Miyamori, T. and Olukotun, K., REMARC: Reconfigurable Multimedia Array Coprocessor IEICE Transactions on Information and Systems E82-D, vol. pp. 389-397, Feb, 1999.
 Xilinx, Virtex Series FPGAs, http://www.xilinx.com, 2001.
 Xilinx, Inc. Virtex II Configuration Architecture Advanced Users- Guide. March, 2000.
 S. C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R. R. Taylor, and R. Laufer. "PipeRench: A Coprocessor for Streaming Multimedia Acceleration", in Proc. Intl. Symp. on Computer Architecture, May 1999.
 Hauser, J. R. and Wawrzynek, J., "Garp: A MIPS Processor With a Reconfigurable Coprocessor," IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 12-21, 1997.
 C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H.Holt, J.Arnold and M. Gokhale, "The NAPA Adaptive Processing Architecture", IEEE Symposium on FPGAs for Custom Computing Machines, Apr. 1998.
 Altera Inc.. Altera Mega Core Functions, San Jose, CA, 1999. http://www.altera.com/html/tools/megacore.htm
 Philip James-Roxby and Steven A. Guccione. Automated Extraction of Run-Time Parameterisable Cores from Programmable Device Configurations. In Proceedings of IEEE Workshop on Field Programmable Custom Computing Machines, pages 153-161, April 2000.
 Edson L. Horta and John W. Lockwood. PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGAs). Washington University Department of Computer Science Technical Report WUCS-01-13. July 2001. (Available at http://www.arl.wustl.edu/arl/projects/fpx/parbit
 S. McMillan and S. Guccione, "Partial run-time reconfiguration using JRTR," in Field-Programmable Logic and Applications / The Roadmap to Reconfigurable Computing (FPL-2000), (Villach, Austria), pp. 352-360, Aug. 2000.
 X. Inc., "Configuration and readback of Virtex FPGAs using (JTAG) boundary scan." Xilinx XAPP139, Feb. 2000.