Search results for: CMOS temperature sensor

Authors: Shiyang Zhu, G. Q. Lo, D. L. Kwong

Abstract:

Silicon photonics has generated an increasing interest in recent years mainly for optical communications optical interconnects in microelectronic circuits or bio-sensing applications. The development of elementary passive and active components (including detectors and modulators), which are mainly fabricated on the silicon on insulator platform for CMOS-compatible fabrication, has reached such a performance level that the integration challenge of silicon photonics with microelectronic circuits should be addressed. Since crystalline silicon can only be grown from another silicon crystal, making it impossible to deposit in this state, the optical devices are typically limited to a single layer. An alternative approach is to integrate a photonic layer above the CMOS chip using back-end CMOS fabrication process. In this paper, various materials, including silicon nitride, amorphous silicon, and polycrystalline silicon, for this purpose are addressed.

Keywords: Silicon photonics, CMOS, Integration.

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Authors: Kimberly Jane S. Uy, Patricia Angela Reyes-Abu, Wen Yaw Chung

Abstract:

A high precision temperature insensitive current and voltage reference generator is presented. It is specifically developed for temperature compensated oscillator. The circuit, designed using MXIC 0.5um CMOS technology, has an operating voltage that ranges from 2.6V to 5V and generates a voltage of 1.21V and a current of 6.38 ӴA. It exhibits a variation of ±0.3nA for the current reference and a stable output for voltage reference as the temperature is varied from 0°C to 70°C. The power supply rejection ratio obtained without any filtering capacitor at 100Hz and 10MHz is -30dB and -12dB respectively.

Keywords: Current reference, voltage reference, threshold voltage, temperature compensation, mobility.

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Authors: Jung-Ho Moon, Myung-Gon Yoon, Tae Kwon Ha

Abstract:

This paper presents a wireless sensor network protocol for a car parking monitoring system. A wireless sensor network for the purpose is composed of multiple sensor nodes, a sink node, a gateway, and a server. Each of the sensor nodes is equipped with a 3-axis AMR sensor and deployed in the center of a parking space. The sensor node reads its sensor values periodically and transmits the data to the sink node if the current and immediate past sensor values show a difference exceeding a threshold value. The operations of the sink and sensor nodes are described in detail along with flow diagrams. The protocol allows a low-duty cycle operation of the sensor nodes and a flexible adjustment of the threshold value used by the sensor nodes.

Keywords: Car parking monitoring, sensor node, wireless sensor network, network protocol.

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Authors: Spyridon Nikolaidis

Abstract:

A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.

Keywords: CMOS gate modeling, Inverter modeling, transistor current model, timing model.

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Authors: Kai-Chao Yang, Chun-Ming Huang, Chih-Chiao Yang, Chien-Ming Wu

Abstract:

Sensors have been used in various kinds of academic fields and applications. In this article, we propose the idea of modularized sensors that combine multiple sensor modules into a unique sensor. We divide a sensor into several units according to functionalities. Each unit has different sensor modules, which share the same type of connectors and can be serially and arbitrarily connected each other. A user can combine different sensor modules into a sensor platform according to requirements. Compared with current modularized sensors, the proposed sensor platform is highly flexible and reusable. We have implemented the prototype of the proposed sensor platform, and the experimental results show the proposed platform can work correctly.

Keywords: Sensor device, sensor fusion.

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Authors: Dil Nawaz Khan, M. H. Sayyad, Muhammad Yaseen, Munawar Ali Munawar, Mukhtar Ali

Abstract:

Effect of temperature and light was investigated on a thin film of organic semiconductor formyl-TIPPCu(II) deposited on a glass substrate with preliminary evaporated gold electrodes. The electrical capacitance and resistance of the fabricated device were evaluated under the effect of temperature and light. The relative capacitance of the fabricated sensor increased by 4.3 times by rising temperature from 27 to 1870C, while under illumination up to 25000 lx, the capacitance of the Au/formyl-TIPPCu(II)/Au photo capacitive sensor increased continuously by 13.2 times as compared to dark conditions.

Keywords: formyl-TIPPCu(II), Organic semiconductor, Photocapacitance, Polarizability.

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Authors: Yong Wang, Wang Ling Goh, Jung Hyup Lee, Kevin T. C. Chai, Minkyu Je

Abstract:

This paper presents a resonant-based read-out circuit for capacitive pressure sensors. The proposed read-out circuit consists of an LC oscillator and a counter. The circuit detects the capacitance changes of a capacitive pressure sensor by means of frequency shifts from its nominal operation frequency. The proposed circuit is designed in 0.18m CMOS with an estimated power consumption of 43.1mW. Simulation results show that the circuit has a capacitive resolution of 8.06kHz/fF, which enables it for high resolution pressure detection.

Keywords: Capacitance-to-frequency converter, Capacitive pressure sensor, Digital counter, LC oscillator.

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Authors: Sanaz Haddadian, Rahele Hedayati

Abstract:

A 10bit, 40 MSps, sample and hold, implemented in 0.18-μm CMOS technology with 3.3V supply, is presented for application in the front-end stage of an analog-to-digital converter. Topology selection, biasing, compensation and common mode feedback are discussed. Cascode technique has been used to increase the dc gain. The proposed opamp provides 149MHz unity-gain bandwidth (wu), 80 degree phase margin and a differential peak to peak output swing more than 2.5v. The circuit has 55db Total Harmonic Distortion (THD), using the improved fully differential two stage operational amplifier of 91.7dB gain. The power dissipation of the designed sample and hold is 4.7mw. The designed system demonstrates relatively suitable response in different process, temperature and supply corners (PVT corners).

Keywords: Analog Integrated Circuit Design, Sample & Hold Amplifier and CMOS Technology.

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Authors: Mahdi Ebrahimzadeh

Abstract:

In this paper we introduce an ultra low power CMOS LC oscillator and analyze a method to design a low power low phase noise complementary CMOS LC oscillator. A 1.8GHz oscillator is designed based on this analysis. The circuit has power supply equal to 1.1 V and dissipates 0.17 mW power. The oscillator is also optimized for low phase noise behavior. The oscillator phase noise is -126.2 dBc/Hz and -144.4 dBc/Hz at 1 MHz and 8 MHz offset respectively.

Keywords: LC oscillator, Low Power, Low Phase Noise

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Authors: Gianluca Cornetta, David J. Santos

Abstract:

This paper describes a 2.4 GHz passive switch mixer and a 5/2.5 GHz voltage-controlled negative Gm oscillator (VCO) with an inversion-mode MOS varactor. Both circuits are implemented using a 1P8M 0.13 μm process. The switch mixer has an input referred 1 dB compression point of -3.89 dBm and a conversion gain of -0.96 dB when the local oscillator power is +2.5 dBm. The VCO consumes only 1.75 mW, while drawing 1.45 mA from a 1.2 V supply voltage. In order to reduce the passives size, the VCO natural oscillation frequency is 5 GHz. A clocked CMOS divideby- two circuit is used for frequency division and quadrature phase generation. The VCO has a -109 dBc/Hz phase noise at 1 MHz frequency offset and a 2.35-2.5 GHz tuning range (after the frequency division), thus complying with ZigBee requirements.

Keywords: Switch Mixers, Varactors, IEEE 802.15.4 (ZigBee), Direct Conversion Receiver, Wireless Sensor Networks.

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Authors: O. Alizadeh Sahraei, A. Khodadadi, Y. Mortazavi, M. Vesali Naseh, S. Mosadegh

Abstract:

A composite made of plasma functionalized multiwall carbon nanotubes (MWNTs) coated with SnO2 was synthesized by sonochemical precipitation method. Thick layer of this nanocomposite material was used as ethanol sensor at low temperatures. The composite sensitivity for ethanol has increased by a factor of 2 at room temperature and by a factor of 13 at 250°C in comparison to that of pure SnO2. SEM image of nanocomposite material showed MWNTs were embedded in SnO2 matrix and also a higher surface area was observed in the presence of functionalized MWNTs. Greatly improved sensitivity of the composite material to ethanol can be attributed to new gas accessing passes through MWNTs and higher specific surface area.

Keywords: Carbon nanotube, Functionalized, Gas sensor, Low temperature, Nanocomposite, Tin oxide.

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Authors: Gao Wei, Xu Minglu, Xu Yan, Zhang Xiaotong, Wang Xinghua

Abstract:

A 3.5-bit stage of the CMOS pipelined ADC is proposed. In this report, the main part of 3.5-bit stage ADC is introduced. How the MDAC, comparator and encoder worked and designed are shown in details. Besides, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with differential amplifier, this OTA achieve high-gain and high-speed. This design was using CMOS 0.18um process and simulation in Cadence. The result of the simulation shows that the OTA has a gain up to 80dB, the unity gain bandwidth of about 1.138GHz with 2pF load.

Keywords: pipelined ADC, MDAC, operational amplifier.

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Authors: Cesar Eduardo Hernández Curiel, Victor Hugo Benítez Baltazar, Jesús Horacio Pacheco Ramírez

Abstract:

This paper is devoted to present the advances in the design of a prototype that is able to supervise the complex behavior of water quality parameters such as pH and temperature, via a real-time monitoring system. The current water quality tests that are performed in government water quality institutions in Mexico are carried out in problematic locations and they require taking manual samples. The water samples are then taken to the institution laboratory for examination. In order to automate this process, a water quality monitoring system based on wireless sensor networks is proposed. The system consists of a sensor node which contains one pH sensor, one temperature sensor, a microcontroller, and a ZigBee radio, and a base station composed by a ZigBee radio and a PC. The progress in this investigation shows the development of a water quality monitoring system. Due to recent events that affected water quality in Mexico, the main motivation of this study is to address water quality monitoring systems, so in the near future, a more robust, affordable, and reliable system can be deployed.

Keywords: pH measurement, water quality monitoring, wireless sensor networks, ZigBee.

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Authors: Arafat A. A. Shabaneh

Abstract:

Harsh environments require developed detection by an optical communication system to ensure a high level of security and safety. Fiber Bragg gratings (FBGs) are emerging sensing instruments that respond to variations in strain and temperature by varying wavelengths. In this study, a cascaded uniform FBG is designed as a strain sensor for 6 km length at 1550 nm wavelength with 30 °C temperature by analyzing dynamic strain and wavelength shifts. The FBG is placed in a small segment of an optical fiber that reflects light with a specific wavelength and passes on the remaining wavelengths. Consequently, periodic alteration occurs in the refractive index in the fiber core. The alteration in the modal index of the fiber is produced by strain effects on a Bragg wavelength. When the developed sensor is exposed to the strain (0.01) of the cascaded uniform FBG, the wavelength shifts by 0.0000144383 μm. The sensing accuracy of the developed sensor is 0.0012. Simulation results show the reliability and effectiveness of the strain monitoring sensor for remote sensing application.

Keywords: Remote sensing, cascaded fiber Bragg grating, strain sensor, wavelength shift.

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Authors: Nasir Mehmood, Saad Rahman, Vinodh Ravinath, Mahesh Balaji

Abstract:

This paper describes the design of a programmable FSK-modulator based on VCO and its implementation in 0.35m CMOS process. The circuit is used to transmit digital data at 100Kbps rate in the frequency range of 400-600MHz. The design and operation of the modulator is discussed briefly. Further the characteristics of PLL, frequency synthesizer, VCO and the whole design are elaborated. The variation among the proposed and tested specifications is presented. Finally, the layout of sub-modules, pin configurations, final chip and test results are presented.

Keywords: FSK Modulator, CMOS, VCO, Phase Locked Loop, Frequency Synthesizer.

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Authors: M. Geetha Priya, K. Baskaran, S. Srinivasan

Abstract:

Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.

Keywords: Low power, CMOS, pass-transistor, flash memory, logic gates.

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Authors: M. Aleshams, A. Shahsavandi

Abstract:

This paper describes a CMOS four-quadrant multiplier intended for use in the front-end receiver by utilizing the square-law characteristic of the MOS transistor in the saturation region. The circuit is based on 0.35 um CMOS technology simulated using HSPICE software. The mixer has a third-order inter the power consumption is 271uW from a single 1.2V power supply. One of the features of the proposed design is using two MOS transistors limitation to reduce the supply voltage, which leads to reduce the power consumption. This technique provides a GHz bandwidth response and low power consumption.

Keywords: RF-Mixer, Multiplier, cut-off frequency, power consumption

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Authors: Heejin Lee, Yeonjoo Kim, Kyungrak Sohn

Abstract:

We present a white LED-based optical wireless communication systems for indoor ubiquitous sensor networks. Each sensor node could access to the server through the PLC (Power Line Communication)-Ethernet interface. The proposed system offers a full-duplex wireless link by using different wavelengths to reduce the inter-symbol interference between uplink and downlink. Through the 1-to-n optical wireless sensor network and PLC modem, the mobile terminals send a temperature data to server. The data transmission speed and distance are 115.2kbps and about 60cm, respectively.

Keywords: Visible light communications, LED lighting, powerline communications, ubiquitous sensor networks, full-duplex links

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Authors: J. S. Kim, N. P. Hong

Abstract:

In this paper, a CMOS vector modulator designed for wireless backhaul system based on 802.11ac is presented. A poly phase filter and sign select switches yield two orthogonal signal paths. Two variable gain amplifiers with strongly reduced phase shift of only ±5 ° are used to weight these paths. It has a phase control range of 360 ° and a gain range of -10 dB to 10 dB. The current drawn from a 1.2 V supply amounts 20.4 mA. Using a 0.13 mm technology, the chip die area amounts 1.47x0.75 mm².

Keywords: CMOS, vector modulator, backhaul, 802.11ac.

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Authors: Alpana Agarwal, Akhil Sharma

Abstract:

This work presents a fully differential CMOS amplifier consisting of two self-biased gain boosted inverter stages, that provides an alternative to the power hungry operational amplifier. The self-biasing avoids the use of external biasing circuitry, thus reduces the die area, design efforts, and power consumption. In the present work, regulated cascode technique has been employed for gain boosting. The Miller compensation is also applied to enhance the phase margin. The circuit has been designed and simulated in 1.8 V 0.18 µm CMOS technology. The simulation results show a high DC gain of 100.7 dB, Unity-Gain Bandwidth of 107.8 MHz, and Phase Margin of 66.7^o with a power dissipation of 286 μW and makes it suitable candidate for the high resolution pipelined ADCs.

Keywords: CMOS amplifier, gain boosting, inverter-based amplifier, self-biased inverter.

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Authors: Shashank Gautam

Abstract:

This paper proposes techniques like MT CMOS, POWER GATING, DUAL STACK, GALEOR and LECTOR to reduce the leakage power. A Full Adder has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of Full Adder. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent.

Keywords: Low Power, MT CMOS, Galeor, Lector, Power Gating, Dual Stack, Full Adder.

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Authors: Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Keivan Navi

Abstract:

In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using HSpice and 0.18┬Ám CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the power-delay product (PDP). The PDP of Multi-Output design at 1.8v power supply is around 0.15 femto joule that is 5% lower than conventional dynamic full adder cell and at least 21% lower than other static full adders.

Keywords: Bridge Style, Dynamic Logic, Full Adder, HighSpeed, Multi Output, NP-CMOS, Zipper.

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Authors: Jung-Ho Moon, Tae Kwon Ha

Abstract:

This paper presents a car parking monitoring system using wireless sensor networks. Multiple sensor nodes and a sink node, a gateway, and a server constitute a wireless network for monitoring a parking lot. Each of the sensor nodes is equipped with a 3-axis AMR sensor and deployed in the center of a parking space. Each sensor node reads its sensor values periodically and transmits the data to the sink node if the current and immediate past sensor values show a difference exceeding a threshold value. The sensor nodes and sink node use the 448 MHz band for wireless communication. Since RF transmission only occurs when sensor values show abrupt changes, the number of RF transmission operations is reduced and battery power can be conserved. The data from the sensor nodes reach the server via the sink node and gateway. The server determines which parking spaces are taken by cars based upon the received sensor data and reference values. The reference values are average sensor values measured by each sensor node when the corresponding parking spot is not occupied by a vehicle. Because the decision making is done by the server, the computational burden of the sensor node is relieved, which helps reduce the duty cycle of the sensor node.

Keywords: Car parking monitoring, magnetometer, sensor node, wireless sensor network.

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Authors: Tae Kyung Kim, Hee Suk Seo

Abstract:

Adapting various sensor devices to communicate within sensor networks empowers us by providing range of possibilities. The sensors in sensor networks need to know their measurable belief of trust for efficient and safe communication. In this paper, we suggested a trust model using fuzzy logic in sensor network. Trust is an aggregation of consensus given a set of past interaction among sensors. We applied our suggested model to sensor networks in order to show how trust mechanisms are involved in communicating algorithm to choose the proper path from source to destination.

Keywords: Fuzzy, Sensor Networks, Trust.

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Authors: S. Mosadegh Sedghi, Y. Mortazavi, A. Khodadadi, O. Alizadeh Sahraei, M. Vesali Naseh

Abstract:

In this study, a low temperature sensor highly selective to CO in presence of methane is fabricated by using 4 nm SnO2 quantum dots (QDs) prepared by sonication assisted precipitation. SnCl4 aqueous solution was precipitated by ammonia under sonication, which continued for 2 h. A part of the sample was then dried and calcined at 400°C for 1.5 h and characterized by XRD and BET. The average particle size and the specific surface area of the SnO2 QDs as well as their sensing properties were compared with the SnO2 nano-particles which were prepared by conventional sol-gel method. The BET surface area of sonochemically as-prepared product and the one calcined at 400°C after 1.5 hr are 257 m2/gr and 212 m2/gr respectively while the specific surface area for SnO2 nanoparticles prepared by conventional sol-gel method is about 80m2/gr. XRD spectra revealed pure crystalline phase of SnO2 is formed for both as-prepared and calcined samples of SnO2 QDs. However, for the sample prepared by sol-gel method and calcined at 400°C SnO crystals are detected along with those of SnO2. Quantum dots of SnO2 show exceedingly high sensitivity to CO with different concentrations of 100, 300 and 1000 ppm in whole range of temperature (25- 350°C). At 50°C a sensitivity of 27 was obtained for 1000 ppm CO, which increases to a maximum of 147 when the temperature rises to 225°C and then drops off while the maximum sensitivity for the SnO2 sample prepared by the sol-gel method was obtained at 300°C with the amount of 47.2. At the same time no sensitivity to methane is observed in whole range of temperatures for SnO2 QDs. The response and recovery times of the sensor sharply decreases with temperature, while the high selectivity to CO does not deteriorate.

Keywords: Sonochemical, SnO2 QDs, SnO2 gas sensor

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Authors: T.C.Manjunath, Ph.D., Ashok Kusagur, Shruthi Sanjay, Saritha Sindushree, C. Ardil

Abstract:

This paper deals with the design, development & implementation of a temperature sensor using zigbee. The main aim of the work undertaken in this paper is to sense the temperature and to display the result on the LCD using the zigbee technology. ZigBee operates in the industrial, scientific and medical (ISM) radio bands; 868 MHz in Europe, 915 MHz in the USA and 2.4 GHz in most jurisdictions worldwide. The technology is intended to be simpler and cheaper than other WPANs such as Bluetooth. The most capable ZigBee node type is said to require only about 10 % of the software of a typical Bluetooth or Wireless Internet node, while the simplest nodes are about 2 %. However, actual code sizes are much higher, more like 50 % of the Bluetooth code size. ZigBee chip vendors have announced 128-kilobyte devices. In this work undertaken in the design & development of the temperature sensor, it senses the temperature and after amplification is then fed to the micro controller, this is then connected to the zigbee module, which transmits the data and at the other end the zigbee reads the data and displays on to the LCD. The software developed is highly accurate and works at a very high speed. The method developed shows the effectiveness of the scheme employed.

Keywords: Zigbee, Microcontroller, PIC, Transmitter, Receiver, Synchronous, Blue tooth, Communication.

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Authors: Abdelmonaem Ayachi, Belgacem Hamdi

Abstract:

This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: Semiconductors, digital electronics, double pass transistor technology, Full adder, fault tolerance.

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Authors: Andrew Randles, Ilker Ocak, Cheam Daw Don, Navab Singh, Alex Gu

Abstract:

Nine Degrees of Freedom (9 DOF) systems are already in development in many areas. In this paper, an integrated pressure sensor is proposed that will make use of an already existing monolithic 9 DOF inertial MEMS platform. Capacitive pressure sensors can suffer from limited sensitivity for a given size of membrane. This novel pressure sensor design increases the sensitivity by over 5 times compared to a traditional array of square diaphragms while still fitting within a 2 mm x 2 mm chip and maintaining a fixed static capacitance. The improved design uses one large diaphragm supported by pillars with fixed electrodes placed above the areas of maximum deflection. The design optimization increases the sensitivity from 0.22 fF/kPa to 1.16 fF/kPa. Temperature sensitivity was also examined through simulation.

Keywords: Capacitive pressure sensor, 9 DOF, 10 DOF, sensor, capacitive, inertial measurement unit, IMU, inertial navigation system, INS.

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Authors: Eduard Atkin, Alexander Klyuev, Vitaly Shumikhin

Abstract:

An approach and its implementation in 0.18 m CMOS process of the multichannel ASIC for capacitive (up to 30 pF) sensors are described in the paper. The main design aim was to study an analog data-driven architecture. The design was done for an analog derandomizing function of the 128 to 16 structure. That means that the ASIC structure should provide a parallel front-end readout of 128 input analog sensor signals and after the corresponding fast commutation with appropriate arbitration logic their processing by means of 16 output chains, including analog-to-digital conversion. The principal feature of the ASIC is a low power consumption within 2 mW/channel (including a 9-bit 20Ms/s ADC) at a maximum average channel hit rate not less than 150 kHz.

Keywords: Data-driven architecture, derandomizer, multichannel sensor readout

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Authors: M.Yousefi, A.Vatanjou, F.Nazeri

Abstract:

A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here. With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to output. Designed circuit is simulated with HSPICE using level 49 parameters (BSIM 3v3) in 0.35mm standard CMOS technology. DC gain achieved is 56.7dB and Unity Gain Bandwidth (UGB) obtained is 1.15GHz. These results confirm that adding extra paths for signal can improve DC gain and UGB of folded-cascode significantly.

Keywords: OTA (Operational Transconductance Amplifier), DC gain, Unity Gain Bandwidth (UGBW)

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