Search results for: Average gate length (Lavg)

Authors: Maruful H. Mazumder, Raymond I. Gilbert, Zhen- T. Chang

Abstract:

A reliable estimate of the average bond stress within the anchorage of steel reinforcing bars in tension is critically important for the design of reinforced concrete member. This paper describes part of a recently completed experimental research program in the Centre for Infrastructure Engineering and Safety (CIES) at the University of New South Wales, Sydney, Australia aimed at assessing the effects of different factors on the anchorage requirements of modern high strength steel reinforcing bars. The study found that an increase in the anchorage length and bar diameter generally leads to a reduction of the average ultimate bond stress. By the extension of a well established analytical model of bond and anchorage, it is shown here that the differences in the average ultimate bond stress for different anchorage lengths is associated with the variable degree of plastic deformation in the tensile zone of the concrete surrounding the bar.

Keywords: Anchorage, Bond stress, Development length, Reinforced concrete.

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Authors: N. Katemee, T. Mayureesawan

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This paper developed the c-Chart based on a Zero- Inflated Poisson (ZIP) processes that approximated by a geometric distribution with parameter p. The p estimated that fit for ZIP distribution used in calculated the mean, median, and variance of geometric distribution for constructed the c-Chart by three difference methods. For cg-Chart, developed c-Chart by used the mean and variance of the geometric distribution constructed control limits. For cmg-Chart, the mean used for constructed the control limits. The cme- Chart, developed control limits of c-Chart from median and variance values of geometric distribution. The performance of charts considered from the Average Run Length and Average Coverage Probability. We found that for an in-control process, the cg-Chart is superior for low level of mean at all level of proportion zero. For an out-of-control process, the cmg-Chart and cme-Chart are the best for mean = 2, 3 and 4 at all level of parameter.

Keywords: average coverage probability, average run length, geometric distribution, zero-inflated poisson distribution

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Authors: Dawit Burusie Abdi, Mamidala Jagadesh Kumar

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In this paper, using 2D TCAD simulations, the application of a dual material gate (DMG) for suppressing ambipolar conduction in a tunnel field effect transistor (TFET) is demonstrated. Using the proposed DMG concept, the ambipolar conduction can be effectively suppressed even if the drain doping is as high as that of the source doping. Achieving this symmetrical doping, without the ambipolar conduction in TFETs, gives the advantage of realizing both n-type and p-type devices with the same doping sequences. Furthermore, the output characteristics of the DMG TFET exhibit a good saturation when compared to that of the gate-drain underlap approach. This improved behavior of the DMG TFET makes it a good candidate for inverter based logic circuits.

Keywords: Dual material gate, suppressing ambipolar current, symmetrically doped TFET, tunnel FETs, PNPN TFET.

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Authors: Y. Areepong

Abstract:

The main goal of this paper is to study Statistical Process Control (SPC) with Exponentially Weighted Moving Average (EWMA) control chart when observations are serially-correlated. The characteristic of control chart is Average Run Length (ARL) which is the average number of samples taken before an action signal is given. Ideally, an acceptable ARL of in-control process should be enough large, so-called (ARL₀). Otherwise it should be small when the process is out-of-control, so-called Average of Delay Time (ARL₁) or a mean of true alarm. We find explicit formulas of ARL for EWMA control chart for Seasonal Autoregressive and Moving Average processes (SARMA) with Exponential white noise. The results of ARL obtained from explicit formula and Integral equation are in good agreement. In particular, this formulas for evaluating (ARL₀) and (ARL₁) be able to get a set of optimal parameters which depend on smoothing parameter (λ) and width of control limit (H) for designing EWMA chart with minimum of (ARL₁).

Keywords: Average Run Length1, Optimal parameters, Exponentially Weighted Moving Average (EWMA) control chart.

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Authors: Muhammad Naeem, Asif Hussain Bhatti, Muhammad Fahad Nouman

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115 samples of Labeo calbasu ranged 8.0-17.9cm length with mean11.90±1.96 and 4.9-68.5g weight with mean 22.25±12.54 from the River Chenab, Southern Punjab, Pakistan were analyzed to investigate length-weight relationships (LWR) of fish in relation to condition factor (K). Standard length (SL), fork length (FL), head length (HL) head width (HW), body girth (BG), dorsal fin length (DFL), dorsal fin base (DFB), pectoral fin length (PcFL), pelvic fin length (PvFL) and anal fin length (AFL) are found to be highly correlated with increasing total length and wet body weight (r > 0.500). Wet body weight has positive (r=0.540) and total length has no correlation (r=0.344) with calculated Condition factor (K). The slope “b" in the relationship is 3.27 and intercepts -2.2258.

Keywords: Labeo calbasu, Length-weight relationship, Body weight, condition factor

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Authors: Santanu Santra, Utpal Roy

Abstract:

The most important mathematical operation for any computing system is addition. An efficient adder can be of greater assistance in designing of any arithmetic circuits. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology to create electronic circuits for computing devices and suitable candidate for next generation of computing systems. The article presents a modest approach to implement a novel XOR gate. The gate is simple in structure and powerful in terms of implementing digital circuits. By applying the XOR gate, the hardware requirement for a QCA circuit can be decrease and circuits can be simpler in level, clock phase and cell count. In order to verify the functionality of the proposed device some implementation of Half Adder (HA) and Full Adder (FA) is checked by means of computer simulations using QCA-Designer tool. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, Computing system, Majority gate, QCA, QCA Designer.

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Authors: S. Sutin, M. Pollar, M. Jaroensutasinee, K. Jaroensutasinee

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This study investigated morphology of the Spanner Barb (Puntius lateristriga Valenciennes, 1842) and water quality at Thepchana waterfall. This study was conducted at Thepchana Waterfall, Khao Nan National Park from March to May 2007. There were 40 Spanner Barb collected with 20 males and 20 females. Males had an average of 5.57 cm in standard length, 6.62 cm in total length and 5.18 g in total body weight. Females had an average of 7.25 cm in standard length, 8.24 cm in total length and 10.96 g in total body weight. The length (L) – weight (W) relationships for combining sexes, males and females were LogW = -2.137 + 3.355logL, log W = -0.068 + 3.297logL, and log W = -2.068 + 3.297logL, respectively. The Spanner Barb were smaller size fish with a compressed form; terminal mouth; villiform teeth; ctenoid scale; concave tail; general body color yellowish olive, with slight reddish tint to fins; vertical band beginning below dorsal and horizontal stripe from base of tail almost to vertical band. They also had a vertical band midway between the eye and first vertical band. There was a black spot above anal fin. The bladder looked like J-shape. Inside of the bladder was found small insects and insect lava. The body length and the bowels length was 1:1 ratio. The water temperature ranged from 25.00 – 27.00 °C which was appropriate for their habitat characteristics. Acid - alkalinity ranged from 6.65 – 6.90 mg/l. Dissolved oxygen ranged from 4.55 – 4.70 mg/l. Water hardness ranged from 31.00 – 48.00 mg/l. The amount of ammonia was about 0.25 mg/l.

Keywords: Spanner barb, morphology, water quality.

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Authors: Tom Snir, Eitan Rubin

Abstract:

Mendelian Disease Genes represent a collection of single points of failure for the various systems they constitute. Such genes have been shown, on average, to encode longer proteins than 'non-disease' proteins. Existing models suggest that this results from the increased likeli-hood of longer genes undergoing mutations. Here, we show that in saturated mutagenesis experiments performed on model organisms, where the likelihood of each gene mutating is one, a similar relationship between length and the probability of a gene being lethal was observed. We thus suggest an extended model demonstrating that the likelihood of a mutated gene to produce a severe phenotype is length-dependent. Using the occurrence of conserved domains, we bring evidence that this dependency results from a correlation between protein length and the number of functions it performs. We propose that protein length thus serves as a proxy for protein cardinality in different networks required for the organism's survival and well-being. We use this example to argue that the collection of Mendelian Disease Genes can, and should, be used to study the rules governing systems vulnerability in living organisms.

Keywords: Systems Biology, Protein Length

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Authors: N. Massoum, A. Guen. Bouazza, B. Bouazza, A. El Ouchdi

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The progress of industry integrated circuits in recent years has been pushed by continuous miniaturization of transistors. With the reduction of dimensions of components at 0.1 micron and below, new physical effects come into play as the standard simulators of two dimensions (2D) do not consider. In fact the third dimension comes into play because the transverse and longitudinal dimensions of the components are of the same order of magnitude. To describe the operation of such components with greater fidelity, we must refine simulation tools and adapted to take into account these phenomena. After an analytical study of the static characteristics of the component, according to the different operating modes, a numerical simulation is performed of field-effect transistor with submicron gate MESFET GaInP. The influence of the dimensions of the gate length is studied. The results are used to determine the optimal geometric and physical parameters of the component for their specific applications and uses.

Keywords: Monte Carlo simulation, transient electron transport, MESFET device.

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Authors: Farid Moshgelani, Dhamin Al-Khalili, Côme Rozon

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In this paper, FinFET devices are analyzed with emphasis on sub-threshold leakage current control. This is achieved through proper biasing of the back gate, and through the use of asymmetric work functions for the four terminal FinFET devices. We are also examining different configurations of multiplexers and XOR gates using transistors of symmetric and asymmetric work functions. Based on extensive characterization data for MUX circuits, our proposed configuration using symmetric devices lead to leakage current and delay improvements of 65% and 47% respectively compared to results in the literature. For XOR gates, a 90% improvement in the average leakage current is achieved by using asymmetric devices. All simulations are based on a 25nm FinFET technology using the University of Florida UFDG model.

Keywords: FinFET, logic functions, asymmetric workfunction devices, back gate biasing, sub-threshold leakage current.

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Authors: Maharavo Randrianarivony

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The length  of a given rational B'ezier curve is efficiently estimated. Since a rational B'ezier function is nonlinear, it is usually impossible to evaluate its length exactly. The length is approximated by using subdivision and the accuracy of the approximation n is investigated. In order to improve the efficiency, adaptivity is used with some length estimator. A rigorous theoretical analysis of the rate of convergence of n to  is given. The required number of subdivisions to attain a prescribed accuracy is also analyzed. An application to CAD parametrization is briefly described. Numerical results are reported to supplement the theory.

Keywords: Adaptivity, Length, Parametrization, Rational Bezier

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Authors: Z. X. Chen, N. Singh, D.-L. Kwong

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This paper presents a vertical silicon nanowire n- MOSFET integrated with a CMOS-compatible fully-silicided (FUSI) NiSi2 gate. Devices with nanowire diameter of 50nm show good electrical performance (SS < 70mV/dec, DIBL < 30mV/V, Ion/Ioff > 107). Most significantly, threshold voltage tunability of about 0.2V is shown. Although threshold voltage remains low for the 50nm diameter device, it is expected to become more positive as nanowire diameter reduces.

Keywords: NiSi , fully-silicided (FUSI) gate, vertical siliconnanowire (SiNW), CMOS compatible.

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Authors: Spyridon Nikolaidis

Abstract:

A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.

Keywords: CMOS gate modeling, Inverter modeling, transistor current model, timing model.

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Authors: A. AlKalbany, H. Al hassan, M. Saeb

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The “PYRAMIDS" Block Cipher is a symmetric encryption algorithm of a 64, 128, 256-bit length, that accepts a variable key length of 128, 192, 256 bits. The algorithm is an iterated cipher consisting of repeated applications of a simple round transformation with different operations and different sequence in each round. The algorithm was previously software implemented in Cµ code. In this paper, a hardware implementation of the algorithm, using Field Programmable Gate Arrays (FPGA), is presented. In this work, we discuss the algorithm, the implemented micro-architecture, and the simulation and implementation results. Moreover, we present a detailed comparison with other implemented standard algorithms. In addition, we include the floor plan as well as the circuit diagrams of the various micro-architecture modules.

Keywords: FPGA, VHDL, micro-architecture, encryption, cryptography, algorithm, data communication security.

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Authors: R. Pesce Delfino, M. Selvaggi, G. V. Celano, C. Dario

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Data on 657 lactation from 163 Maltese goat, collected over a 5-year period were analyzed by a mixed model to estimate the variance components for heritability. The considered lactation traits were: milk yield (MY) and lactation length (LL). Year, parity and type of birth (single or twin) were significant sources of variation for lactation length; on the other hand milk yield was significantly influenced only by the year. The average MY was 352.34 kg and the average LL was 230 days. Estimates of heritability were 0.21 and 0.15 for MY and LL respectively. These values suggest there is low correlation between genotype and phenotype so it may be difficult to evaluate animals directly on phenotype. So, the genetic improvement of this breed may be quite slow without the support of progeny test aimed to select Maltese breeders.

Keywords: Heritability estimate, lactation traits, Maltese goat

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Authors: Rishikesh Pandey, Maneesha Gupta

Abstract:

A new low-voltage floating gate MOSFET (FGMOS) based squarer using square law characteristic of the FGMOS is proposed in this paper. The major advantages of the squarer are simplicity, rail-to-rail input dynamic range, low total harmonic distortion, and low power consumption. The proposed circuit is biased without body effect. The circuit is designed and simulated using SPICE in 0.25μm CMOS technology. The squarer is operated at the supply voltages of ±0.75V . The total harmonic distortion (THD) for the input signal 0.75Vpp at 25 KHz, and maximum power consumption were found to be less than 1% and 319μW respectively.

Keywords: Analog signal processing, floating gate MOSFETs, low-voltage, Spice, squarer.

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Authors: Mecheri Zeid Belmecheri, Maamar Ahfir, Izzet Kale

Abstract:

Automatic cardiac auscultation is still a subject of research in order to establish an objective diagnosis. Recorded heart sounds as Phonocardiogram (PCG) signals can be used for automatic segmentation into components that have clinical meanings. These are the first sound, S1, the second sound, S2, and the systolic and diastolic components, respectively. In this paper, an automatic method is proposed for the robust segmentation of heart sounds. This method is based on calculating an intermediate sawtooth-shaped signal from the length variation of the recorded PCG signal in the time domain and, using its positive derivative function that is a binary signal in training a Recurrent Neural Network (RNN). Results obtained in the context of a large database of recorded PCGs with their simultaneously recorded Electrocardiograms (ECGs) from different patients in clinical settings, including normal and abnormal subjects, show on average a segmentation testing performance average of 76% sensitivity and 94% specificity.

Keywords: Heart sounds, PCG segmentation, event detection, Recurrent Neural Networks, PCG curve length.

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Authors: Satyendra Nath Mandal, J. Pal Choudhury, Dilip De, S. R. Bhadra Chaudhuri

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The production of a plant can be measured in terms of seeds. The generation of seeds plays a critical role in our social and daily life. The fruit production which generates seeds, depends on the various parameters of the plant, such as shoot length, leaf number, root length, root number, etc When the plant is growing, some leaves may be lost and some new leaves may appear. It is very difficult to use the number of leaves of the tree to calculate the growth of the plant.. It is also cumbersome to measure the number of roots and length of growth of root in several time instances continuously after certain initial period of time, because roots grow deeper and deeper under ground in course of time. On the contrary, the shoot length of the tree grows in course of time which can be measured in different time instances. So the growth of the plant can be measured using the data of shoot length which are measured at different time instances after plantation. The environmental parameters like temperature, rain fall, humidity and pollution are also play some role in production of yield. The soil, crop and distance management are taken care to produce maximum amount of yields of plant. The data of the growth of shoot length of some mustard plant at the initial stage (7,14,21 & 28 days after plantation) is available from the statistical survey by a group of scientists under the supervision of Prof. Dilip De. In this paper, initial shoot length of Ken( one type of mustard plant) has been used as an initial data. The statistical models, the methods of fuzzy logic and neural network have been tested on this mustard plant and based on error analysis (calculation of average error) that model with minimum error has been selected and can be used for the assessment of shoot length at maturity. Finally, all these methods have been tested with other type of mustard plants and the particular soft computing model with the minimum error of all types has been selected for calculating the predicted data of growth of shoot length. The shoot length at the stage of maturity of all types of mustard plants has been calculated using the statistical method on the predicted data of shoot length.

Keywords: Fuzzy time series, neural network, forecasting error, average error.

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Authors: Priyanka Malik A, Rishu Chaujar B, Mridula Gupta C, R.S. Gupta D

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In this paper, for the first time, a two-dimensional (2D) analytical drain current model for sub-100 nm multi-layered gate material engineered trapezoidal recessed channel (MLGMETRC) MOSFET: a novel design is presented and investigated using ATLAS and DEVEDIT device simulators, to mitigate the large gate leakages and increased standby power consumption that arise due to continued scaling of SiO2-based gate dielectrics. The twodimensional (2D) analytical model based on solution of Poisson-s equation in cylindrical coordinates, utilizing the cylindrical approximation, has been developed which evaluate the surface potential, electric field, drain current, switching metric: ION/IOFF ratio and transconductance for the proposed design. A good agreement between the model predictions and device simulation results is obtained, verifying the accuracy of the proposed analytical model.

Keywords: ATLAS, DEVEDIT, NJD, MLGME- TRCMOSFET.

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Authors: Fatemeh Karimi, Morteza Fathipour, Hamdam Ghanatian, Vala Fathipour

Abstract:

In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility in tensile strained silicon, the n-type FETs with strained silicon channel have better drain current compare with the pure Si one. In this structure gate dielectric divided in two parts, we have used high-κ dielectric near the source and low-κ dielectric near the drain to reduce the short channel effects. By this structure short channel effects such as FIBL will be reduced indeed by increasing the RSiGe, ID-VD characteristics will be improved. The leakage current and transfer characteristics, the threshold-voltage (Vt), the drain induced barrier height lowering (DIBL), are estimated with respect to, gate bias (VG), RSiGe and different gate dielectrics. For short channel effects, such as DIBL, gate all around strained silicon nanowire FET have similar characteristics with the pure Si one while dual dielectrics can improve short channel effects in this structure.

Keywords: SNWT (silicon nanowire transistor), Tensile Strain, high-κ dielectric, Field Induced Barrier Lowering (FIBL), cylindricalnano wire (CW), drain induced barrier lowering (DIBL).

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Authors: Yashvir Singh, Mayank Joshi

Abstract:

A lateral trench-gate power metal-oxide-semiconductor on 4H-SiC is proposed. The device consists of two separate trenches in which two gates are placed on both sides of P-body region resulting two parallel channels. Enhanced current conduction and reduced-surface-field effect in the structure provide substantial improvement in the device performance. Using two dimensional simulations, the performance of proposed device is evaluated and compare of with that of the conventional device for same cell pitch. It is demonstrated that the proposed structure provides two times higher output current, 11% decrease in threshold voltage, 70% improvement in transconductance, 70% reduction in specific ON-resistance, 52% increase in breakdown voltage, and nearly eight time improvement in figure-of-merit over the conventional device.

Keywords: 4H-SiC, lateral, trench-gate, power MOSFET.

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Authors: Sri Wahjuningsih, Hermanto, Nuryadi, Agus Budiarto, Panji Bhintoro

Abstract:

The objective of the present study was to determine the effect of different concentration of spermatozoa and length of storage in 5 0C on sperm motility. Semen was collected using artificial vagina from goat aged 2 to 2.5 years. Fresh goat semen with sperm motility ≥ 70% was used as material. Semen was divided into 4 treatments of concentration (40 x 10 6 / ml, 50 x 106/ml, 60x106/ml, 70x106/ml) with length of storage 0,12,24,36 h. in 5 0C. There were interactions (P <0.05) between concentration and length of storage on individual motility of spermatozoa. Concentration of spermatozoa and length of storage affect the motility of individual (P <0.05). It was concluded that Sperm motility will decrease with increasing concentration and length of storage in 5 0C. Concentration of sperm 40x106/ ml and length of storage 0 h in 50C showed the highest motility of spermatozoa

Keywords: Goat, Length of storage, Motility, Sperm Concentration

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Authors: Maruful H. Mazumder, Raymond I. Gilbert

Abstract:

The design specifications for calculating development and lapped splice lengths of reinforcement in concrete are derived from a conventional empirical modelling approach that correlates experimental test data using a single mathematical equation. This paper describes part of a recently completed experimental research program to assess the effects of different structural parameters on the development length requirements of modern high strength steel reinforcing bars, including the case of lapped splices in large-scale reinforced concrete members. The normalized average bond stresses for the different variations of anchorage lengths are assessed according to the general form of a typical empirical analytical model of bond and anchorage. Improved analytical modelling equations are developed in the paper that better correlate the normalized bond strength parameters with the structural parameters of an empirical model of bond and anchorage.

Keywords: Bond stress, Development length, Lapped splice length, Reinforced concrete.

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Authors: Ahmet Turer

Abstract:

Middle-gate is located in Hasankeyf, Batman dating back to 1800 BC and is one of the important historical structures in Turkey. The ancient structure has suffered major structural cracks due to aging as well as lateral pressure of a cracked rock which is predicted to be about 100 tons. The existing support system was found to be inadequate to support the load especially after a recent rock fall in the close vicinity. Concerns were increased since the existing support system that is integral with a damaged and cracked gate wall needed to be replaced by a new support system. The replacement process must be carefully monitored by crackmeters and control mechanisms should be integrated to prevent cracks to expand while the same crack width needs to be maintained after the operation. The control system and actions taken during the intervention are explained in this paper.

Keywords: structural control, crack width, replacement, support

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Authors: Muhammad H. Rais,

Abstract:

Truncated multiplier is a good candidate for digital signal processing (DSP) applications including finite impulse response (FIR) and discrete cosine transform (DCT). Through truncated multiplier a significant reduction in Field Programmable Gate Array (FPGA) resources can be achieved. This paper presents for the first time a comparison of resource utilization of Spartan-3AN and Virtex-5 implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The Virtex-5 FPGA shows significant improvement as compared to Spartan-3AN FPGA device. The Virtex-5 FPGA device shows better performance with a percentage ratio of number of occupied slices for standard to truncated multipliers is increased from 40% to 73.86% as compared to Spartan- 3AN is decreased from 68.75% to 58.78%. Results show that the anomaly in Spartan-3AN FPGA device average connection and maximum pin delay have been efficiently reduced in Virtex-5 FPGA device.

Keywords: Digital Signal Processing (DSP), FieldProgrammable Gate Array (FPGA), Spartan-3AN, TruncatedMultiplier, Virtex-5, VHDL.

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Authors: Fasil Endalamaw

Abstract:

Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.

Keywords: Efficient, gate diffusion input, high speed, low power, CMOS.

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Authors: Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy, Hiranmay Saha

Abstract:

The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.

Keywords: XOR gate, full adder, improvement in speed, area minimization, transistor count minimization.

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Authors: Ehab Hasan Ahmed Hasan Ali

Abstract:

The calculation of buckling length factor (K) for steel frames columns is a major and governing processes to determine the dimensions steel frame columns cross sections during design. The buckling length of steel frames columns has a direct effect on the cost (weight) of using cross section. A new formula is required to determine buckling length factor (K) by simplified way. In this research a new formula for buckling length factor (K) was established to determine by accurate method for a limited interval of columns ends rigidity (GA, GB). The new formula can be used ease to evaluate the buckling length factor without needing to complicated equations or difficult charts.

Keywords: Buckling length, New formula, Curve fitting, Simplification, Steel column design.

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Authors: Yngvar Berg, Mehdi Azadmehr

Abstract:

In this paper we present a linear autozeroing ultra lowvoltage amplifier. The autozeroing performed by all ULV circuits is important to reduce the impact of noise and especially avoid power supply noise in mixed signal low-voltage CMOS circuits. The simulated data presented is relevant for a 90nm TSMC CMOS process.

Keywords: Low-voltage, trans conductance amplifier, linearity, floating-gate.

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Authors: Chun-Yuan Huang, Chiao-Yang Cheng, Chun-Yem Huang, Yan-Kuin Su, James Chin-Lung Fang

Abstract:

ZnO nanostructures including nanowires, nanorods, and nanoneedles were successfully deposited on GaAs substrates, respectively, by simple two-step chemical method for the first time. A ZnO seed layer was firstly pre-coated on the O2-plasma treated substrate by sol-gel process, followed by the nucleation of ZnO nanostructures through hydrothermal synthesis. Nanostructures with different average diameter (15-250 nm), length (0.9-1.8 μm), density (0.9-16×109 cm-2) were obtained via adjusting the growth time and concentration of precursors. From the reflectivity spectra, we concluded ordered and taper nanostructures were preferential for photovoltaic applications. ZnO nanoneedles with an average diameter of 106 nm, a moderate length of 2.4 μm, and the density of 7.2×109 cm-2 could be synthesized in the concentration of 0.04 M for 18 h. Integrated with the nanoneedle array, the power conversion efficiency of single junction solar cell was increased from 7.3 to 12.2%, corresponding to a 67% improvement.

Keywords: Anti-reflection, Chemical synthesis, Solar cells, ZnO nanostructures.

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