@article{(Open Science Index):https://publications.waset.org/pdf/10346,
	  title     = {Efficient Hardware Realization of Truncated Multipliers using FPGA},
	  author    = {Muhammad H. Rais and },
	  country	= {},
	  institution	= {},
	  abstract     = {Truncated multiplier is a good candidate for digital
signal processing (DSP) applications including finite impulse
response (FIR) and discrete cosine transform (DCT). Through
truncated multiplier a significant reduction in Field Programmable
Gate Array (FPGA) resources can be achieved. This paper presents
for the first time a comparison of resource utilization of Spartan-3AN
and Virtex-5 implementation of standard and truncated multipliers
using Very High Speed Integrated Circuit Hardware Description
Language (VHDL). The Virtex-5 FPGA shows significant
improvement as compared to Spartan-3AN FPGA device. The
Virtex-5 FPGA device shows better performance with a percentage
ratio of number of occupied slices for standard to truncated
multipliers is increased from 40% to 73.86% as compared to Spartan-
3AN is decreased from 68.75% to 58.78%. Results show that the
anomaly in Spartan-3AN FPGA device average connection and
maximum pin delay have been efficiently reduced in Virtex-5 FPGA
device.},
	    journal   = {International Journal of Electrical and Computer Engineering},
	  volume    = {3},
	  number    = {9},
	  year      = {2009},
	  pages     = {1734 - 1738},
	  ee        = {https://publications.waset.org/pdf/10346},
	  url   	= {https://publications.waset.org/vol/33},
	  bibsource = {https://publications.waset.org/},
	  issn  	= {eISSN: 1307-6892},
	  publisher = {World Academy of Science, Engineering and Technology},
	  index 	= {Open Science Index 33, 2009},
	}