Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 30184
Efficient Hardware Realization of Truncated Multipliers using FPGA

Authors: Muhammad H. Rais,


Truncated multiplier is a good candidate for digital signal processing (DSP) applications including finite impulse response (FIR) and discrete cosine transform (DCT). Through truncated multiplier a significant reduction in Field Programmable Gate Array (FPGA) resources can be achieved. This paper presents for the first time a comparison of resource utilization of Spartan-3AN and Virtex-5 implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The Virtex-5 FPGA shows significant improvement as compared to Spartan-3AN FPGA device. The Virtex-5 FPGA device shows better performance with a percentage ratio of number of occupied slices for standard to truncated multipliers is increased from 40% to 73.86% as compared to Spartan- 3AN is decreased from 68.75% to 58.78%. Results show that the anomaly in Spartan-3AN FPGA device average connection and maximum pin delay have been efficiently reduced in Virtex-5 FPGA device.

Keywords: Digital Signal Processing (DSP), FieldProgrammable Gate Array (FPGA), Spartan-3AN, TruncatedMultiplier, Virtex-5, VHDL.

Digital Object Identifier (DOI):

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2209


[1] T. J. Todman, G. A. Constantinides, S. J. E. Wilton, O. Mencer, W. Luk, and P. Y. K. Cheung, "Reconfigurable computing: architectures and design methods," IEE Proc. Comput. Digit. Tech., vol. 152, no. 2, pp. 193-207, Mar. 2005.
[2] C. Maxfield, The Design Warrior-s Guide to FPGAs: Devices, Tools and flows. Newnes Publishers, MA, 2004, ch 7.
[3] E. III. Walters, M. G. Arnold, and M. J. Schulte, "Using truncated multipliers in DCT and IDCT hardware accelerators," in Proc. XIII SPIE Advanced Signal Processing Algorithms, Architectures, and Implementations, San Diego, California, 2003, pp. 573-584.
[4] M. -H. Sheu, and S. -H. Lin, "Fast compensative design approach of the approximate squaring function," IEEE J. Solid State Circuits, vol. 37, no. 1, pp. 95-97, Jan. 2002.
[5] C. R. Baugh, and B. A. Wooley, "A Two-s Complement Parallel Array Multiplication Algorithm," IEEE Trans. Comput., vol. C-22, no. 12, pp. 1045-1047, Dec. 1973.
[6] E. E. Swartzlander Jr., "Truncated Multiplication with Approximate Rounding," in Proc. 33rd Asilomar Conf. Signals, Systems, and Computers, Pacific Grove, CA, USA , 1999, Vol. 2, pp. 1480-1483.
[7] J. E. Stine, and O. M. Duverne, "Variations on Truncated Multiplication," in Proc. Euromicro Symposium on Digital System Design, Washington, 2003, pp. 112-119.
[8] W. Stallings, Cryptography and Network Security: Principles and Practices. Prentice-Hall, 4th edn., Upper Saddle River, NJ, 2006, ch 5.
[9] S. S. Kidambi, F. El-. Guibaly, and A. Antonious, "Area-Efficient Multipliers for Digital Signal Processing Applications," IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 43, no. 2, pp. 90-95, Feb. 1996.
[10] Y. C. Lim, "Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications," IEEE Trans. Comput., Vol. 41, No. 10, pp. 1333-1336, Oct. 1992.
[11] J. M. Jou, S. R. Kuang, and R. D. Chen, "Design of Low-Error Fixed- Width Multipliers for DSP Applications," IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 46, no. 6, pp. 836-842, Jun. 1999.
[12] L. D. Van, S. Wang, and W. Feng, "Design of the Lower Error Fixed- Width Multiplier and Its Application," IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, no. 10, pp. 1112-1118, Oct. 2000.
[13] A. G. M. Strollo, N. Petra, and D. DeCaro, "Dual-tree Error Compensation for High Performance Fixed-width Multipliers," IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 52, no. 8, pp. 501-507, Aug. 2005.
[14] R. Michard, A. Tisserand, and N. V-. Charvillon, "Carry Predictionan and Selection for Truncated Multiplication," in Proc Workshop Signal Processing Systems, Banff, Alta., 2006, pp. 339-344.
[15] Y. C. Liao, H. C. Chang, and C. W. Liu, "Carry Estimation for Two-s Complement Fixed-Width Multipliers," in Proc. Workshop Signal Processing Systems, Banff, Alta., 2006, pp. 345-350.
[16] S. R. Kuang, and J. P. Wang, "Low-error configurable truncated multipliers for multiply-accumulate applications," Electronics Letters, vol. 42, no. 16, pp. 904-905, Aug. 2006.
[17] V. Garofalo, N. Petra, D. DeCaro, A. G. M. Strollo, and E. Napoli, "Low error truncated multipliers for DSP applications," in Proc. 15th IEEE Int. Conf. Electronics, Circuits and Systems, St. Julien's, 2008, pp. 29-32.
[18] M. H. Rais, and S. M. Qasim, "FPGA design and implementation of standard and truncated 6×6-bit multipliers," MASAUM Journal of Computing, to be published.
[19] Xilinx, Spartan-3 FPGA family datasheet, 2008.
[20] Xilinx, Virtex-5 FPGA family overview, 2008.