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Software Digital Phase-locked Loop for Induction Motor Speed Control
Abstract:This article deals to describe the simulation investigation of the digital phase locked loop implemented in software (SDPLL). SDPLL has been developed for speed drives of an induction motor in scalar strategy. A drive was implemented and simulation results are presented to verify the robustness against motor parameter variation and regulation speed.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1054777Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 2230
 A. CHAARI., "Identification and control of a light system using the phase locked loop technique", Journal of applied Sciences, vol. 5, no. 9, pp. 1589-1596, 2005.
 N. Mahmoud, H. Ismail, and M. Othman, "Low power phaselocked loop frequency synthesizer for 2.4 GHz band zigbee" American J. of Engineering and applied Sciences, vol. 2, no. 2, pp. 337-343, 2009
 E. B. BRAIEK, and A. CHAARI, "Sampled modelling approach for stability analysis of a PLL DC Motor speed control", ACSE Journal, vol. 5, no. 4, pp. 608-613, December, 2005.
 G. C. HSIEH, and J. C. HUNG, "Phase-locked loop techniques-a survey". IEEE Transactions on Industrial Electronics, vol. 443, no. 6, pp. 609-615, December 1996.
 P. C. SEN, and M. L. MACDONALD, "Stability analysis of induction motor drives using phase-locked loop control system". IEEE Transaction on Industrial Electronics and Control Instrumentation, vol. IECI-27, no. 3, p. 147-155, August 1980.
 W. Djatmiko, and B. Sutopo, "Speed control DC motor under varying load using phase-locked loop system", Proc. of the International Conf. on Electronics, Communication, and Information CECI-2001, March 7- 8, Jakarta, 2001.
 R. MOFFAT, and M. M. BAYOUNI, "Digital phase-locked loop for induction motor speed control", IEEE Transaction on Industry Application, vol. IA-15, no. 2, pp. 176-182, March/April 1979.
 W. L. KENLY, and B. K. BOSE, "Triac speed control of three-phase induction motor with phase-locked loop regulation", IEEE Transaction on Industry Application, vol.IA-12, no.5, pp. 492-498, September/October 1976.
 D. Y. Abramovitch, "Lyapnov redesign of analog phase-lock loops", American control conference in Pitts-burg, PA, June 1989 and the IEEE transactions on communications, vol. 38, no. 12, pp. 1-6, December 1990.
 K. M. Ware, and Hae-Seung Lee, "A 200-MHz CMOS phase-locked loop with dual phase detectors", IEEE Journal of solid-state circuits, vol. 24, no. 6, pp. 1560-1568, December 1989.
 Y. M. Jhona, H. J. Ki, and S. H. Kim, "Clock recovery from 40 Gbps optical signal with optical phase-locked loop based on a terahertz optical asymmetric demultiplexer", Elsevier Science Optics Communications 220, pp. 315-319, April 2003.
 J. Crowe, and M. A. Johnson, "Towards autonomous PI control satisfying classical robustness specification", IEE Proc.-Control Theory Appl, vol. 149, no. 1, pp. 26-31,January 2002.