Search results for: double gate PN diode based tunnel field effect transistor

Authors: Mahmoud Hassanlourad, Mehran Naghizadehrokni, Vahid Molaei

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In this study, the seismic behavior of a shallow tunnel with square cross section is investigated in a two layered and elastic heterogeneous environment using numerical method. To do so, FLAC finite difference software was used. Behavioral model of the ground and tunnel structure was assumed linear elastic. Dynamic load was applied to the model for 0.2 seconds from the bottom in form of a square pulse with maximum acceleration of 1 m/s². The interface between the two layers was considered at three different levels of crest, middle, and bottom of the tunnel. The stiffness of the two upper and lower layers was considered to be varied from 10 MPa to 1000 MPa. Deformation of cross section of the tunnel due to dynamic load propagation, as well as the values of axial force and bending moment created in the tunnel structure, were examined in the three states mentioned above. The results of analyses show that heterogeneity of the environment, its stratification, and positioning of the interface of the two layers with respect to tunnel height and the stiffness ratio of the two layers have significant effects on the value of bending moment, axial force, and distortion of tunnel cross-section.

Keywords: Dynamic analysis, shallow-buried tunnel, two-layered ground.

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Authors: A. R. Salimi, M. Esmaeili, B. Salehi

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The development and extension of large cities induced a need for shallow tunnel in soft ground of building areas. Estimation of ground settlement caused by the tunnel excavation is important engineering point. In this paper, prediction of surface subsidence caused by tunneling in one section of seventh line of Tehran subway is considered. On the basis of studied geotechnical conditions of the region, tunnel with the length of 26.9km has been excavated applying a mechanized method using an EPB-TBM with a diameter of 9.14m. In this regard, settlement is estimated utilizing both analytical and numerical finite element method. The numerical method shows that the value of settlement in this section is 5cm. Besides, the analytical consequences (Bobet and Loganathan-Polous) are 5.29 and 12.36cm, respectively. According to results of this study, due tosaturation of this section, there are good agreement between Bobet and numerical methods. Therefore, tunneling processes in this section needs a special consolidation measurement and support system before the passage of tunnel boring machine.

Keywords: TBM, Subsidence, Numerical Method, Analytical Method.

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Authors: Partha Sarathi Majee, S. Bhattacharyya

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Migration of a core-shell soft particle under the influence of an external electric field in an electrolyte solution is studied numerically. The soft particle is coated with a positively charged polyelectrolyte layer (PEL) and the rigid core is having a uniform surface charge density. The Darcy-Brinkman extended Navier-Stokes equations are solved for the motion of the ionized fluid, the non-linear Nernst-Planck equations for the ion transport and the Poisson equation for the electric potential. A pressure correction based iterative algorithm is adopted for numerical computations. The effects of convection on double layer polarization (DLP) and diffusion dominated counter ions penetration are investigated for a wide range of Debye layer thickness, PEL fixed surface charge density, and permeability of the PEL. Our results show that when the Debye layer is in order of the particle size, the DLP effect is significant and produces a reduction in electrophoretic mobility. However, the double layer polarization effect is negligible for a thin Debye layer or low permeable cases. The point of zero mobility and the existence of mobility reversal depending on the electrolyte concentration are also presented.

Keywords: Debye length, double layer polarization, electrophoresis, mobility reversal, soft particle.

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Authors: Somayeh Gholami, Meysam Khakbaz

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The current-voltage characteristics of a PtSi/p-Si Schottky barrier diode was measured at the temperature of 85 K and from the forward bias region of the I-V curve, the electrical parameters of the diode were measured by three methods. The results obtained from the two methods which considered the series resistance were in close agreement with each other and from them barrier height (
), ideality factor (n) and series resistance () were found to be 0.2045 eV, 2.877 and 14.556 K
respectively. By measuring the I-V characteristics in the temperature range of 85-136 K the electrical parameters were observed to have strong dependency on temperature. The increase of barrier height and decrease of ideality factor with increasing temperature is attributed to the existence of barrier height inhomogeneities in the silicide-semiconductor structure.

Keywords: Schottky diode, barrier height, series resistance, I-V, barrier height inhomogeneities.

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Authors: S. P. Sharma, Som Nath Saha

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This paper presents the performance, based on exergy analysis of double flow solar air heaters with corrugated and flat plate absorber. A mathematical model of double flow solar air heater based on energy balance equations has been presented and the results obtained have been compared with that of a conventional flat-plate solar air heater. The double flow corrugated absorber solar air heater performs thermally better than the flat plate double flow and conventional flat-plate solar air heater under same operating conditions. However, the corrugated absorber leads to higher pressure drop thereby increasing pumping power. The results revealed that the energy and exergy efficiencies of double flow corrugated absorber solar air heater is much higher than conventional solar air heater with the concept involving of increase in heat transfer surface area and turbulence in air flow. The results indicate that the energy efficiency increases, however, exergy efficiency decreases with increase in mass flow rate.

Keywords: Corrugated absorber, double flow, exergy efficiency, solar air heater.

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Authors: Han Run-Sheng, Li Wen-Yao, Wang Feng, Liu Fei, Qiu Wen-Long, Lei Li

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Accurately positioning detection of concealed deposits or ore-bodies is one of the difficult problems in mineral exploration field. Theory calculation and exploration practices for tunnel gravity indicate that 3D high-precision Tunnel Gravity Exploration Method (TGEM) can find concealed high-density three-dimensional ore-bodies in the depth. The ore-finding breakthroughs at the depth of the Zhaotong Maoping carbonate-hosted Zn–Pb–(Ag–Ge) deposit in Northeastern Yunnan have proved that the exploration method in combination with MEAHFZ method is effective to detect concealed high-density ore-bodies. TGEM may overcome anomalous ambiguity of other geophysical methods for 3D positioning of concealed ore-bodies.

Keywords: 3D tunnel gravity exploration method, concealed high-density ore-bodies, Zn–Pb–(Ag–Ge) deposit, Zaotong Maoping, Northeastern Yunnan.

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Authors: Santanu Santra, Utpal Roy

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The most important mathematical operation for any computing system is addition. An efficient adder can be of greater assistance in designing of any arithmetic circuits. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology to create electronic circuits for computing devices and suitable candidate for next generation of computing systems. The article presents a modest approach to implement a novel XOR gate. The gate is simple in structure and powerful in terms of implementing digital circuits. By applying the XOR gate, the hardware requirement for a QCA circuit can be decrease and circuits can be simpler in level, clock phase and cell count. In order to verify the functionality of the proposed device some implementation of Half Adder (HA) and Full Adder (FA) is checked by means of computer simulations using QCA-Designer tool. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, Computing system, Majority gate, QCA, QCA Designer.

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Authors: M. Khalid Imran, Syed Masood, Milan Brandt, Sudip Bhattacharya, Jyotirmoy Mazumder

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In the present investigation, H13 tool steel has been deposited on copper alloy substrate using both CO2 and diode laser. A detailed parametric analysis has been carried out in order to find out optimum processing zone for coating defect free H13 tool steel on copper alloy substrate. Followed by parametric optimization, the microstructure and microhardness of the deposited clads have been evaluated. SEM micrographs revealed dendritic microstructure in both clads. However, the microhardness of CO2 laser deposited clad was much higher compared to diode laser deposited clad.

Keywords: CO2 laser, Diode laser, Direct Metal Deposition, Microstructure, Microhardness, Porosity.

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Authors: Aritra Acharyya, Moumita Mukherjee, J. P. Banerjee

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A generalized method for small-signal simulation of avalanche noise in Mixed Tunneling Avalanche Transit Time (MITATT) device is presented in this paper where the effect of series resistance is taken into account. The method is applied to a millimeter-wave Double Drift Region (DDR) MITATT device based on Silicon to obtain noise spectral density and noise measure as a function of frequency for different values of series resistance. It is found that noise measure of the device at the operating frequency (122 GHz) with input power density of 1010 Watt/m2 is about 35 dB for hypothetical parasitic series resistance of zero ohm (estimated junction temperature = 500 K). Results show that the noise measure increases as the value of parasitic resistance increases.

Keywords: Noise Analysis, Silicon MITATT, Admittancecharacteristics, Noise spectral density.

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Authors: Muhammad Tahir, Muhammad H. Sayyad, Dil N. Khan, Fazal Wahab

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Herein, the organic semiconductor methyl orange (MO), is investigated for the first time for its electronic applications. For this purpose, Al/MO/n-Si heterojunction is fabricated through economical cheap and simple “drop casting” technique. The currentvoltage (I-V) measurements of the device are made at room temperature under dark conditions. The I-V characteristics of Al/MO/n-Si junction exhibits asymmetrical and rectifying behavior that confirms the formation of diode. The diode parameters such as rectification ratio (RR), turn on voltage (Vturn on), reverse saturation current (I0), ideality factor (n), barrier height ( b f ), series resistance (Rs) and shunt resistance (Rsh) are determined from I-V curves using Schottky equations. These values of these parameters are also extracted and verified by applying Cheung’s functions. The conduction mechanisms are explained from the forward bias I-V characteristics using the power law.

Keywords: Electrical properties, Organic/inorganic heterojunction diode, Methyl Orange, Cheungs Functions

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Authors: M. Raciti Castelli, A. Castelli, E. Benini

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The flow field over a flat roof model building has been numerically investigated in order to determine threedimensional CFD guidelines for the calculation of the turbulent flow over a structure immersed in an atmospheric boundary layer. To this purpose, a complete validation campaign has been performed through a systematic comparison of numerical simulations with wind tunnel experimental data. Wind tunnel measurements and numerical predictions have been compared for five different vertical positions, respectively from the upstream leading edge to the downstream bottom edge of the analyzed model. Flow field characteristics in the neighborhood of the building model have been numerically investigated, allowing a quantification of the capabilities of the CFD code to predict the flow separation and the extension of the recirculation regions. The proposed calculations have allowed the development of a preliminary procedure to be used as guidance in selecting the appropriate grid configuration and corresponding turbulence model for the prediction of the flow field over a three-dimensional roof architecture dominated by flow separation.

Keywords: CFD, roof, building, wind

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Authors: S. Daneshmand, A. Ahmadi Nadooshan, C. Aghanajafi

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Traditional wind tunnel models are meticulously machined from metal in a process that can take several months. While very precise, the manufacturing process is too slow to assess a new design's feasibility quickly. Rapid prototyping technology makes this concurrent study of air vehicle concepts via computer simulation and in the wind tunnel possible. This paper described the Affects layer thickness models product with rapid prototyping on Aerodynamic Coefficients for Constructed wind tunnel testing models. Three models were evaluated. The first model was a 0.05mm layer thickness and Horizontal plane 0.1μm (Ra) second model was a 0.125mm layer thickness and Horizontal plane 0.22μm (Ra) third model was a 0.15mm layer thickness and Horizontal plane 4.6μm (Ra). These models were fabricated from somos 18420 by a stereolithography (SLA). A wing-body-tail configuration was chosen for the actual study. Testing covered the Mach range of Mach 0.3 to Mach 0.9 at an angle-of-attack range of -2° to +12° at zero sideslip. Coefficients of normal force, axial force, pitching moment, and lift over drag are shown at each of these Mach numbers. Results from this study show that layer thickness does have an effect on the aerodynamic characteristics in general; the data differ between the three models by fewer than 5%. The layer thickness does have more effect on the aerodynamic characteristics when Mach number is decreased and had most effect on the aerodynamic characteristics of axial force and its derivative coefficients.

Keywords: Aerodynamic characteristics, stereolithography, layer thickness, Rapid prototyping, surface finish.

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Authors: Jianping Hu, Xiaolei Sheng

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This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz.

Keywords: Low power, Register file, Complementarypass-transistor logic, Adiabatic logic, Single-phase power clock.

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Authors: E. Yosry, W. Fikry, A. El-henawy, M. Marzouk

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This work offers a study of new simple compact model of dual-drain Magnetic Field Effect Transistor (MAGFET) including geometrical effects and biasing dependency. An explanation of the sensitivity is investigated, involving carrier deflection as the dominant operating principle. Finally, model verification with simulation results is introduced to ensure that acceptable error of 2% is achieved.

Keywords: MAGFET, Modeling, Simulation, Split-drain.

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Authors: Heung Sun Yoon, Jong Tae Kim

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In this paper, we present an activity diagram model for double-loop control self-adaptive braking system. Since activity diagram helps to improve visibility of self-adaption. We can easily find where improvement is needed on double-loop control. Double-loop control is adopted since the design conditions and actual conditions can be different. The system is reconfigured in runtime by using double-loop control. We simulated to verify and validate our model by using MATLAB. We compared single-loop control model with double-loop control model. Simulation results show that double-loop control provides more consistent brake power control than single-loop control.

Keywords: Activity diagram, automotive, braking system, double-loop, Self-adaptive, UML, vehicle.

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Authors: H. Bentarzi, A. Zitouni

Abstract:

The reliability of the power grid depends on the successful operation of thousands of protective relays. The failure of one relay to operate as intended may lead the entire power grid to blackout. In fact, major power system failures during transient disturbances may be caused by unnecessary protective relay tripping rather than by the failure of a relay to operate. Adequate relay testing provides a first defense against false trips of the relay and hence improves power grid stability and prevents catastrophic bulk power system failures. The goal of this research project is to design and enhance the relay tester using a technology such as Field Programmable Gate Array (FPGA) card NI 7851. A PC based tester framework has been developed using Simulink power system model for generating signals under different conditions (faults or transient disturbances) and LabVIEW for developing the graphical user interface and configuring the FPGA. Besides, the interface system has been developed for outputting and amplifying the signals without distortion. These signals should be like the generated ones by the real power system and large enough for testing the relay’s functionality. The signals generated that have been displayed on the scope are satisfactory. Furthermore, the proposed testing system can be used for improving the performance of protective relay.

Keywords: Amplifier class D, FPGA, protective relay, tester.

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Authors: Hema Sandhya Jagarlamudi, Mousumi Saha, Pavan Kumar Jagarlamudi

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The use of Quantum dots is a promising emerging Technology for implementing digital system at the nano level. It is effecient for attractive features such as faster speed , smaller size and low power consumption than transistor technology. In this paper, various Combinational and sequential logical structures - HALF ADDER, SR Latch and Flip-Flop, D Flip-Flop preceding NAND, NOR, XOR,XNOR are discussed based on QCA design, with comparatively less number of cells and area. By applying these layouts, the hardware requirements for a QCA design can be reduced. These structures are designed and simulated using QCA Designer Tool. By taking full advantage of the unique features of this technology, we are able to create complete circuits on a single layer of QCA. Such Devices are expected to function with ultra low power Consumption and very high speeds.

Keywords: QCA, QCA Designer, Clock, Majority Gate

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Authors: F. Rasi Marzabadi

Abstract:

A series of experiments were carried out to study unsteady behavior of the flow field as well as the boundary layer of an airfoil oscillating in plunging motion in a subsonic wind tunnel. The measurements involved surface pressure distribution complimented with surface-mounted hot-films. The effect of leadingedge roughness that simulates surface irregularities on the wind turbine blades was also studied on variations of aerodynamic loads and boundary layer behavior.

Keywords: Boundary layer transition, plunging, reduced frequency, wind turbine.

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Authors: Rohollah. Abdollahi, Alireza. Jalilian

Abstract:

This paper presents a pulse doubling technique in a 12-pulse ac-dc converter which supplies direct torque controlled motor drives (DTCIMD-s) in order to have better power quality conditions at the point of common coupling. The proposed technique increases the number of rectification pulses without significant changes in the installations and yields in harmonic reduction in both ac and dc sides. The 12-pulse rectified output voltage is accomplished via two paralleled six-pulse ac-dc converters each of them consisting of three-phase diode bridge rectifier. An autotransformer is designed to supply the rectifiers. The design procedure of magnetics is in a way such that makes it suitable for retrofit applications where a six-pulse diode bridge rectifier is being utilized. Independent operation of paralleled diode-bridge rectifiers, i.e. dc-ripple re-injection methodology, requires a Zero Sequence Blocking Transformer (ZSBT). Finally, a tapped interphase reactor is connected at the output of ZSBT to double the pulse numbers of output voltage up to 24 pulses. The aforementioned structure improves power quality criteria at ac mains and makes them consistent with the IEEE-519 standard requirements for varying loads. Furthermore, near unity power factor is obtained for a wide range of DTCIMD operation. A comparison is made between 6- pulse, 12-pulse, and proposed converters from view point of power quality indices. Results show that input current total harmonic distortion (THD) is less than 5% for the proposed topology at various loads.

Keywords: AC–DC converter, star-connected autotransformer, power quality, 24 pulse rectifier, Pulse Doubling, direct torquecontrolled induction motor drive (DTCIMD).

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Authors: Y. Bentoutou

Abstract:

Memory Errors Detection and Correction aim to secure the transaction of data between the central processing unit of a satellite onboard computer and its local memory. In this paper, the application of a double-bit error detection and correction method is described and implemented in Field Programmable Gate Array (FPGA) technology. The performance of the proposed EDAC method is measured and compared with two different EDAC devices, using the same FPGA technology. Statistical analysis of single-event upset (SEU) and multiple-bit upset (MBU) activity in commercial memories onboard the first Algerian microsatellite Alsat-1 is given.

Keywords: Error Detection and Correction, On-board computer, small satellite missions.

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Authors: Arnab Majumdar, Srimani Sen

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In this paper, a vivid simulated study has been made on 35 GHz Ka-band window frequency in order to judge and compare the DC and high frequency properties of cubic ZnB-GaN with the existing hexagonal 4H-SiC. A flat profile p⁺pnn⁺ DDR structure of impatt is chosen and is optimized at a particular bias current density with respect to efficiency and output power taking into consideration the effect of mobile space charge also. The simulated results obtained reveals the strong potentiality of impatts based on both cubic ZnB-GaN and hexagonal 4H-SiC. The DC-to-millimeter wave conversion efficiency for cubic ZnB-GaN impatt obtained is 50% with an estimated output power of 2.83 W at an optimized bias current density of 2.5×10⁸ A/m². The conversion efficiency and estimated output power in case of hexagonal 4H-SiC impatt obtained is 22.34% and 40 W respectively at an optimum bias current density of 0.06×10⁸ A/m².

Keywords: Cubic ZnB-GaN, hexagonal 4H-SiC, Double drift impatt diode, millimeter wave, optimized bias current density, wide band gap semiconductor.

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Authors: Jong-Bae Lee, Seongsoo Lee

Abstract:

Local interconnect network (LIN) is a communication protocol that combines sensors, actuators, and processors to a functional module in automotive applications. In this paper, a LIN ver. 2.2A controller was designed in Verilog hardware description language (Verilog HDL) and implemented in field-programmable gate array (FPGA). Its operation was verified by making full-scale LIN network with the presented FPGA-implemented LIN controller, commercial LIN transceivers, and commercial processors. When described in Verilog HDL and synthesized in 0.18 μm technology, its gate size was about 2,300 gates.

Keywords: Local interconnect network, controller, transceiver, processor.

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Authors: B. M. Manjunatha, D. V. Ashok Kumar, M. Vijay Kumar

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This paper proposes five level diode clamped Z source Inverter. The existing PWM techniques used for ZSI are restricted for two level. The two level Z Source Inverter have high harmonic distortions which effects the performance of the grid connected PV system. To improve the performance of the system the number of voltage levels in the output waveform need to be increased. This paper presents comparative analysis of a five level diode clamped Z source Inverter with different carrier based Modified Pulse Width Modulation techniques. The parameters considered for comparison are output voltage, voltage gain, voltage stress across switch and total harmonic distortion when powered by same DC supply. Analytical results are verified using MATLAB.

Keywords: Diode Clamped, Pulse Width Modulation, total harmonic distortion, Z Source Inverter.

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Authors: A. Leelasantitham, B. Srisuchinwong

Abstract:

A high-frequency low-power sinusoidal quadrature oscillator is presented through the use of two 2nd-order low-pass current-mirror (CM)-based filters, a 1st-order CM low-pass filter and a CM bilinear transfer function. The technique is relatively simple based on (i) inherent time constants of current mirrors, i.e. the internal capacitances and the transconductance of a diode-connected NMOS, (ii) a simple negative resistance RN formed by a resistor load RL of a current mirror. Neither external capacitances nor inductances are required. As a particular example, a 1.9-GHz, 0.45-mW, 2-V CMOS low-pass-filter-based all-current-mirror sinusoidal quadrature oscillator is demonstrated. The oscillation frequency (f0) is 1.9 GHz and is current-tunable over a range of 370 MHz or 21.6 %. The power consumption is at approximately 0.45 mW. The amplitude matching and the quadrature phase matching are better than 0.05 dB and 0.15°, respectively. Total harmonic distortions (THD) are less than 0.3 %. At 2 MHz offset from the 1.9 GHz, the carrier to noise ratio (CNR) is 90.01 dBc/Hz whilst the figure of merit called a normalized carrier-to-noise ratio (CNRnorm) is 153.03 dBc/Hz. The ratio of the oscillation frequency (f0) to the unity-gain frequency (fT) of a transistor is 0.25. Comparisons to other approaches are also included.

Keywords: Sinusoidal quadrature oscillator, low-pass-filterbased, current-mirror bilinear transfer function, all-current-mirror, negative resistance, low power, high frequency, low distortion.

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Authors: Arash Azizi Mazreah, Mohammad Reza Sahebi, Mohammad T. Manzuri Shalmani

Abstract:

To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.

Keywords: SRAM Cell, leakage current, cell area.

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Authors: Siti Khadijah Che Osmi, Syed Mohd Ahmad

Abstract:

This paper presents a methodology to develop fragility curves for shallow tunnels so as to describe a relationship between seismic hazard and tunnel vulnerability. Emphasis is given to the influence of surrounding soil material properties because the dynamic behaviour of the tunnel mostly depends on it. Four ground properties of soils ranging from stiff to soft soils are selected. A 3D nonlinear time history analysis is used to evaluate the seismic response of the tunnel when subjected to five real earthquake ground intensities. The derived curves show the future probabilistic performance of the tunnels based on the predicted level of damage states corresponding to the peak ground acceleration. A comparison of the obtained results with the previous literature is provided to validate the reliability of the proposed fragility curves. Results show the significant role of soil properties and input motions in evaluating the seismic performance and response of shallow tunnels.

Keywords: Fragility analysis, seismic performance, tunnel lining, vulnerability.

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Authors: Cristian P. Topa, Esteban A. Valencia, Victor H. Hidalgo, Marco A. Martinez

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Wind tunnel experiments for aerodynamic profiles display numerous advantages, such as: clean steady laminar flow, controlled environmental conditions, streamlines visualization, and real data acquisition. However, the experiment instrumentation usually is expensive, and hence, each test implies a incremented in design cost. The aim of this work is to select and implement a low-cost static pressure data acquisition system for a NACA 2412 airfoil in an open cycle wind tunnel. This work compares wind tunnel experiment with Computational Fluid Dynamics (CFD) simulation and parametric analysis. The experiment was evaluated at Reynolds of 1.65 e⁵, with increasing angles from -5° to 15°. The comparison between the approaches show good enough accuracy, between the experiment and CFD, additional parametric analysis results differ widely from the other methods, which complies with the lack of accuracy of the lateral approach due its simplicity.

Keywords: Wind tunnel, low cost instrumentation, experimental testing, CFD simulation.

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Authors: Shobha Sharma, Amita Dev

Abstract:

Data driven dynamic logic is the high speed dynamic circuit with low area. The clock of the dynamic circuit is removed and data drives the circuit instead of clock for precharging purpose. This data driven dynamic nand gate is given static forward substrate biasing of Vsupply/2 as well as the substrate bias is connected to the input data, resulting in dynamic substrate bias. The dynamic substrate bias gives the shortest propagation delay with a penalty on the power dissipation. Propagation delay is reduced by 77.8% compared to the normal reverse substrate bias Data driven dynamic nand. Also dynamic substrate biased D3nand’s propagation delay is reduced by 31.26% compared to data driven dynamic nand gate with static forward substrate biasing of Vdd/2. This data driven dynamic nand gate with dynamic body biasing gives us the highest speed with no area penalty and finds its applications where power penalty is acceptable. Also combination of Dynamic and static Forward body bias can be used with reduced propagation delay compared to static forward biased circuit and with comparable increase in an average power. The simulations were done on hspice simulator with 22nm High-k metal gate strained Si technology HP models of Arizona State University, USA.

Keywords: Data driven nand gate, dynamic substrate biasing, nand gate, static substrate biasing.

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Authors: K.Ting, K. T. Chen, Y. L. Su, C. J. Chang

Abstract:

In medical therapy, laser has been widely used to conduct cosmetic, tumor and other treatments. During the process of laser irradiation, there may be thermal damage caused by excessive laser exposure. Thus, the establishment of a complete thermal analysis model is clinically helpful to physicians in reference data. In this study, porcine liver in place of tissue was subjected to laser irradiation to set up the experimental data considering the explored impact on surface thermal field and thermal damage region under different conditions of power, laser irradiation time, and distance between laser and porcine liver. In the experimental process, the surface temperature distribution of the porcine lever was measured by the infrared thermal imager. In the part of simulation, the bio heat transfer Pennes-s equation was solved by software SYSWELD applying in welding process. The double ellipsoid function as a laser source term is firstly considered in the prediction for surface thermal field and internal tissue damage. The simulation results are compared with the experimental data to validate the mathematical model established here in.

Keywords: laser infrared thermal imager, bio-heat transfer, double ellipsoid function.

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Authors: Hafiz ul Azad, Dragan V.Lazic, Waqar Shahid

Abstract:

This paper presents implementation of attitude controller for a small UAV using field programmable gate array (FPGA). Due to the small size constrain a miniature more compact and computationally extensive; autopilot platform is needed for such systems. More over UAV autopilot has to deal with extremely adverse situations in the shortest possible time, while accomplishing its mission. FPGAs in the recent past have rendered themselves as fast, parallel, real time, processing devices in a compact size. This work utilizes this fact and implements different attitude controllers for a small UAV in FPGA, using its parallel processing capabilities. Attitude controller is designed in MATLAB/Simulink environment. The discrete version of this controller is implemented using pipelining followed by retiming, to reduce the critical path and thereby clock period of the controller datapath. Pipelined, retimed, parallel PID controller implementation is done using rapidprototyping and testing efficient development tool of “system generator", which has been developed by Xilinx for FPGA implementation. The improved timing performance enables the controller to react abruptly to any changes made to the attitudes of UAV.

Keywords: Field Programmable gate array (FPGA), Hardwaredescriptive Language (HDL), PID, Pipelining, Retiming, XilinxSystem Generator.

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