Search results for: hardware errors

Authors: Rekha V. Dundur , M.V.Latte, S.Y. Kulkarni, M.K.Venkatesha

Abstract:

The advent of multi-million gate Field Programmable Gate Arrays (FPGAs) with hardware support for multiplication opens an opportunity to recreate a significant portion of the front end of a human cochlea using this technology. In this paper we describe the implementation of the cochlear filter and show that it is entirely suited to a single device XC3S500 FPGA implementation .The filter gave a good fit to real time data with efficiency of hardware usage.

Keywords: Cochlea, FPGA, IIR (Infinite Impulse Response), Multiplier.

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Authors: Yu. Menshikov

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In this paper the influence of errors of function derivatives in initial time which have been obtained by experiment (uncontrollable inaccuracy) to the results of inverse problem solution was investigated. It was shown that these errors distort the inverse problem solution as a rule near the beginning of interval where the solutions are analyzed. Several methods for removing the influence of uncontrollable inaccuracy have been suggested. 

Keywords: Inverse problems, uncontrollable inaccuracy, filtration.

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Authors: R. Damaševičius

Abstract:

System-level design based on high-level abstractions is becoming increasingly important in hardware and embedded system design. This paper analyzes meta-design techniques oriented at developing meta-programs and meta-models for well-understood domains. Meta-design techniques include meta-programming and meta-modeling. At the programming level of design process, metadesign means developing generic components that are usable in a wider context of application than original domain components. At the modeling level, meta-design means developing design patterns that describe general solutions to the common recurring design problems, and meta-models that describe the relationship between different types of design models and abstractions. The paper describes and evaluates the implementation of meta-design in hardware design domain using object-oriented and meta-programming techniques. The presented ideas are illustrated with a case study.

Keywords: Design patterns, meta-design, meta-modeling, metaprogramming.

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Authors: Kar Foo Chong, Andreas Lee Astuti, Pradeep K. Gopalakrishnan, T. Hui Teo

Abstract:

This paper describes design of a digital feedback loop for a low switching frequency dc-dc switching converters. Low switching frequencies were selected in this design. A look up table for the digital PID (proportional integrator differentiator) compensator was implemented using Altera Stratix II with built-in ADC (analog-to-digital converter) to achieve this hardware realization. Design guidelines are given for the PID compensator, high frequency DPWM (digital pulse width modulator) and moving average filter.

Keywords: dc-dc converter, FPGA, PID, power management, .

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Authors: Chaiwat Tantarangsee

Abstract:

The purposes of this study are 1) to study the frequent English writing errors of students registering the course: Reading and Writing English for Academic Purposes II, and 2) to find out the results of writing error correction by using coded indirect corrective feedback and writing error treatments. Samples include 28 2nd year English Major students, Faculty of Education, Suan Sunandha Rajabhat University. Tool for experimental study includes the lesson plan of the course; Reading and Writing English for Academic Purposes II, and tool for data collection includes 4 writing tests of short texts. The research findings disclose that frequent English writing errors found in this course comprise 7 types of grammatical errors, namely Fragment sentence, Subject-verb agreement, Wrong form of verb tense, Singular or plural noun endings, Run-ons sentence, Wrong form of verb pattern and Lack of parallel structure. Moreover, it is found that the results of writing error correction by using coded indirect corrective feedback and error treatment reveal the overall reduction of the frequent English writing errors and the increase of students’ achievement in the writing of short texts with the significance at .05.

Keywords: Coded indirect corrective feedback, error correction, and error treatment.

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Authors: Iyad F. Jafar, Sandra J. Alrawashdeh, Ban K. Alhamayel

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High level synthesis (HLS) is a process which generates register-transfer level design for digital systems from behavioral description. There are many HLS algorithms and commercial tools. However, most of these algorithms consider a behavioral description for the system when a single token is presented to the system. This approach does not exploit extra hardware efficiently, especially in the design of digital filters where common operations may exist between successive tokens. In this paper, we modify the behavioral description to process multiple tokens in parallel. However, this approach is unlike the full processing that requires full hardware replication. It exploits the presence of common operations between successive tokens. The performance of the proposed approach is better than sequential processing and approaches that of full parallel processing as the hardware resources are increased.

Keywords: Digital filters, High level synthesis, Sub-token forwarding

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Authors: Aimen Mohamed Almaloul

Abstract:

The main focus of this study is investigating the interference of Arabic in the use of English prepositions by Libyan university students. Prepositions in the tests used in the study were categorized, according to their relation to Arabic, into similar Arabic and English prepositions (SAEP), dissimilar Arabic and English prepositions (DAEP), Arabic prepositions with no English counterparts (APEC), and English prepositions with no Arabic counterparts (EPAC).

The subjects of the study were the first year university students of the English department, Sabrata Faculty of Arts, Azzawia University; both males and females, and they were 100 students. The basic tool for data collection was a test of English prepositions; students are instructed to fill in the blanks with the correct prepositions and to put a zero (0) if no preposition was needed. The test was then handed to the subjects of the study.

The test was then scored and quantitative as well as qualitative results were obtained. Quantitative results indicated the number, percentages and rank order of errors in each of the categories and qualitative results indicated the nature and significance of those errors and their possible sources. Based on the obtained results the researcher could detect that students made more errors in the EPAC category than the other three categories and these errors could be attributed to the lack of knowledge of the different meanings of English prepositions. This lack of knowledge forced the students to adopt what is called the strategy of transfer.

Keywords: Foreign language acquisition, foreign language learning, interference system, interlanguage system, mother tongue interference.

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Authors: Cyrille Lambert, Tatiana Kalganova, Emanuele Stomeo

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Since 1992, year where Hugo de Garis has published the first paper on Evolvable Hardware (EHW), a period of intense creativity has followed. It has been actively researched, developed and applied to various problems. Different approaches have been proposed that created three main classifications: extrinsic, mixtrinsic and intrinsic EHW. Each of these solutions has a real interest. Nevertheless, although the extrinsic evolution generates some excellent results, the intrinsic systems are not so advanced. This paper suggests 3 possible solutions to implement the run-time configuration intrinsic EHW system: FPGA-based Run-Time Configuration system, JBits-based Run-Time Configuration system and Multi-board functional-level Run-Time Configuration system. The main characteristic of the proposed architectures is that they are implemented on Field Programmable Gate Array. A comparison of proposed solutions demonstrates that multi-board functional-level run-time configuration is superior in terms of scalability, flexibility and the implementation easiness.

Keywords: Evolvable hardware, evolutionary computation, FPGA systems.

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Authors: Konstantin Movsovic, Emanuele Stomeo, Tatiana Kalganova

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The evolutionary design of electronic circuits, or evolvable hardware, is a discipline that allows the user to automatically obtain the desired circuit design. The circuit configuration is under the control of evolutionary algorithms. Several researchers have used evolvable hardware to design electrical circuits. Every time that one particular algorithm is selected to carry out the evolution, it is necessary that all its parameters, such as mutation rate, population size, selection mechanisms etc. are tuned in order to achieve the best results during the evolution process. This paper investigates the abilities of evolution strategy to evolve digital logic circuits based on programmable logic array structures when different mutation rates are used. Several mutation rates (fixed and variable) are analyzed and compared with each other to outline the most appropriate choice to be used during the evolution of combinational logic circuits. The experimental results outlined in this paper are important as they could be used by every researcher who might need to use the evolutionary algorithm to design digital logic circuits.

Keywords: Evolvable hardware, evolutionary algorithm, digitallogic circuit, mutation rate.

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Authors: Iqbalur Rahman, Miftahur Rahman, Abul L Haque, Mostafizur Rahman,

Abstract:

In this paper, RSA encryption algorithm and its hardware implementation in Xilinx-s Virtex Field Programmable Gate Arrays (FPGA) is analyzed. The issues of scalability, flexible performance, and silicon efficiency for the hardware acceleration of public key crypto systems are being explored in the present work. Using techniques based on the interleaved math for exponentiation, the proposed RSA calculation architecture is compared to existing FPGA-based solutions for speed, FPGA utilization, and scalability. The paper covers the RSA encryption algorithm, interleaved multiplication, Miller Rabin algorithm for primality test, extended Euclidean math, basic FPGA technology, and the implementation details of the proposed RSA calculation architecture. Performance of several alternative hardware architectures is discussed and compared. Finally, conclusion is drawn, highlighting the advantages of a fully flexible & parameterized design.

Keywords: Crypto Accelerator, FPGA, Public Key Cryptography, RSA.

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Authors: Balasundaram Prasaant, Ploix Stephane, Delinchant Benoit, Muresan Cristian

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Hardware in Loop (HIL) testing is done to test and validate a particular product especially in building technology. When it comes to building technology, it is more important to test the products for their efficiency. The test rig in the HIL simulator may contribute to some uncertainties on measured efficiency. The uncertainties include physical uncertainties and scenario-based uncertainties. In this paper, a simple uncertainty analysis framework for an HIL setup is shown considering only the physical uncertainties. The entire modeling of the HIL setup is done in Dymola. The uncertain sources are considered based on available knowledge of the components and also on expert knowledge. For the propagation of uncertainty, Monte Carlo Simulation is used since it is the most reliable and easy to use. In this article it is shown how an HIL setup can be modeled and how uncertainty propagation can be performed on it. Such an approach is not common in building energy analysis.

Keywords: Energy in Buildings, Hardware in Loop, Modelica (Dymola), Monte Carlo Simulation, Uncertainty Propagation.

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Authors: Z. Karakus, Z. Ozer

Abstract:

Nurses are responsible for the care and treatment of individuals, as well as health maintenance and education. Medication administration is an important part of health promotion. The administration of a medicine is a common but important clinical procedure for nurses because of its complex structure. Therefore, medication errors are inevitable for nurses or nursing students. Medication errors can cause ineffective treatment, patient’s prolonged hospital stay, disablement or death. Additionally, medication errors affect the global economy adversely by increasing health costs. Hence, preventing or decreasing of medication errors is a critical and essential issue in nursing. Nurse educators are in pursuit of new teaching methods to teach students significance of medication application. In the light of technological developments of this age, e-learning has started to be accepted as an important teaching method. E-learning is the use of electronic media and information and communication technologies in education. It has advantages such as flexibility of time and place, lower costs, faster delivery and lower environmental impact. Students can make their own schedule and decide the learning method. This study is conducted to determine the impact of e-learning on medication administration of nursing students.

Keywords: E-Learning, Medication Administration, Nursing, Nursing Students.

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Authors: Sung Kyu Kim, Yong Soo Kim

Abstract:

Safety instrumented systems (SISs) are becoming increasingly complex and the proportion of programmable electronic parts is growing. The IEC 61508 global standard was established to ensure the functional safety of SISs, but it was expressed in highly macroscopic terms. This study introduces an evaluation process for hardware safety integrity levels through failure modes, effects, and diagnostic analysis (FMEDA).FMEDA is widely used to evaluate safety levels, and it provides the information on failure rates and failure mode distributions necessary to calculate a diagnostic coverage factor for a given component. In our evaluation process, the components of the SIS subsystem are first defined in terms of failure modes and effects. Then, the failure rate and failure mechanism distribution are assigned to each component. The safety mode and detectability of each failure mode are determined for each component. Finally, the hardware safety integrity level is evaluated based on the calculated results.

Keywords: Safety instrumented system; Safety integrity level; Failure modes, effects, and diagnostic analysis; IEC 61508.

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Authors: M. A. Sedghamiz, S. Raeissi

Abstract:

This study presents three different approaches to estimate bubble point pressures for the binary system of CO2 and ethyl palmitate fatty acid ethyl ester. The first method involves the Peng-Robinson (PR) Equation of State (EoS) with the conventional mixing rule of Van der Waals. The second approach involves the PR EOS together with the Wong Sandler (WS) mixing rule, coupled with the UNIQUAC GE model. In order to model the bubble point pressures with this approach, the volume and area parameter for ethyl palmitate were estimated by the Hansen group contribution method. The last method involved the Peng-Robinson, combined with the Wong-Sandler method, but using NRTL as the GE model. Results using the Van der Waals mixing rule clearly indicated that this method has the largest errors among all three methods, with errors in the range of 3.96-6.22%. The PR-WS-UNIQUAC method exhibited small errors, with average absolute deviations between 0.95 to 1.97 percent. The PR-WS-NRTL method led to the least errors, where average absolute deviations ranged between 0.65-1.7%.

Keywords: Bubble pressure, Gibbs excess energy model, mixing rule, CO2 solubility, ethyl palmitate.

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Authors: May Phyo Thwal, Khin Htay Kyi, Kyaw Swar Soe

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According to the density of the chips, designers are trying to put so any facilities of computational and storage on single chips. Along with the complexity of computational and storage circuits, the designing, testing and debugging become more and more complex and expensive. So, hardware design will be built by using very high speed hardware description language, which is more efficient and cost effective. This paper will focus on the implementation of 32-bit ALU design based on Verilog hardware description language. Adder and subtracter operate correctly on both unsigned and positive numbers. In ALU, addition takes most of the time if it uses the ripple-carry adder. The general strategy for designing fast adders is to reduce the time required to form carry signals. Adders that use this principle are called carry look- ahead adder. The carry look-ahead adder is to be designed with combination of 4-bit adders. The syntax of Verilog HDL is similar to the C programming language. This paper proposes a unified approach to ALU design in which both simulation and formal verification can co-exist.

Keywords: Addition, arithmetic logic unit, carry look-ahead adder, Verilog HDL.

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Authors: Ionel Zagan, Vasile Gheorghita Gaitan

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Minimizing the response time to asynchronous events in a real-time system is an important factor in increasing the speed of response and an interesting concept in designing equipment fast enough for the most demanding applications. The present article will present the results regarding the validation of the nMPRA (Multi Pipeline Register Architecture) architecture using the FPGA Virtex-7 circuit. The nMPRA concept is a hardware processor with the scheduler implemented at the processor level; this is done without affecting a possible bus communication, as is the case with the other CPU solutions. The implementation of static or dynamic scheduling operations in hardware and the improvement of handling interrupts and events by the real-time executive described in the present article represent a key solution for eliminating the overhead of the operating system functions. The nMPRA processor is capable of executing a preemptive scheduling, using various algorithms without a software scheduler. Therefore, we have also presented various scheduling methods and algorithms used in scheduling the real-time tasks.

Keywords: nMPRA architecture, pipeline processor, preemptive scheduling, real-time system.

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Authors: Kyung-Jung Lee, Young-Hun Ki, Hyun-Sik Ahn

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In this paper, we propose a hardware and software design method for automotive Electronic Control Units (ECU) considering the functional safety. The proposed ECU is considered for the application to Electro-Mechanical Actuator systems and the validity of the design method is shown by the application to the Electro-Mechanical Brake (EMB) control system which is used as a brake actuator in Brake-By-Wire (BBW) systems. The importance of a functional safety-based design approach to EMB ECU design has been emphasized because of its safety-critical functions, which are executed with the aid of many electric actuators, sensors, and application software. Based on hazard analysis and risk assessment according to ISO26262, the EMB system should be ASIL-D-compliant, the highest ASIL level. To this end, an external signature watchdog and an Infineon 32-bit microcontroller TriCore are used to reduce risks considering common-cause hardware failure. Moreover, a software design method is introduced for implementing functional safety-oriented monitoring functions based on an asymmetric dual core architecture considering redundancy and diversity. The validity of the proposed ECU design approach is verified by using the EMB Hardware-In-the-Loop (HILS) system, which consists of the EMB assembly, actuator ECU, a host PC, and a few debugging devices. Furthermore, it is shown that the existing sensor fault tolerant control system can be used more effectively for mitigating the effects of hardware and software faults by applying the proposed ECU design method.

Keywords: BBW (Brake-By-wire), EMB (Electro-Mechanical Brake), Functional Safety, ISO26262.

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Authors: Youngjae Jin, Daeshik Kim

Abstract:

This paper describes a cycle accurate simulation results of weight values learned by an auto-encoder behavior model in terms of pre-route simulation. Given the results we visualized the first layer representations with natural images. Many common deep learning threads have focused on learning high-level abstraction of unlabeled raw data by unsupervised feature learning. However, in the process of handling such a huge amount of data, the learning method’s computation complexity and time limited advanced research. These limitations came from the fact these algorithms were computed by using only single core CPUs. For this reason, parallel-based hardware, FPGAs, was seen as a possible solution to overcome these limitations. We adopted and simulated the ready-made auto-encoder to design a behavior model in VerilogHDL before designing hardware. With the auto-encoder behavior model pre-route simulation, we obtained the cycle accurate results of the parameter of each hidden layer by using MODELSIM. The cycle accurate results are very important factor in designing a parallel-based digital hardware. Finally this paper shows an appropriate operation of behavior model based pre-route simulation. Moreover, we visualized learning latent representations of the first hidden layer with Kyoto natural image dataset.

Keywords: Auto-encoder, Behavior model simulation, Digital hardware design, Pre-route simulation, Unsupervised feature learning.

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Authors: Jooho Hwang, Chang-Kyu Song, Chun-Hong Park

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This paper describes a method to measure and compensate a 4 axes ultra-precision machine tool that generates micro patterns on the large surfaces. The grooving machine is usually used for making a micro mold for many electrical parts such as a light guide plate for LCD and fuel cells. The ultra precision machine tool has three linear axes and one rotational table. Shaping is usually used to generate micro patterns. In the case of 50 μm pitch and 25 μm height pyramid pattern machining with a 90° wedge angle bite, one of linear axis is used for long stroke motion for high cutting speed and other linear axis are used for feeding. The triangular patterns can be generated with many times of long stroke of one axis. Then 90° rotation of work piece is needed to make pyramid patterns with superposition of machined two triangular patterns. To make a two dimensional positioning error, straightness of two axes in out of plane, squareness between the each axis are important. Positioning errors, straightness and squarness were measured by laser interferometer system. Those were compensated and confirmed by ISO230-6. One of difficult problem to measure the error motions is squareness or parallelism of axis between the rotational table and linear axis. It was investigated by simultaneous moving of rotary table and XY axes. This compensation method is introduced in this paper.

Keywords: Ultra-precision machine tool, muti-axis errors, squraness, positioning errors.

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Authors: Rehab Abdullah Shendi

Abstract:

The use of customised soft-core processors in which instructions can be integrated into a system in application hardware is increasing in the Field Programmable Gate Array (FPGA) field. Specifically, the partial run-time reconfiguration of FPGAs in specialised processors for a particular domain can be very beneficial. In this report, the design and implementation for the customisation of a soft-core MIPS processor using an FPGA and partial reconfiguration (PR) of FPGA technology will be addressed to achieve efficient resource use. This can be achieved using a PR design flow that helps the design fit into a smaller device. Moreover, the impact of static power consumption could be reduced due to runtime reconfiguration. This will be done by configurable custom instructions implemented in the hardware as an extension on the MIPS CPU. The aim of this project is to investigate the PR of FPGAs for run-time adaptations of the instruction set of a soft-core CPU, including the integration of custom instructions and the exploration of the potential to use the MultiBoot feature available in Xilinx FPGAs to carry out the PR process. The system will be evaluated and tested on a Nexus 3 development board featuring a Xilinx Spartran-6 FPGA. The system will be able to load reconfigurable custom instructions dynamically into user programs with the help of the trap handler when the custom instruction is called by the MIPS CPU. The results of this experiment demonstrate that custom instructions in hardware can speed up a certain function and many instructions can be saved when compared to a software implementation of the same function. Implementing custom instructions in hardware is perfectly possible and worth exploring.

Keywords: Customisation, FPGA, MIPS, partial reconfiguration.

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Authors: Amit Kumar, Himanshu Singal, Arnav Bhavsar

Abstract:

In this modern era of automation, most of the academic exams and competitive exams are Multiple Choice Questions (MCQ). The responses of these MCQ based exams are recorded in the Optical Mark Reader (OMR) sheet. Evaluation of the OMR sheet requires separate specialized machines for scanning and marking. The sheets used by these machines are special and costs more than a normal sheet. Available process is non-economical and dependent on paper thickness, scanning quality, paper orientation, special hardware and customized software. This study tries to tackle the problem of evaluating the OMR sheet without any special hardware and making the whole process economical. We propose an image processing based algorithm which can be used to read and evaluate the scanned OMR sheets with no special hardware required. It will eliminate the use of special OMR sheet. Responses recorded in normal sheet is enough for evaluation. The proposed system takes care of color, brightness, rotation, little imperfections in the OMR sheet images.

Keywords: OMR, image processing, hough circle transform, interpolation, detection, Binary Thresholding.

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Authors: Wen-Yuh Jywe, Bor-Jeng Lin, Jing-Chung Shen, Jeng-Dao Lee, Hsueh-Liang Huang, Tung-Hsien Hsieh

Abstract:

In this study, a simple 2-D measurement system based on optical design was developed to measure the motion errors of the linear guideway. Compared with the transitional methods about the linear guideway for measuring the motion errors, our proposed 2-D optical measurement system can simultaneously measure horizontal and vertical running straightness errors for the linear guideway.

The performance of the 2-D optical measurement system is verified by experimental results. The standard deviation of the 2-D optical measurement system is about 0.4μm in the measurement range of 100 mm. The maximum measuring speed of the proposed automatic measurement instrument is 1 m/sec.

Keywords: 2-D measurement, linear guideway, motion errors, running straightness.

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Authors: Kazutaka Kobayashi, Norihiko Yoshida, Shuji Narazaki

Abstract:

This paper presents a dynamic adaptation scheme for the frequency of inter-deme migration in distributed genetic algorithms (GA), and its VLSI hardware design. Distributed GA, or multi-deme-based GA, uses multiple populations which evolve concurrently. The purpose of dynamic adaptation is to improve convergence performance so as to obtain better solutions. Through simulation experiments, we proved that our scheme achieves better performance than fixed frequency migration schemes.

Keywords: Genetic algorithms, dynamic adaptation, VLSI hardware.

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Authors: Jarrod Trevathan, Trina Myers

Abstract:

Proprietary sensor network systems are typically expensive, rigid and difficult to incorporate technologies from other vendors. When using competing and incompatible technologies, a non-proprietary system is complex to create because it requires significant technical expertise and effort, which can be more expensive than a proprietary product. This paper presents the Sensor Abstraction Layer (SAL) that provides middleware architectures with a consistent and uniform view of heterogeneous sensor networks, regardless of the technologies involved. SAL abstracts and hides the hardware disparities and specificities related to accessing, controlling, probing and piloting heterogeneous sensors. SAL is a single software library containing a stable hardware-independent interface with consistent access and control functions to remotely manage the network. The end-user has near-real-time access to the collected data via the network, which results in a cost-effective, flexible and simplified system suitable for novice users. SAL has been used for successfully implementing several low-cost sensor network systems.

Keywords: Sensor networks, hardware abstraction, middleware integration platform, sensor web enablement.

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Authors: Muhammad Yasir Wadood, Fatemeh Babaeian

Abstract:

By developing ultra-wideband (UWB) systems, there is a high demand for UWB filters with low insertion loss, wide bandwidth, and having a planar structure which is compatible with other components of the UWB system. A microstrip interdigital filter is a great option for designing UWB filters. However, the presence of via holes in this structure creates difficulties in the fabrication procedure of the filter. Especially in the higher frequency band, any misalignment of the drilled via hole with the Microstrip stubs causes large errors in the measurement results compared to the desired results. Moreover, in this case (high-frequency designs), the line width of the stubs are very narrow, so highly precise small via holes are required to be implemented, which increases the cost of fabrication significantly. Also, in this case, there is a risk of having fabrication errors. To combat this issue, in this paper, a via-less UWB microstrip filter is proposed which is designed based on a modification of a conventional inter-digital bandpass filter. The novel approaches in this filter design are 1) replacement of each via hole with a quarter-wavelength open circuit stub to avoid the complexity of manufacturing, 2) using a bend structure to reduce the unwanted coupling effects and 3) minimising the size. Using the proposed structure, a UWB filter operating in the frequency band of 3.9-6.6 GHz (1-dB bandwidth) is designed and fabricated. The promising results of the simulation and measurement are presented in this paper. The selected substrate for these designs was Rogers RO4003 with a thickness of 20 mils. This is a common substrate in most of the industrial projects. The compact size of the proposed filter is highly beneficial for applications which require a very miniature size of hardware.

Keywords: Band-pass filters, inter-digital filter, microstrip, via-less.

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Authors: Ridha Ghayoula, ElAmjed Hajlaoui, Talel Korkobi, Mbarek Traii, Hichem Trabelsi

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In this paper, the hardware implementation of the RSA public-key cryptographic algorithm is presented. The RSA cryptographic algorithm is depends on the computation of repeated modular exponentials. The Montgomery algorithm is used and modified to reduce hardware resources and to achieve reasonable operating speed for FPGA. An efficient architecture for modular multiplications based on the array multiplier is proposed. We have implemented a RSA cryptosystem based on Montgomery algorithm. As a result, it is shown that proposed architecture contributes to small area and reasonable speed.

Keywords: RSA, Cryptosystem, Montgomery, Implementation.FPGA.

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Authors: Kar Foo Chong, Pradeep K. Gopalakrishnan, T. Hui Teo

Abstract:

There are multiple ways to implement a decimator filter. This paper addresses usage of CIC (cascaded-integrator-comb) filter and HB (half band) filter as the decimator filter to reduce the frequency sample rate by factor of 64 and detail of the implementation step to realize this design in hardware. Low power design approach for CIC filter and half band filter will be discussed. The filter design is implemented through MATLAB system modeling, ASIC (application specific integrated circuit) design flow and verified using a FPGA (field programmable gate array) board and MATLAB analysis.

Keywords: CIC filter, decimation filter, half-band filter, lowpower.

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Authors: Adnan Z. Mkhelif

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The production of number forms in English tends to be problematic for Iraqi learners of English as a foreign language (EFL), even at the undergraduate level. To help better understand and consequently address this problem, it is important to identify its sources. This study aims at: (1) statistically analysing Iraqi EFL undergraduates' performance in the production of number forms in English; (2) classifying learners' errors in terms of their possible major causes; and (3) outlining some pedagogical recommendations relevant to the teaching of number forms in English. It is hypothesized in this study that (1) Iraqi EFL undergraduates still face problems in the production of number forms in English and (2) errors pertaining to the context of learning are more numerous than those attributable to the other possible causes. After reviewing the literature available on the topic, a written test comprising 50 items has been constructed and administered to a randomly chosen sample of 50 second-year college students from the Department of English, College of Education, Wasit University. The findings of the study showed that Iraqi EFL undergraduates still face problems in the production of number forms in English and that the possible major sources of learners’ errors can be arranged hierarchically in terms of the percentages of errors to which they can be ascribed as follows: (1) context of learning (50%), (2) intralingual transfer (37%), and (3) interlingual transfer (13%). It is hoped that the implications of the study findings will be beneficial to researchers, syllabus designers, as well as teachers of English as a foreign/second language.

Keywords: L2 morphology, L2 number forms, L2 vocabulary learning, productive knowledge.

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Authors: Jieh-Shian Young, Chan Wei Hsu

Abstract:

This paper mainly studies the analyses of parameters in the intersection collision avoidance (ICA) system based on the radar sensors. The parameters include the positioning errors, the repeat period of the radar sensor, the conditions of potential collisions of two cross-path vehicles, etc. The analyses of the parameters can provide the requirements, limitations, or specifications of this ICA system. In these analyses, the positioning errors will be increased as the measured vehicle approach the intersection. In addition, it is not necessary to implement the radar sensor in higher position since the positioning sensitivities become serious as the height of the radar sensor increases. A concept of the safety buffer distances for front and rear of the measured vehicle is also proposed. The conditions for potential collisions of two cross-path vehicles are also presented to facilitate the computation algorithm.

Keywords: Intersection Collision Avoidance (ICA), Positioning Errors, Radar Sensors, Sensitivity of Positioning.

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Authors: Abhijit Mitra, Harpreet Singh Dhillon

Abstract:

We present a novel scheme to evaluate sinusoidal functions with low complexity and high precision using cubic spline interpolation. To this end, two different approaches are proposed to find the interpolating polynomial of sin(x) within the range [- π , π]. The first one deals with only a single data point while the other with two to keep the realization cost as low as possible. An approximation error optimization technique for cubic spline interpolation is introduced next and is shown to increase the interpolator accuracy without increasing complexity of the associated hardware. The architectures for the proposed approaches are also developed, which exhibit flexibility of implementation with low power requirement.

Keywords: Arithmetic, spline interpolator, hardware design, erroranalysis, optimization methods.

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