%0 Journal Article
	%A Sung Kyu Kim and  Yong Soo Kim
	%D 2013
	%J International Journal of Industrial and Manufacturing Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 76, 2013
	%T Evaluation Process for the Hardware Safety Integrity Level
	%U https://publications.waset.org/pdf/5621
	%V 76
	%X Safety instrumented systems (SISs) are becoming
increasingly complex and the proportion of programmable electronic
parts is growing. The IEC 61508 global standard was established to
ensure the functional safety of SISs, but it was expressed in highly
macroscopic terms. This study introduces an evaluation process for
hardware safety integrity levels through failure modes, effects, and
diagnostic analysis (FMEDA).FMEDA is widely used to evaluate
safety levels, and it provides the information on failure rates and
failure mode distributions necessary to calculate a diagnostic coverage
factor for a given component. In our evaluation process, the
components of the SIS subsystem are first defined in terms of failure
modes and effects. Then, the failure rate and failure mechanism
distribution are assigned to each component. The safety mode and
detectability of each failure mode are determined for each component.
Finally, the hardware safety integrity level is evaluated based on the
calculated results.
	%P 547 - 551