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Feasibility of the Evolutionary Algorithm using Different Behaviours of the Mutation Rate to Design Simple Digital Logic Circuits

Authors: Tatiana Kalganova, Emanuele Stomeo, Konstantin Movsovic

Abstract:

The evolutionary design of electronic circuits, or evolvable hardware, is a discipline that allows the user to automatically obtain the desired circuit design. The circuit configuration is under the control of evolutionary algorithms. Several researchers have used evolvable hardware to design electrical circuits. Every time that one particular algorithm is selected to carry out the evolution, it is necessary that all its parameters, such as mutation rate, population size, selection mechanisms etc. are tuned in order to achieve the best results during the evolution process. This paper investigates the abilities of evolution strategy to evolve digital logic circuits based on programmable logic array structures when different mutation rates are used. Several mutation rates (fixed and variable) are analyzed and compared with each other to outline the most appropriate choice to be used during the evolution of combinational logic circuits. The experimental results outlined in this paper are important as they could be used by every researcher who might need to use the evolutionary algorithm to design digital logic circuits.

Keywords: Evolvable hardware, evolutionary algorithm, mutation rate, digitallogic circuit

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1075204

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References:


[1] N. Forbes. "Evolution on a chip: evolvable hardware aims to optimize circuit design". Computing in Science & Engineering
[see also IEEE Computational Science and Engineering]. Volume 3, Issue 3, May-June 2001 Page(s):6 - 10.
[2] G. W. Greenwood, "On the practicality of using intrinsic reconfiguration for fault recovery." IEEE Transactions on Evolutionary Computation. Volume 9, Issue 4. Pages: 398 - 405.
[3] X. Yao, T. Higuchi. "Promises and challenges of evolvable hardware" IEEE Trans. Systems, Man and Cybernetics, Part C, vol. 29, Pages. 87 - 97, February 1999.
[4] J. Holland. Adaptation in Natural and Artificial Systems. Ann Arbor, MI: University of Michigan Press, 1975.
[5] I. Rechenberg, "Evolution Strategy", in J. Zurada, R. Marks II, and C. Robinson (Eds.), Computational Intelligence: Imitating Life, 1994, pp. 147-159.
[6] J. R Koza. Genetic Programming: On the Programming of Computers by Means of Natural selection. ISBN 0-262-11170-5. MIT Press, 1992.
[7] E. Stomeo, T. Kalganova, C. Lambert. "Generalized Disjunction Decomposition for Evolvable Hardware" IEEE Trans. Systems, Man and Cybernetics, Part B. 2006 (Accepted for publication).
[8] Lee Altenberg "The Evolution of Evolvability in Genetic Programming". Chapter 3 in Advances in Genetic Programming, ed. Kenneth Kinnear. pp. 47-74. MIT Press, Cambridge, 1994.
[9] M. Srinivas, L. M. Patnaik; "Genetic algorithms: a survey". IEEE JNL Computer, Volume: 27, Issue: 6, June 1994. Pages: 17 - 26.
[10] T. Kalganova; "Bidirectional incremental evolution in extrinsic evolvable hardware". Proc. of the Second NASA/DoD Workshop on Evolvable Hardware. IEEE Computer Society, 13-15 July 2000. Pages:65 - 74
[11] J. Torresen, "Increased complexity evolution applied to evolvable hardware", ANNIE'99, November 1999, St. Louis, USA.
[12] E. Stomeo, T. Kalganova, C. Lambert. "Mutation Rate for Evolvable Hardware". International Conference on Computational Intelligence - ICCI 2005 August 26-28, 2005. Prague, Czech Republic. Pages: 117 - 124.
[13] E. Stomeo, T. Kalganova, C. Lambert "Chose the Right Mutation Rate for Better Evolve Combinational Logic Circuits". International Journal of Computational Intelligence (IJCI) (accepted for publication).
[14] S. Bleuler, M. Brack, L. Thiele, E. Zitzler. "Multiobjective genetic programming: reducing bloat using SPEA2". Proceedings of the 2001 Congress on Evolutionary Computation, 2001.Volume 1, 27-30 May 2001. Page: 536 - 543.
[15] M. Oltean. "Solving even-parity problems using traceless genetic programming". Congress on Evolutionary Computation, 2004. CEC2004. Volume 2. 19-23 June 2004 Page: 1813 - 1819.
[16] A. James Walker and Julian F. Miller, "Evolution and Acquisition of Modules in Cartesian Genetic Programming", Proceedings of EuroGp2004. Lecture Notes in Computer Science, Volume 3003 / 2004. Pages: 187 - 197. Maarten Keijzer, Una-May O-Reilly, Simon M. Lucas, Ernesto Costa, Terence Soule (Eds.).
[17] T. Bäck, F. Hoffmeister, and H. P. Schwefel. "A survey of evolutionary strategies". In R. Belew and L. Booker, editors, Proceedings of the 4th International Conference on Genetic Algorithms, San Francisco, CA, 1991. Morgan Kaufmann. Pages 2-9.
[18] H.-P. Schwefel. Numerical Optimization of Computer Models. John Wiley & Sons, Chichester, UK, 1981.
[19] E. Stomeo, T. Kalganova, C. Lambert, N. Lipnitsakya, Y. Yatskevich. "On Evolution of Relatively Large Combinational Logic Circuits". The IEEE 2005 NASA/DoD Conference on Evolvable Hardware. June 29 - July 1, 2005, Washington DC, USA. IEEE Computer Society. Pages 59 - 66.