Search results for: power circuit breakers

Authors: Koyu Chinen, Haruka Mikamori

Abstract:

A new multi-step comprehensive experience-based learning program was developed and carried out so that the students understood about what was the principle of the circuit function and how the designed circuit was used in actual advanced applications.

Keywords: Electronic circuit education, Experience based learning, Comprehensive education,

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Authors: Gianluca Cornetta, Abdellah Touhafi, David J. Santos, Jose Manuel Vazquez

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A direct downconversion receiver implemented in 0.13 μm 1P8M process is presented. The circuit is formed by a single-end LNA, an active balun for conversion into balanced mode, a quadrature double-balanced passive switch mixer and a quadrature voltage-controlled oscillator. The receiver operates in the 2.4 GHz ISM band and complies with IEEE 802.15.4 (ZigBee) specifications. The circuit exhibits a very low noise figure of only 2.27 dB and dissipates only 14.6 mW with a 1.2 V supply voltage and is hence suitable for low-power applications.

Keywords: LNA, Active Balun, Passive Mixer, VCO, IEEE 802.15.4(ZigBee).

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Authors: Vinod Kumar Khera, R. K. Sharma, A. K. Gupta

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Power dissipation increases exponentially during test mode as compared to normal operation of the circuit. In extreme cases, test power is more than twice the power consumed during normal operation mode. Test vector generation scheme is key component in deciding the power hungriness of a circuit during testing. Test vector count and consequent leakage current are functions of test vector generation scheme. Fault based test vector count optimization has been presented in this work. It helps in reducing test vector count and the leakage current. In the presented scheme, test vectors have been reduced by extracting essential child vectors. The scheme has been tested experimentally using stuck at fault models and results ensure the reduction in test vector count.

Keywords: Low power VLSI testing, independent fault, essential faults, test vector reduction.

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Authors: P. Prasad Rao, K. Lal Kishore

Abstract:

Pipeline ADCs are becoming popular at high speeds and with high resolution. This paper discusses the options of number of bits/stage conversion techniques in pipelined ADCs and their effect on Area, Speed, Power Dissipation and Linearity. The basic building blocks like op-amp, Sample and Hold Circuit, sub converter, DAC, Residue Amplifier used in every stage is assumed to be identical. The sub converters use flash architectures. The design is implemented using 0.18

Keywords: 1.5 bits/stage, Conversion Frequency, Redundancy Switched Capacitor Sample and Hold Circuit

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Authors: Jun Yu, Yat-Hei Lam, Boris Grinberg, Kevin Chai Tshun Chuan

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This paper presents a 5-V to 30-V current-mode boost converter for powering the drive circuit of a micro-electro-mechanical sensor. The design of a transconductance amplifier and an integrated current sensing circuit are presented. In addition, essential building blocks for power-on protection such as a soft-start and clamp block and supply and clock ready block are discussed in details. The chip is fabricated in a 0.18-μm CMOS process. Measurement results show that the soft-start and clamp block can effectively limit the inrush current during startup and protect the boost converter from startup failure.

Keywords: Boost Converter, Current Sensing, Power-on protection, Step-up Converter, Soft-start.

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Authors: Y. Kobori, L. Xing, H. Gao, N.Onozawa, S. Wu, S. N. Mohyar, Z. Nosker, H. Kobayashi, N. Takai, K. Niitsu

Abstract:

This paper proposes two types of non-isolated direct AC-DC converters. First, it shows a buck-boost converter with an H-bridge, which requires few components (three switches, two diodes, one inductor and one capacitor) to convert AC input to DC output directly. This circuit can handle a wide range of output voltage. Second, a direct AC-DC buck converter is proposed for lower output voltage applications. This circuit is analyzed with output voltage of 12V. We describe circuit topologies, operation principles and simulation results for both circuits.

Keywords: AC-DC converter, Buck-boost converter, Buck converter, PFC, BCM PFC circuit.

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Authors: Pedro Luis Ferrer Penalver, Edmundo da Silva Braga

Abstract:

In this paper, the performance of a simple surge protection for a direct current circuit was simulated. The protection circuit was developed from modified electric macro models of a gas discharge tube and a transient voltage suppressor diode. Moreover, a combination wave generator circuit was used as source of energy surges. The simulations showed that the circuit presented ensures immunity corresponding with test level IV of the IEC 61000-4-5:2014 international standard. The developed circuit can be modified to meet the requirements of any other equipment to be protected. Similarly, the parameters of the combination wave generator can be changed to provide different surge amplitudes.

Keywords: Combination wave generator, IEC 61000-4-5, Pspice simulation, surge protection.

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Authors: Syed Javed Arif, Mohd Ayyub Khan, Saleem Anwar Khan

Abstract:

In this paper, a simple method is presented for measurement of power frequency deviations. A phase locked loop (PLL) is used to multiply the signal under test by a factor of 100. The number of pulses in this pulse train signal is counted over a stable known period, using decade driving assemblies (DDAs) and flip-flops. These signals are combined using logic gates and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded. These pulses are equally suitable for both control applications and display units. The experimental circuit developed gives a resolution of 1 Hz within the measurement period of 20 ms. The proposed circuit is also simulated in Verilog Hardware Description Language (VHDL) and implemented using Field Programing Gate Arrays (FPGAs). A Mixed signal Oscilloscope (MSO) is used to observe the results of FPGA implementation. These results are compared with the results of the proposed circuit of discrete components. The proposed system is useful for frequency deviation measurement and control in power systems.

Keywords: Frequency measurement, digital control, phase locked loop, encoding, Verilog HDL.

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Authors: Hossein Sahoolizadeh, Alishir Moradi Kordalivand, Zargham Heidari

Abstract:

In first stage of each microwave receiver there is Low Noise Amplifier (LNA) circuit, and this stage has important rule in quality factor of the receiver. The design of a LNA in Radio Frequency (RF) circuit requires the trade-off many importance characteristics such as gain, Noise Figure (NF), stability, power consumption and complexity. This situation Forces desingners to make choices in the desing of RF circuits. In this paper the aim is to design and simulate a single stage LNA circuit with high gain and low noise using MESFET for frequency range of 5 GHz to 6 GHz. The desing simulation process is down using Advance Design System (ADS). A single stage LNA has successfully designed with 15.83 dB forward gain and 1.26 dB noise figure in frequency of 5.3 GHz. Also the designed LNA should be working stably In a frequency range of 5 GHz to 6 GHz.

Keywords: Advance Design System, Low Noise Amplifier, Radio Frequency, Noise Figure.

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Authors: B. Nasri, M. Bensaada

Abstract:

We present a simulation and realization of a battery charge regulator (BCR) in microsatellite earth observation. The tests were performed on battery pack 12volt, capacity 24Ah and the solar array open circuit voltage of 100 volt and optimum power of about 250 watt. The battery charge is made by solar module. The principle is to adapt the output voltage of the solar module to the battery by using the technique of pulse width modulation (PWM). Among the different techniques of charge battery, we opted for the technique of the controller ON/OFF is a standard technique and simple, it-s easy to be board executed validation will be made by simulation "Proteus Isis Professional software ". The circuit and the program of this prototype are based on the PIC16F877 microcontroller, a serial interface connecting a PC is also realized, to view and save data and graphics in real time, for visualization of data and graphs we develop an interface tool “visual basic.net (VB)--.

Keywords: Battery Charge Regulator, Batteries, Buck converter, Power System, Power Conditioning, Power Distribution, Solar arrays.

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Authors: B. Sathyanandhi, P. M. Balasubramaniam

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This paper presents Buck-Boost converter topology to maintain the input power factor by using the power factor stage control and regulation stage control. Suppose, if we are using the RL load the power factor will be reduced due to the presence of total harmonic distortion in the current wave. To improve the power factor the current waveform should follow the fundamental component of the voltage waveform. These can be achieved by using the high -frequency power converter. Based on the resonant circuit the converter is able to perform the function of Buck, Boost, and buck-boost converter. Here ,we have used Buck-Boost converter, because, the buck-boost converter has more advantages than the boost converter. Here the switching action of the power converter can  take place by using the external zero comparator PFC stage control. The power converter consisting of the resonant  circuit which is used to control the output voltage gain of the converter. The power converter is operated at a very high switching frequency in the range of 400KHz in order to overcome the switching losses of the power converter. Due to  presence of high switching frequency, the power factor will improve. Therefore, the total harmonics distortion present in the current waveform has also reduced. These results has generated in the form of simulation by using MATLAB/SIMULINK software.  Similar to the Buck and Boost converters, the operation of the Buck-Boost has best understood, in terms of the inductor's "reluctance" for allowing rapid change in current, which also reduces the Total Harmonic Distortion (THD) in the input current waveform, which can improve the input Power factor, based on the type of load used.

Keywords: Buck-boost converter, High switching frequency, Power factor correction, power factor correction stage Regulation stage, Total harmonic distortion (THD).

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Authors: O. Hashemipour, S. G. Nabavi

Abstract:

A high-linearity and high-speed current-mode sampleand- hold circuit is designed and simulated using a 0.25μm CMOS technology. This circuit design is based on low voltage and it utilizes a fully differential circuit. Due to the use of only two switches the switch related noise has been reduced. Signal - dependent -error is completely eliminated by a new zero voltage switching technique. The circuit has a linearity error equal to ±0.05μa, i.e. 12-bit accuracy with a ±160 μa differential output - input signal frequency of 5MHZ, and sampling frequency of 100 MHZ. Third harmonic is equal to –78dB.

Keywords: Zero-voltage-technique, MOS-resistor, OTA, Feedback-resistor.

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Authors: Jun-Hyuk Choi, Joon Sung Park, Jung-Moo Seo, In-Soung Jung

Abstract:

A brushless DC motor with integrated drive circuit for air management system is presented. Using magnetic equivalent circuit model a basic design of the motor is determined, and specific configurations are inspected thanks to finite element analysis. In order to reduce an unbalanced magnetic force in an axial direction, induced forces between a stator core and a permanent magnet are calculated with respect to the relative positions of them. For the high efficiency, and high power density, BLDC motor and drive are developed. Also vibration mode and eccentricity of a rotor are considered at the rated and maximum rotational speed Through the experimental results, a validity of the simulated one is confirmed.

Keywords: blower, BLDC, inverter

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Authors: Renbin Dai, Rana Arslan Ali Khan

Abstract:

The design of Class A and Class AB 2-stage X band Power Amplifier is described in this report. This power amplifier is part of a transceiver used in radar for monitoring iron characteristics in a blast furnace. The circuit was designed using foundry WIN Semiconductors. The specification requires 15dB gain in the linear region, VSWR nearly 1 at input as well as at the output, an output power of 10 dBm and good stable performance in the band 10.9-12.2 GHz. The design was implemented by using inter-stage configuration, the Class A amplifier was chosen for driver stage i.e. the first amplifier focusing on the gain and the output amplifier conducted at Class AB with more emphasis on output power.

Keywords: Power amplifier, Class AB, Class A, MMIC, 2-stage, X band.

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Authors: Mohammad Hasan Raouf, Azim Nowbakht, Mohammad Bagher Haddadi, Mohammad Reza Tabatabaei

Abstract:

Power quality has become a very important issue recently due to the impact on electricity suppliers, equipment manufacturers and customers. Power quality is described as the variation of voltage, current and frequency in a power system. Voltage magnitude is one of the major factors that determine the quality of power. Indeed, custom power technology, the low-voltage counterpart of the more widely known flexible ac transmission system (FACTS) technology, aimed at high-voltage power transmission applications, has emerged as a credible solution to solve many problems relating to power quality problems. There are various power quality problems such as voltage sags, swells, flickers, interruptions and harmonics etc. Active Power Filter (APF) is one of the custom power devices and can mitigate harmonics, reactive power and unbalanced load currents originating from load side. In this study, an extensive review of APF studies, the advantages and disadvantages of each introduced methods are presented. The study also helps the researchers to choose the optimum control techniques and power circuit configuration for APF applications.

Keywords: Power Quality, Custom Power, Active Filter, Control Approach.

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Authors: Jae Hyung Noh, Hang Geun Jeong

Abstract:

The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-μm 1.8-V CMOS technology.

Keywords: Phase-locked loop (PLL), charge-pump, phase/frequency detector (PFD), regulated cascode.

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Authors: Jingjing Lan, Jun Zhou, Xin Liu

Abstract:

In this paper, a low-power digital controller for DC-DC power conversion was presented. The controller generates the pulse-width modulated (PWM) signal from digital inputs provided by analog-to-digital converter (ADC). An efficient and simple design scheme to develop the control unit was discussed. This method allows minimization of the consumed resources of the chip and it is based on direct digital design approach. In this application, with the proposed scheme, nearly half area and two-third of the power consumption was saved compared to the conventional schemes. This work illustrates the possibility of implementing low-power and area-efficient power management circuit using direct digital design based approach. 

Keywords: Buck converter, DC-DC power conversion, digital control, proportional-integral (PI) controller.

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Authors: Arup K. George, Wai Pan Chan, Zhi Hui Kong, Minkyu Je

Abstract:

This paper describes a low-power second-order filter for a continuous-time chopper stabilized capacitive sensor interface, integrated with a fully differential post-CMOS surface-micromachined MEMS pressure sensor. The circuit uses a single-ended folded-cascode operational amplifier and two GM-C filters connected in cascade. The circuit is realized in a 0.18 μm CMOS process and offers differential to single-ended conversion. The novelty of the scheme is the cascade of two GM-C filters to achieve a second-order filter while minimizing power dissipation. The simulated filter cutoff frequency is 1.14 kHz at common-mode voltage 1.65 V, operating from a 3.3 V supply while dissipating 172μW of power. The filter achieves an operating range of 1V for an output load of 1MOhm and 10pF.

Keywords: Chopper Stabilization, MEMS, Pressure Sensors, Low Pass Filter

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Authors: Rafik Medjoudj, Rabah Medjoudj, D. Aissani

Abstract:

The electrical substation components are often subject to degradation due to over-voltage or over-current, caused by a short circuit or a lightning. A particular interest is given to the circuit breaker, regarding the importance of its function and its dangerous failure. This component degrades gradually due to the use, and it is also subject to the shock process resulted from the stress of isolating the fault when a short circuit occurs in the system. In this paper, based on failure mechanisms developments, the wear out of the circuit breaker contacts is modeled. The aim of this work is to evaluate its reliability and consequently its residual lifetime. The shock process is based on two random variables such as: the arrival of shocks and their magnitudes. The arrival of shocks was modeled using homogeneous Poisson process (HPP). By simulation, the dates of short-circuit arrivals were generated accompanied with their magnitudes. The same principle of simulation is applied to the amount of cumulative wear out contacts. The objective reached is to find the formulation of the wear function depending on the number of solicitations of the circuit breaker.

Keywords: reliability, short-circuit, models of shocks.

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Authors: Rishikesh Pandey, Maneesha Gupta

Abstract:

A new low-voltage floating gate MOSFET (FGMOS) based squarer using square law characteristic of the FGMOS is proposed in this paper. The major advantages of the squarer are simplicity, rail-to-rail input dynamic range, low total harmonic distortion, and low power consumption. The proposed circuit is biased without body effect. The circuit is designed and simulated using SPICE in 0.25μm CMOS technology. The squarer is operated at the supply voltages of ±0.75V . The total harmonic distortion (THD) for the input signal 0.75Vpp at 25 KHz, and maximum power consumption were found to be less than 1% and 319μW respectively.

Keywords: Analog signal processing, floating gate MOSFETs, low-voltage, Spice, squarer.

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Authors: Shobha Sharma, Amita Dev

Abstract:

Data driven dynamic logic is the high speed dynamic circuit with low area. The clock of the dynamic circuit is removed and data drives the circuit instead of clock for precharging purpose. This data driven dynamic nand gate is given static forward substrate biasing of Vsupply/2 as well as the substrate bias is connected to the input data, resulting in dynamic substrate bias. The dynamic substrate bias gives the shortest propagation delay with a penalty on the power dissipation. Propagation delay is reduced by 77.8% compared to the normal reverse substrate bias Data driven dynamic nand. Also dynamic substrate biased D3nand’s propagation delay is reduced by 31.26% compared to data driven dynamic nand gate with static forward substrate biasing of Vdd/2. This data driven dynamic nand gate with dynamic body biasing gives us the highest speed with no area penalty and finds its applications where power penalty is acceptable. Also combination of Dynamic and static Forward body bias can be used with reduced propagation delay compared to static forward biased circuit and with comparable increase in an average power. The simulations were done on hspice simulator with 22nm High-k metal gate strained Si technology HP models of Arizona State University, USA.

Keywords: Data driven nand gate, dynamic substrate biasing, nand gate, static substrate biasing.

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Authors: Kritphon Phanruttanachai, Winai Jaikla

Abstract:

This article presents a current-mode quadrature oscillator using differential different current conveyor (DDCC) and voltage differencing transconductance amplifier (VDTA) as active elements. The proposed circuit is realized fro m a non-inverting lossless integrator and an inverting second order low-pass filter. The oscillation condition and oscillation frequency can be electronically/orthogonally controlled via input bias currents. The circuit description is very simple, consisting of merely 1 DDCC, 1 VDTA, 1 grounded resistor and 3 grounded capacitors. Using only grounded elements, the proposed circuit is then suitable for IC architecture. The proposed oscillator has high output impedance which is easy to cascade or dive the external load without the buffer devices. The PSPICE simulation results are depicted, and the given results agree well with the theoretical anticipation. The power consumption is approximately 1.76mW at ±1.25V supply voltages.

Keywords: Current-mode, oscillator, integrated circuit, DDCC, VDTA

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Authors: G.Ramana Murthy, C.Senthilpari, P.Velrajkumar, Lim Tien Sze

Abstract:

The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other existing six adder circuits in terms of power, propagation delay and PDP. The proposed adder circuit is further analyzed for interconnect analysis, which gives better performance than other adder circuits in terms of layout thickness, width and height.

Keywords: Full Adder, Interconnect Analysis, Low-Power, Multiplexer, Propagation Delay, Parametric Analysis.

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Authors: Mamidi Ramakrishna Rao

Abstract:

Doubly-fed induction generator (DFIG) is currently the choice for many wind turbines. These generators, when connected to the grid through a converter, is subjected to varied power system conditions like voltage variation, frequency variation, short circuit fault conditions, etc. Further, many countries like Canada, Germany, UK, Scotland, etc. have distinct grid codes relating to wind turbines. Accordingly, following the network faults, wind turbines have to supply a definite reactive current. To satisfy the requirements including reactive current capability, an optimum electrical design becomes a mandate for DFIG to function. This paper intends to optimize the equivalent circuit parameters of an electrical design for satisfactory DFIG performance. Direct search method has been used for optimization of the parameters. The variables selected include electromagnetic core dimensions (diameters and stack length), slot dimensions, radial air gap between stator and rotor and winding copper cross section area. Optimization for 2 MW DFIG has been executed separately for three objective functions - maximum reactive power capability (Case I), maximum efficiency (Case II) and minimum weight (Case III). In the optimization analysis program, voltage variations (10%), power factor- leading and lagging (0.95), speeds for corresponding to slips (-0.3 to +0.3) have been considered. The optimum designs obtained for objective functions were compared. It can be concluded that direct search method of optimization helps in determining an optimum electrical design for each objective function like efficiency or reactive power capability or weight minimization.

Keywords: Direct search, DFIG, equivalent circuit parameters, optimization.

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Authors: H. A. Majid, N. Razali, M. S. Sulaiman, A. K. A'ain

Abstract:

A new interface circuit for capacitive sensor is presented. This paper presents the design and simulation of soil moisture capacitive sensor interface circuit based on phase differential technique. The circuit has been designed and fabricated using MIMOS- 0.35"m CMOS technology. Simulation and test results show linear characteristic from 36 – 52 degree phase difference, representing 0 – 100% in soil moisture level. Test result shows the circuit has sensitivity of 0.79mV/0.10 phase difference, translating into resolution of 10% soil moisture level.

Keywords: Capacitive sensor, interface, phase differential.

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Authors: Amod P. Vaze

Abstract:

Genetic Algorithm has been used to solve wide range of optimization problems. Some researches conduct on applying Genetic Algorithm to analog circuit design automation. These researches show a better performance due to the nature of Genetic Algorithm. In this paper a modified Genetic Algorithm is applied for analog circuit design automation. The modifications are made to the topology of the circuit. These modifications will lead to a more computationally efficient algorithm.

Keywords: Genetic algorithm, analog circuits, design.

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Authors: Vishnu Pratap Singh Kirar

Abstract:

Memristor is also known as the fourth fundamental passive circuit element. When current flows in one direction through the device, the electrical resistance increases and when current flows in the opposite direction, the resistance decreases. When the current is stopped, the component retains the last resistance that it had, and when the flow of charge starts again, the resistance of the circuit will be what it was when it was last active. It behaves as a nonlinear resistor with memory. Recently memristors have generated wide research interest and have found many applications. In this paper we survey the various applications of memristors which include non volatile memory, nanoelectronic memories, computer logic, neuromorphic computer architectures low power remote sensing applications, crossbar latches as transistor replacements, analog computations and switches.

Keywords: Memristor, non-volatile memory, arithmatic operation, programmable resistor.

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Authors: Ambuj Kumar, Sunil Kumar Singh, Shrikant Singh

Abstract:

Sweep frequency response analysis has been turning out a powerful tool for investigation of mechanical as well as electrical integration of transformers. In this paper various aspect of practical application of SFRA has been studied. Open circuit and short circuit measurement were done on different phases of high voltage and low voltage winding. A case study was presented for the transformer of rating 31.5 MVA for various frequency ranges. A clear picture was presented for sub- frequency ranges for HV as well as LV winding. The main motive of work is to investigate high voltage short circuit response. The theoretical concept about SFRA responses is validated with expert system software results.

Keywords: Frequency deviation, OCT & SCT, SFRA, Transformer winding.

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Authors: Alexandr A. Penin

Abstract:

Application of projective geometry to the theory of two-ports and cascade circuits with a load change is considered. The equations linking the input and output of a two-port are interpreted as projective transformations which have the invariant as a cross-ratio of four points. This invariant has place for all regime parameters in all parts of a cascade circuit. This approach allows justifying the definition of a regime and its change, to calculate a circuit without explicitly finding the aparameters, to transmit accurately an analogue signal through the unstable two-port.

Keywords: Circuit regime, geometric circuit theory, projective geometry, two-port.

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Authors: M. Y. Ismail, M. Inam

Abstract:

This paper presents equivalent circuit modeling of active planar reflectors which can be used for the detailed analysis and characterization of reflector performance in terms of lumped components. Equivalent circuit representation has been proposed for PIN diodes and liquid crystal based active planar reflectors designed within X-band frequency range. A very close agreement has been demonstrated between equivalent circuit results, 3D EM simulated results as well as measured scattering parameter results. In the case of measured results, a maximum discrepancy of 1.05dB was observed in the reflection loss performance, which can be attributed to the losses occurred during measurement process.

Keywords: Equivalent circuit modelling, planar reflectors, reflectarray antenna, PIN diode, liquid crystal.

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