Search results for: dual-mode CMOS analog multiplier

Authors: Ahmad Zahran, Ahmed Herzallah, Ahmad Ahmad, Mahran Quraan

Abstract:

Generation of high DC voltages is necessary for testing the insulation material of high voltage AC transmission lines with long lengths. The harmonic and ripple contents of the output DC voltage supplied by high voltage DC circuits require the use of costly capacitors to smooth the output voltage after rectification. This paper proposes a new modular multiplier high voltage DC generator with embedded Cockcroft-Walton circuits that achieve a negligible harmonic and ripple contents of the output DC voltage without the need for costly filters to produce a nearly constant output voltage. In this new topology, Cockcroft-Walton modules are connected in series to produce a high DC output voltage. The modules are supplied by low input AC voltage sources that have the same magnitude and frequency and shifted from each other by a certain angle to eliminate the harmonics from the output voltage. The small ripple factor is provided by the smoothing column capacitors and the phase shifted input voltages of the cascaded modules. The constituent harmonics within each module are determined using Fourier analysis. The viability of the proposed DC generator for testing purposes and the effectiveness of the cascaded connection are confirmed by numerical simulations using MATLAB/Simulink.

Keywords: Cockcroft-Walton circuit, Harmonics, Ripple factor, HVDC generator.

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Authors: Santanu Santra, Utpal Roy

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Quantum-dot Cellular Automata (QCA) is one of the most substitute emerging nanotechnologies for electronic circuits, because of lower power consumption, higher speed and smaller size in comparison with CMOS technology. The basic devices, a Quantum-dot cell can be used to implement logic gates and wires. As it is the fundamental building block on nanotechnology circuits. By applying XOR gate the hardware requirements for a QCA circuit can be decrease and circuits can be simpler in terms of level, delay and cell count. This article present a modest approach for implementing novel optimized XOR gate, which can be applied to design many variants of complex QCA circuits. Proposed XOR gate is simple in structure and powerful in terms of implementing any digital circuits. In order to verify the functionality of the proposed design some complex implementation of parity generator and parity checker circuits are proposed and simulating by QCA Designer tool and compare with some most recent design. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, CMOS technology, Logic gates, QCA Designer, Quantum-dot Cellular Automata (QCA).

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Authors: N. Ben Ameur, M. Loulou

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This paper study the high-level modelling and design of delta-sigma (ΔΣ) noise shapers for audio Digital-to-Analog Converter (DAC) so as to eliminate the in-band Signal-to-Noise- Ratio (SNR) degradation that accompany one channel mismatch in audio signal. The converter combines a cascaded digital signal interpolation, a noise-shaping single loop delta-sigma modulator with a 5-bit quantizer resolution in the final stage. To reduce sensitivity of Digital-to-Analog Converter (DAC) nonlinearities of the last stage, a high pass second order Data Weighted Averaging (R2DWA) is introduced. This paper presents a MATLAB description modelling approach of the proposed DAC architecture with low distortion and swing suppression integrator designs. The ΔΣ Modulator design can be configured as a 3rd-order and allows 24-bit PCM at sampling rate of 64 kHz for Digital Video Disc (DVD) audio application. The modeling approach provides 139.38 dB of dynamic range for a 32 kHz signal band at -1.6 dBFS input signal level.

Keywords: DVD-audio, DAC, Interpolator and Interpolation Filter, Single-Loop ΔΣ Modulation, R2DWA, Clock Jitter

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Authors: Nureni O. Adeboye, Dawud A. Agunbiade

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This research attempts to investigate the effects of heteroscedasticity and periodicity in a Panel Data Regression Model (PDRM) by extending previous works on balanced panel data estimation within the context of fitting PDRM for Banks audit fee. The estimation of such model was achieved through the derivation of Joint Lagrange Multiplier (LM) test for homoscedasticity and zero-serial correlation, a conditional LM test for zero serial correlation given heteroscedasticity of varying degrees as well as conditional LM test for homoscedasticity given first order positive serial correlation via a two-way error component model. Monte Carlo simulations were carried out for 81 different variations, of which its design assumed a uniform distribution under a linear heteroscedasticity function. Each of the variation was iterated 1000 times and the assessment of the three estimators considered are based on Variance, Absolute bias (ABIAS), Mean square error (MSE) and the Root Mean Square (RMSE) of parameters estimates. Eighteen different models at different specified conditions were fitted, and the best-fitted model is that of within estimator when heteroscedasticity is severe at either zero or positive serial correlation value. LM test results showed that the tests have good size and power as all the three tests are significant at 5% for the specified linear form of heteroscedasticity function which established the facts that Banks operations are severely heteroscedastic in nature with little or no periodicity effects.

Keywords: Audit fee, heteroscedasticity, Lagrange multiplier test, periodicity.

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Authors: Jörg Lenhardt, Wolfram Schiffmann, Jörg Keller

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While the feature sizes of recent Complementary Metal Oxid Semiconductor (CMOS) devices decrease the influence of static power prevails their energy consumption. Thus, power savings that benefit from Dynamic Frequency and Voltage Scaling (DVFS) are diminishing and temporal shutdown of cores or other microchip components become more worthwhile. A consequence of powering off unused parts of a chip is that the relative difference between idle and fully loaded power consumption is increased. That means, future chips and whole server systems gain more power saving potential through power-aware load balancing, whereas in former times this power saving approach had only limited effect, and thus, was not widely adopted. While powering off complete servers was used to save energy, it will be superfluous in many cases when cores can be powered down. An important advantage that comes with that is a largely reduced time to respond to increased computational demand. We include the above developments in a server power model and quantify the advantage. Our conclusion is that strategies from datacenters when to power off server systems might be used in the future on core level, while load balancing mechanisms previously used at core level might be used in the future at server level.

Keywords: Power efficiency, static power consumption, dynamic power consumption, CMOS.

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Authors: P. Asadee

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Multiplication algorithms have considerable effect on processors performance. A new high-speed, low-power multiplication algorithm has been presented using modified Dadda tree structure. Three important modifications have been implemented in inner product generation step, inner product reduction step and final addition step. Optimized algorithms have to be used into basic computation components, such as multiplication algorithms. In this paper, we proposed a new algorithm to reduce power, delay, and transistor count of a multiplication algorithm implemented using low power modified counter. This work presents a novel design for Dadda multiplication algorithms. The proposed multiplication algorithm includes structured parts, which have important effect on inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid adder is presented for fast, low voltage applications. The new 64-bit adder uses a new circuit to implement the proposed carry hybrid adder. The new adder using 80 nm CMOS technology has been implemented on 700 MHz clock frequency. The proposed multiplication algorithm has achieved 14 percent improvement in transistor count, 13 percent reduction in delay and 12 percent modification in power consumption in compared with conventional designs.

Keywords: adder, CMOS, counter, Dadda tree, encoder.

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Authors: Jiri Sebesta

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Phase locked loops (PLL) and delay locked loops (DLL) play an important role in establishing coherent references (phase of carrier and symbol timing) in digital communication systems. Fully digital receiver including digital carrier synchronizer and symbol timing synchronizer fulfils the conditions for universal multi-mode communication receiver with option of symbol rate setting over several digit places and long-term stability of requirement parameters. Afterwards it is necessary to realize PLL and DLL in synchronizer in digital form and to approach to these subsystems as a discrete representation of analog template. Analysis of discrete phase locked loop (DPLL) or discrete delay locked loop (DDLL) and technique to determine their characteristics based on analog (continuous-time) template is performed in this posed paper. There are derived transmission response and error function for 1st order discrete locked loop and resulting equations and graphical representations for 2nd order one. It is shown that the spectrum translation due to sampling takes effect at frequency characteristics computing for specific values of loop parameters.

Keywords: Carrier synchronization, coherent demodulation, software defined receiver, symbol timing.

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Authors: P. N. Korde, P. P. Bedekar

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The time coordination of overcurrent relays (OCR) in a power distribution network is of great importance, as it reduces the power outages by avoiding the mal-operation of the backup relays. For this, the optimum value of the time multiplier setting (TMS) of OCRs should be chosen. The problem of determining the optimum value of TMS of OCRs in power distribution networks is formulated as a constrained optimization problem. The objective is to find the optimum value of TMS of OCRs to minimize the time of operation of relays under the constraint of maintaining the coordination of relays. A power distribution network can have a combination of numerical and electromechanical relays. The TMS of numerical relays can be set to any real value (which satisfies the constraints of the problem), whereas the TMS of electromechanical relays can be set in fixed step (0 to 1 in steps of 0.05). The main contribution of this paper is a formulation of the problem as a mixed-integer linear programming (MILP) problem and application of Gomory's cutting plane method to find the optimum value of TMS of OCRs. The TMS of electromechanical relays are taken as integers in the range 1 to 20 in the step of 1, and these values are mapped to 0.05 to 1 in the step of 0.05. The results obtained are compared with those obtained using a simplex method and its variants. It has been shown that the mixed-integer linear programming method outperforms the simplex method (and its variants) in the case of a system having a combination of numerical and electromechanical relays.

Keywords: Backup protection, constrained optimization, Gomory's cutting plane method, mixed-integer linear programming, overcurrent relay coordination, simplex method.

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Authors: Anthony Wachs, Guillaume Vinay, Gilles Ferrer, Jacques Kouakou, Calin Dan, Laurence Girolami

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An original Direct Numerical Simulation (DNS) method to tackle the problem of particulate flows at moderate to high concentration and finite Reynolds number is presented. Our method is built on the framework established by Glowinski and his coworkers [1] in the sense that we use their Distributed Lagrange Multiplier/Fictitious Domain (DLM/FD) formulation and their operator-splitting idea but differs in the treatment of particle collisions. The novelty of our contribution relies on replacing the simple artificial repulsive force based collision model usually employed in the literature by an efficient Discrete Element Method (DEM) granular solver. The use of our DEM solver enables us to consider particles of arbitrary shape (at least convex) and to account for actual contacts, in the sense that particles actually touch each other, in contrast with the simple repulsive force based collision model. We recently upgraded our serial code, GRIFF 1 [2], to full MPI capabilities. Our new code, PeliGRIFF 2, is developed under the framework of the full MPI open source platform PELICANS [3]. The new MPI capabilities of PeliGRIFF open new perspectives in the study of particulate flows and significantly increase the number of particles that can be considered in a full DNS approach: O(100000) in 2D and O(10000) in 3D. Results on the 2D/3D sedimentation/fluidization of isometric polygonal/polyedral particles with collisions are presented.

Keywords: Particulate flow, distributed lagrange multiplier/fictitious domain method, discrete element method, polygonal shape, sedimentation, distributed computing, MPI

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Authors: Sanjay Singh, M Sathish Kumar, H. S Mruthyunjaya

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Multicarrier transmission system such as Orthogonal Frequency Division Multiplexing (OFDM) is a promising technique for high bit rate transmission in wireless communication system. OFDM is a spectrally efficient modulation technique that can achieve high speed data transmission over multipath fading channels without the need for powerful equalization techniques. However the price paid for this high spectral efficiency and less intensive equalization is low power efficiency. OFDM signals are very sensitive to nonlinear effects due to the high Peak-to-Average Power Ratio (PAPR), which leads to the power inefficiency in the RF section of the transmitter. This paper investigates the effect of PAPR reduction on the performance parameter of multicarrier communication system. Performance parameters considered are power consumption of Power Amplifier (PA) and Digital-to-Analog Converter (DAC), power amplifier efficiency, SNR of DAC and BER performance of the system. From our analysis it is found that irrespective of PAPR reduction technique being employed, the power consumption of PA and DAC reduces and power amplifier efficiency increases due to reduction in PAPR. Moreover, it has been shown that for a given BER performance the requirement of Input-Backoff (IBO) reduces with reduction in PAPR.

Keywords: BER, Crest Factor (CF), Digital-to-Analog Converter(DAC), Input-Backoff (IBO), Orthogonal Frequency Division Multiplexing(OFDM), Peak-to-Average Power Ratio (PAPR), PowerAmplifier efficiency, SNR

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Authors: D. Krishnaveni, M. Geetha Priya

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Application of reversible logic in integrated circuits results in the improved optimization of power consumption. This technology can be put into use in a variety of low power applications such as quantum computing, optical computing, nano-technology, and Complementary Metal Oxide Semiconductor (CMOS) Very Large Scale Integrated (VLSI) design etc. Logic gates are the basic building blocks in the design of any logic network and thus integrated circuits. In this paper, reversible Dual Key Gate (DKG) and Dual key Gate Pair (DKGP) gates that work singly as full adder/full subtractor are used to realize the basic building blocks of logic circuits. Reversible full adder/subtractor and parallel adder/ subtractor are designed using other reversible gates available in the literature and compared with that of DKG & DKGP gates. Efficient performance of reversible logic circuits relies on the optimization of the key parameters viz number of constant inputs, garbage outputs and number of reversible gates. The full adder/subtractor and parallel adder/subtractor design with reversible DKGP and DKG gates results in least number of constant inputs, garbage outputs, and number of reversible gates compared to the other designs. Thus, this paper provides a threshold to build more complex arithmetic systems using these reversible logic gates, leading to the enhanced performance of computing systems.

Keywords: Low power CMOS, quantum computing, reversible logic gates, full adder, full subtractor, parallel adder/subtractor, basic gates, universal gates.

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Authors: N. Shen, Z. X. Chen, K.D. Buddharaju, H. M. Chua, X. Li, N. Singh, G.Q Lo, D.-L. Kwong

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In this paper, we present a vertical wire NMOS device fabricated using CMOS compatible processes. The impact of temperature on various device parameters is investigated in view of usual increase in surrounding temperature with device density.

Keywords: Gate-all-around, temperature dependence, silicon nanowire

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Authors: G. Sonfack, J. Mbihi, B. Lonla Moffo

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This paper presents an optimal duty-cycle modulation (ODCM) scheme for analog-to-digital conversion (ADC) systems. The overall ODCM-Based ADC problem is decoupled into optimal DCM and digital filtering sub-problems, while taking into account constraints of mutual design parameters between the two. Using a set of three lemmas and four morphological theorems, the ODCM sub-problem is modelled as a nonlinear cost function with nonlinear constraints. Then, a weighted least p^th norm of the error between ideal and predicted frequency responses is used as a cost function for the digital filtering sub-problem. In addition, MATLAB fmincon and MATLAB iirlnorm tools are used as optimal DCM and least p^th norm solvers respectively. Furthermore, the virtual simulation scheme of an overall prototyping ODCM-based ADC system is implemented and well tested with the help of Simulink tool according to relevant set of design data, i.e., 3 KHz of modulating bandwidth, 172 KHz of maximum modulation frequency and 25 MHZ of sampling frequency. Finally, the results obtained and presented show that the ODCM-based ADC achieves under 3 KHz of modulating bandwidth: 57 dBc of SINAD (signal-to-noise and distorsion), 58 dB of SFDR (Surpious free dynamic range) -80 dBc of THD (total harmonic distorsion), and 10 bits of minimum resolution. These performance levels appear to be a great challenge within the class of oversampling ADC topologies, with 2^nd order IIR (infinite impulse response) decimation filter.

Keywords: Digital IIR filter, morphological lemmas and theorems, optimal DCM-based DAC, virtual simulation, weighted least pth norm.

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Authors: Dalibor Biolek, Viera Biolková, Zden─øk Kolka

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A universal current-mode biquad is described which represents an economical variant of well-known KHN (Kerwin, Huelsman, Newcomb) voltage-mode filter. The circuit consists of two multiple-output OTAs and of two grounded capacitors. Utilizing simple splitter of the input current and a pair of jumpers, all the basic 2nd-order transfer functions can be implemented. The principle is verified by Spice simulation on the level of a CMOS structure of OTAs.

Keywords: Biquad, current mode, OTA.

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Authors: Asmaa M. El-Bandrawy, Afaf M. Botla, Ghada E. El-Refaye, Hassan O. Ghareeb

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Background: Urinary incontinence is a common problem among adults. Its incidence increases with age and it is more frequent in women. Pelvic floor muscle training (PFMT) is the first-line therapy in the treatment of pelvic floor dysfunction (PFD) either alone or combined with biofeedback-assisted PFMT. The aim of the work: The purpose of this study is to evaluate the efficacy of biofeedback-assisted PFMT in postoperative stress urinary incontinence. Settings and Design: A single blind controlled trial design was. Methods and Material: This study was carried out in 30 volunteer patients diagnosed as severe degree of stress urinary incontinence and they were admitted to surgical treatment. They were divided randomly into two equal groups: (Group A) consisted of 15 patients who had been treated with post-operative biofeedback-assisted PFMT and home exercise program (Group B) consisted of 15 patients who had been treated with home exercise program only. Assessment of all patients in both groups (A) and (B) was carried out before and after the treatment program by measuring intra-vaginal pressure in addition to the visual analog scale. Results: At the end of the treatment program, there was a highly statistically significant difference between group (A) and group (B) in the intra-vaginal pressure and the visual analog scale favoring the group (A). Conclusion: biofeedback-assisted PFMT is an effective method for the symptomatic relief of post-operative female stress urinary incontinence.

Keywords: Stress urinary incontinence, pelvic floor muscles, pelvic floor exercises, biofeedback.

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Authors: Amin Chegenizadeh, Hamid Nikraz

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The use of computer hardware and software in education and training dates to the early 1940s, when American researchers developed flight simulators which used analog computers to generate simulated onboard instrument data.Computer software is widely used to help engineers and undergraduate student solve their problems quickly and more accurately. This paper presents the list of computer software in geotechnical engineering.

Keywords: Geotechnical, Teaching, Courseware

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Authors: Jasdeep Kaur, Nupur Prakash, S. S. Rajput

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A current mirror (CM) based on self cascode MOSFETs low voltage analog and mixed mode structures has been proposed. The proposed CM has high output impedance and can operate at 0.5 V. P-Spice simulations confirm the high performance of this CM with a bandwidth of 6.0 GHz at input current of 100 μA.

Keywords: Current Mirrors, Composite Cascode Structure, Current Source/Sink

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Authors: S. Bouhouche, M. Lahreche, S. Ziani, J. Bast

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Modern manufacturing facilities are large scale, highly complex, and operate with large number of variables under closed loop control. Early and accurate fault detection and diagnosis for these plants can minimise down time, increase the safety of plant operations, and reduce manufacturing costs. Fault detection and isolation is more complex particularly in the case of the faulty analog control systems. Analog control systems are not equipped with monitoring function where the process parameters are continually visualised. In this situation, It is very difficult to find the relationship between the fault importance and its consequences on the product failure. We consider in this paper an approach to fault detection and analysis of its effect on the production quality using an adaptive centring and scaling in the pickling process in cold rolling. The fault appeared on one of the power unit driving a rotary machine, this machine can not track a reference speed given by another machine. The length of metal loop is then in continuous oscillation, this affects the product quality. Using a computerised data acquisition system, the main machine parameters have been monitored. The fault has been detected and isolated on basis of analysis of monitored data. Normal and faulty situation have been obtained by an artificial neural network (ANN) model which is implemented to simulate the normal and faulty status of rotary machine. Correlation between the product quality defined by an index and the residual is used to quality classification.

Keywords: Modeling, fault detection and diagnosis, parameters estimation, neural networks, Fault Detection and Diagnosis (FDD), pickling process.

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Authors: Virupakshaiah DBM, Chandrakanth Kelmani, Rachanagouda Patil, Prasad Hegade

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Severe acute respiratory syndrome (SARS) is a respiratory disease in humans which is caused by the SARS coronavirus. The treatment of coronavirus-associated SARS has been evolving and so far there is no consensus on an optimal regimen. The mainstream therapeutic interventions for SARS involve broad-spectrum antibiotics and supportive care, as well as antiviral agents and immunomodulatory therapy. The Protein- Ligand interaction plays a significant role in structural based drug designing. In the present work we have taken the receptor Angiotensin converting enzyme 2 and identified the drugs that are commonly used against SARS. They are Lopinavir, Ritonavir, Ribavirin, and Oseltamivir. The receptor Angiotensin converting enzyme 2 (ACE-2) was docked with above said drugs and the energy value obtained are as follows, Lopinavir (-292.3), Ritonavir (-325.6), Oseltamivir (- 229.1), Ribavirin (-208.8). Depending on the least energy value we have chosen the best two drugs out of the four conventional drugs. We tried to improve the binding efficiency and steric compatibility of the two drugs namely Ritonavir and Lopinavir. Several modifications were made to the probable functional groups (phenylic, ketonic groups in case of Ritonavir and carboxylic groups in case of Lopinavir respectively) which were interacting with the receptor molecule. Analogs were prepared by Marvin Sketch software and were docked using HEX docking software. Lopinavir analog 8 and Ritonavir analog 11 were detected with significant energy values and are probable lead molecule. It infers that some of the modified drugs are better than the original drugs. Further work can be carried out to improve the steric compatibility of the drug based upon the work done above for a more energy efficient binding of the drugs to the receptor.

Keywords: Protein data bank, Rasmol, Marvin sketch, Hexdocking.

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Authors: Rekha V. Dundur , M.V.Latte, S.Y. Kulkarni, M.K.Venkatesha

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The advent of multi-million gate Field Programmable Gate Arrays (FPGAs) with hardware support for multiplication opens an opportunity to recreate a significant portion of the front end of a human cochlea using this technology. In this paper we describe the implementation of the cochlear filter and show that it is entirely suited to a single device XC3S500 FPGA implementation .The filter gave a good fit to real time data with efficiency of hardware usage.

Keywords: Cochlea, FPGA, IIR (Infinite Impulse Response), Multiplier.

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Authors: Karama M. AL-Tamimi, Munir A. Al-Absi

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A new OTA-based logarithmic-control variable gain current amplifier (LCCA) is presented. It consists of two Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The circuit operates from 0.6V DC power supply and consumes 0.6 μW. The linear-dB controllable output range is 43 dB with maximum error less than 0.5dB. The functionality of the proposed design was confirmed using HSPICE in 0.35μm CMOS process technology.

Keywords: LCCA, OTA, Logarithmic, VGA, Weak inversion, Current-mode

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Authors: Lei Li, Xiaobing Ren, Xiaoxia Lu, Xiaofang Yan

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In this paper, some experiments of liquid dispersion flow driven by explosion in vertical plane were carried out using a liquid explosive dispersion device with film cylindrical constraints. The separated time series describing the breakup shape and dispersion process of liquid were recorded with high speed CMOS camera. The experimental results were analyzed and some essential characteristics of liquid dispersing flow are presented.

Keywords: Explosive Disseminations, liquid dispersion Flow, Cavitations, Gasification.

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Authors: Shahram Jafari, Mohammad-Ali Nikouei Mahani, Mohammad Arabnezhad, Mahdi Sharifi

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Car accident is one of the major causes of death in many countries. Many researchers have attempted to design and develop techniques to increase car safety in the past recent years. In spite of all the efforts, it is still challenging to design a system adaptive to the driver rather than the automotive characteristics. In this paper, the adaptive car safety system is explained which attempts to find a balance.

Keywords: Analog to Digital Converter (ADC), AdaptiveCar Safety System, Multi-Media Card (MMC).

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Authors: Ivelina N. Cholakova, Tihomir B. Takov, Radostin Ts. Tsankov, Nicolas Simonne, Slavka S. Tzanova

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Adjacent Hall microsensors, comprising a silicon substrate and four contacts, providing simultaneously two supply inputs and two differential outputs, are characterized. The voltage related sensitivity is in the order of 0.11T-1, and a cancellation method for offset compensation is used, achieving residual offset in the micro scale which is also compared to a single Hall plate.

Keywords: Adjacent Hall sensors, offset compensation, voltage related sensitivity, 0.18μm CMOS technology.

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Authors: Gianluca Cornetta, David J. Santos, Balwant Godara

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A 1.2 V, 0.61 mA bias current, low noise amplifier (LNA) suitable for low-power applications in the 2.4 GHz band is presented. Circuit has been implemented, laid out and simulated using a UMC 130 nm RF-CMOS process. The amplifier provides a 13.3 dB power gain a noise figure NF< 2.28 dB and a 1-dB compression point of -15.69 dBm, while dissipating 0.74 mW. Such performance make this design suitable for wireless sensor networks applications such as ZigBee.

Keywords: Current Reuse, IEEE 802.15.4 (ZigBee), Low NoiseAmplifiers, Wireless Sensor Networks.

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Authors: Ridha Ghayoula, ElAmjed Hajlaoui, Talel Korkobi, Mbarek Traii, Hichem Trabelsi

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In this paper, the hardware implementation of the RSA public-key cryptographic algorithm is presented. The RSA cryptographic algorithm is depends on the computation of repeated modular exponentials. The Montgomery algorithm is used and modified to reduce hardware resources and to achieve reasonable operating speed for FPGA. An efficient architecture for modular multiplications based on the array multiplier is proposed. We have implemented a RSA cryptosystem based on Montgomery algorithm. As a result, it is shown that proposed architecture contributes to small area and reasonable speed.

Keywords: RSA, Cryptosystem, Montgomery, Implementation.FPGA.

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Authors: H. Asiaban, E. Farshidi

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This paper presents a new true RMS-to-DC converter circuit based on a square-root-domain squarer/divider. The circuit is designed by employing up-down translinear loop and using of MOSFET transistors that operate in strong inversion saturation region. The converter offer advantages of two-quadrant input current, low circuit complexity, low supply voltage (1.2V) and immunity from the body effect. The circuit has been simulated by HSPICE. The simulation results are seen to conform to the theoretical analysis and shows benefits of the proposed circuit.

Keywords: Current-mode, squarer/divider, low-pass filter, converter, translinear loop, RMS-to-DC.

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Authors: Padmanabhan Balasubramanian, C. Ardil

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In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.

Keywords: Reed-Muller forms, Logic function, Hammingdistance, Algebraic factorization, Low power design.

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Authors: Yibo Fan, Takeshi Ikenaga, Yukiyasu Tsunoo, Satoshi Goto

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This paper proposes a low-cost reconfigurable architecture for AES algorithm. The proposed architecture separates SubBytes and MixColumns into two parallel data path, and supports different bit-width operation for this two data path. As a result, different number of S-box can be supported in this architecture. The throughput and power consumption can be adjusted by changing the number of S-box running in this design. Using the TSMC 0.18μm CMOS standard cell library, a very low-cost implementation of 7K Gates is obtained under 182MHz frequency. The maximum throughput is 360Mbps while using 4 S-Box simultaneously, and the minimum throughput is 114Mbps while only using 1 S-Box

Keywords: AES, Reconfigurable architecture, low cost

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Authors: Mohsen Bagheri, Ahmad Afifi

Abstract:

This paper presents a new method for read out of the piezoresistive accelerometer sensors. The circuit works based on Instrumentation amplifier and it is useful for reducing offset In Wheatstone Bridge. The obtained gain is 645 with 1μv/°c Equivalent drift and 1.58mw power consumption. A Schmitt trigger and multiplexer circuit control output node. a high speed counter is designed in this work .the proposed circuit is designed and simulated In 0.18μm CMOS technology with 1.8v power supply.

Keywords: Piezoresistive accelerometer, zero offset, Schmitt trigger, bidirectional reversible counter

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