A 24-Bit, 8.1-MS/s D/A Converter for Audio Baseband Channel Applications

Authors: N. Ben Ameur, M. Loulou

Abstract:

This paper study the high-level modelling and design of delta-sigma (ΔΣ) noise shapers for audio Digital-to-Analog Converter (DAC) so as to eliminate the in-band Signal-to-Noise- Ratio (SNR) degradation that accompany one channel mismatch in audio signal. The converter combines a cascaded digital signal interpolation, a noise-shaping single loop delta-sigma modulator with a 5-bit quantizer resolution in the final stage. To reduce sensitivity of Digital-to-Analog Converter (DAC) nonlinearities of the last stage, a high pass second order Data Weighted Averaging (R2DWA) is introduced. This paper presents a MATLAB description modelling approach of the proposed DAC architecture with low distortion and swing suppression integrator designs. The ΔΣ Modulator design can be configured as a 3rd-order and allows 24-bit PCM at sampling rate of 64 kHz for Digital Video Disc (DVD) audio application. The modeling approach provides 139.38 dB of dynamic range for a 32 kHz signal band at -1.6 dBFS input signal level.

Keywords: DVD-audio, DAC, Interpolator and Interpolation Filter, Single-Loop ΔΣ Modulation, R2DWA, Clock Jitter

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1080288

References:

[1] T. Soh, "Five semiconductor makers to ship 24-bit DAC LSI-s for use in audio equipment" (in Japanese), Nikkei Electron, no. 706, pp. 51-56, Jan 1998.
[2] J. C. Candy and G. C. Temes, "Oversampling Delta-Sigma Data Converters", IEEE, New York, NY, USA, 1992, ISBN 0-87942-281-5.
[3] I. Fujimori, A. Nogi, and T. Sugimoto, "A multibit delta-sigma audio DAC with 120 dB dynamic range", in ISSCC Dig. Tech. Papers, Feb. 1999, pp. 152-153.
[4] D. Reefman et. al. , "A 128fs, Multi-bit ΔΣ CMOS Audio DAC with Real-time DEM and 115 dB SFDR », Philips Semiconductors, Eindhoven, the Netherlands. AES Preprint 5846, March 2003.
[5] T. Rueger et.al., "A 110dB Ternary PWM Current-Mode Audio DAC with Monolithic 2Vrms Driver", ISSCC 2004 Paper 20.7, February 2004.
[6] N. J. Fliege, "Multirate Digital Signal Processing", John Wiley & Sons Ltd. Chichester, 1994.
[7] Alan V. Oppenheim and Ronald W. Schafer. Discrete-Time Signal Processing. Prentice Hall, Upper Saddle River, New Jersey, second edition, 1999.
[8] S. K. Mitra, "Digital Signal Processing". A Computer-Based Approach, 2nd Ed., McGraw-Hill, New York, 2001.
[9] N. Ben Ameur, and M Loulou, "Design of Efficient Digital Interpolation Filters and Sigma-Delta Modulator for Audio DAC", IEEE International Conference on Design &Test of Integrated Systems (DTIS-08), March 25-28, 2008 Tozeur, Tunisia.
[10] PhilSchniter,"Computational Savings of Polyphase Interpolation/ Decimation", Version 2.2, Sep 20, 2005.
[11] T. Saramäki, "Design of FIR filters as a tapped cascaded interconnection of identical subfilters," IEEE Transactions on Circuits and Systems. Vol.34, pp.1011-1029, 1987.
[12] R. A. Losada, "Practical FIR Filter Design in Matlab®", Revision 1.0, The Math Works, Inc., 3 Apple Hill, Dr Natick, MA 01760, USA, March 31, 2003.
[13] R. Lyons, "Interpolated narrowband lowpass FIR filters," IEEE Signal Proc. Mag., pp. 50-57, January, 2003.
[14] Rusu A. and Tenhunen H., "A Third-Order Multibit Sigma-Delta Modulator with Feedforward Signal Path", IEEE NEWCAS Workshop, 2003, pp. 145-148.
[15] R. Schreier, "An Empirical Study of Higher Order Single Bit Sigma Delta Modulators". IEEE Transactions on Circuits and Systems - II, vol. 40, pp.461-466, August 1993.
[16] S.R. Norsworthy, R. Schreier, and G.C. Temes, "Delta-Sigma Data Converters: Theory,Design, and Simulation", IEEE Press, NY, USA, ISBN 0-78031-045-4, Nov. 1996.
[17] A. A. Hamoui, K. Martin, "High-Order Multibit ΔΣ Modulators and Pseudo Data-Weighted-Averaging in Low- Oversampling ΔΣ ADCs for Broad-Band Applications," IEEE Trans. Circuits Syst. I, vol. 51, pp. 72- 85, Jan. 2004
[18] J. G. Kenney and L. R. Carley, "Design of multibit noise-shaping data converters," in Analog Integrated Circuits and Signal Processing. Boston, MA: Kluwer, 1993, pp. 99-112
[19] R. E. Radke, A. Eshraghi, and T. S. Fiez, "A 14-bit current-mode ΔΣ DAC based upon rotated data weighted averaging," IEEE J. Solid-State Circuits, vol. 35, pp. 1074-1084, Aug. 2000
[20] R. T. Baird and T. S. Fiez, "Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averaging," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 12, pp. 753- 762, Dec. 1995.
[21] S. Brigati, F. Francesconi, P. Malcovati, D. Tonietto, A. Baschirotto and F. Maloberti", Modeling Sigma-Delta Modulator Non-Idealities in SIMULINK", Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS ÔÇÿ99), 2, Orlando, USA, pp. 384-387, 1999
[22] S. Lee and K. Yang, "Design a Low-Jitter Clock for High-Speed A/D Converters". Sensors, vol. 18, no. 10, October 2001.