Search results for: Complementary Metal Oxide Semiconductor (CMOS)

Authors: V. Rednic, N. Aldea, P. Marginean, D. Macovei, C. M. Teodorescu, E. Dorolti, F. Matei

Abstract:

The supported Pd catalysts were analyzed by X-ray diffraction and X-ray absorption spectroscopy in order to determine their global and local structure. The average particle size of the supported Pd catalysts was determined by X-ray diffraction method. One of the main purposes of the present contribution is to focus on understanding the specific role of the Pd particle size determined by X-ray diffraction and that of the support oxide. Based on X-ray absorption fine structure spectroscopy analysis we consider that the whole local structure of the investigated samples are distorted concerning the atomic number but the distances between atoms are almost the same as for standard Pd sample. Due to the strong modifications of the Pd cluster local structure, the metal-support interface may influence the electronic properties of metal clusters and thus their reactivity for absorption of the reactant molecules.

Keywords: metal-support interaction, supported metal catalysts, synchrotron radiation, X-ray absorption spectroscopy, X-raydiffraction

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Authors: Dipankar Dhabak, Soumya Pandit

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This paper presents an adaptive technique for generation of data required for construction of artificial neural network-based performance model of nano-scale CMOS inverter circuit. The training data are generated from the samples through SPICE simulation. The proposed algorithm has been compared to standard progressive sampling algorithms like arithmetic sampling and geometric sampling. The advantages of the present approach over the others have been demonstrated. The ANN predicted results have been compared with actual SPICE results. A very good accuracy has been obtained.

Keywords: CMOS Inverter, Nano-scale, Adaptive Sampling, ArtificialNeural Network

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Authors: M. Zamin Khan, Yanjie Wang, R. Raut

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A 1V, 1GHz low noise amplifier (LNA) has been designed and simulated using Spectre simulator in a standard TSMC 0.18um CMOS technology.With low power and noise optimization techniques, the amplifier provides a gain of 24 dB, a noise figure of only 1.2 dB, power dissipation of 14 mW from a 1 V power supply.

Keywords:

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Authors: Neslihan Yuca, Nilgün Karatepe, Fahrettin Yakuphanoğlu

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Carbon nanotubes (CNTs) possess unique structural, mechanical, thermal and electronic properties, and have been proposed to be used for applications in many fields. However, to reach the full potential of the CNTs, many problems still need to be solved, including the development of an easy and effective purification procedure, since synthesized CNTs contain impurities, such as amorphous carbon, carbon nanoparticles and metal particles. Different purification methods yield different CNT characteristics and may be suitable for the production of different types of CNTs. In this study, the effect of different purification chemicals on carbon nanotube quality was investigated. CNTs were firstly synthesized by chemical vapor deposition (CVD) of acetylene (C2H2) on a magnesium oxide (MgO) powder impregnated with an iron nitrate (Fe(NO3)3·9H2O) solution. The synthesis parameters were selected as: the synthesis temperature of 800°C, the iron content in the precursor of 5% and the synthesis time of 30 min. The liquid phase oxidation method was applied for the purification of the synthesized CNT materials. Three different acid chemicals (HNO3, H2SO4, and HCl) were used in the removal of the metal catalysts from the synthesized CNT material to investigate the possible effects of each acid solution to the purification step. Purification experiments were carried out at two different temperatures (75 and 120 °C), two different acid concentrations (3 and 6 M) and for three different time intervals (6, 8 and 15 h). A 30% H2O2 : 3M HCl (1:1 v%) solution was also used in the purification step to remove both the metal catalysts and the amorphous carbon. The purifications using this solution were performed at the temperature of 75°C for 8 hours. Purification efficiencies at different conditions were evaluated by thermogravimetric analysis. Thermal and electrical properties of CNTs were also determined. It was found that the obtained electrical conductivity values for the carbon nanotubes were typical for organic semiconductor materials and thermal stabilities were changed depending on the purification chemicals.

Keywords: Carbon nanotubes, purification, acid digestion, thermalstability, electrical conductivity

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Authors: Nwe Nwe Soe, Lwin Thuzar Shwe, Kay Thi Lwin

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Lanthanum oxide is to be recovered from monazite, which contains about 13.44% lanthanum oxide. The principal objective of this study is to be able to extract lanthanum oxide from monazite of Moemeik Myitsone Area. The treatment of monazite in this study involves three main steps; extraction of lanthanum hydroxide from monazite by using caustic soda, digestion with nitric acid and precipitation with ammonium hydroxide and calcination of lanthanum oxalate to lanthanum oxide.

Keywords: Calcination, Digestion, Precipitation.

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Authors: R. M. López-Gutiérrez, L. Cardoza-Avendaño, H. Cervantes-De Ávila, J. A. Michel-Macarty, C. Cruz-Hernández, A. Arellano-Delgado, R. Carmona-Rodríguez

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In this paper, synchronization of multiple chaotic semiconductor lasers is achieved by appealing to complex system theory. In particular, we consider dynamical networks composed by semiconductor laser, as interconnected nodes, where the interaction in the networks are defined by coupling the first state of each node. An interest case is synchronized with master-slave configuration in star topology. Nodes of these networks are modeled for the laser and simulate by Matlab. These results are applicable to private communication.

Keywords: Synchronization, chaotic laser, network.

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Authors: T. Brettschneider, C. Dorrer, H. Suy, T. Braun, E. Jung, R. Hoofman, M. Bründel, R. Zengerle, F. Lärmer

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We present an integration approach of a CMOS biosensor into a polymer based microfluidic environment suitable for mass production. It consists of a wafer-level-package for the silicon die and laser bonding process promoted by an intermediate hot melt foil to attach the sensor package to the microfluidic chip, without the need for dispensing of glues or underfiller. A very good condition of the sensing area was obtained after introducing a protection layer during packaging. A microfluidic flow cell was fabricated and shown to withstand pressures up to Δp = 780 kPa without leakage. The employed biosensors were electrically characterized in a dry environment.

Keywords: CMOS biosensor, laser bonding, silicon polymer integration, wafer level packaging.

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Authors: K. E. Kaharudin, A. H. Hamidon, F. Salehuddin

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Vertical Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is believed to suppress various short channel effect problems. The gate to channel coupling in vertical DG-MOSFET are doubled, thus resulting in higher current density. By having two gates, both gates are able to control the channel from both sides and possess better electrostatic control over the channel. In order to ensure that the transistor possess a superb turn-off characteristic, the subs-threshold swing (SS) must be kept at minimum value (60-90mV/dec). By utilizing SILVACO TCAD software, an n-channel vertical DG-MOSFET was successfully designed while keeping the sub-threshold swing (SS) value as minimum as possible. From the observation made, the value of sub-threshold swing (SS) was able to be varied by adjusting the height of the silicon pillar. The minimum value of sub-threshold swing (SS) was found to be 64.7mV/dec with threshold voltage (V_TH) of 0.895V. The ideal height of the vertical DG-MOSFET pillar was found to be at 0.265 µm.

Keywords: DG-MOSFET, pillar, SCE, vertical

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Authors: Sae-Rom Pak, Seung Hwan Park, Jeong Ho Cho, Daewoong An, Cheong-Sool Park, Jun Seok Kim, Jun-Geol Baek

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It is important to predict yield in semiconductor test process in order to increase yield. In this study, yield prediction means finding out defective die, wafer or lot effectively. Semiconductor test process consists of some test steps and each test includes various test items. In other world, test data has a big and complicated characteristic. It also is disproportionably distributed as the number of data belonging to FAIL class is extremely low. For yield prediction, general data mining techniques have a limitation without any data preprocessing due to eigen properties of test data. Therefore, this study proposes an under-sampling method using support vector machine (SVM) to eliminate an imbalanced characteristic. For evaluating a performance, randomly under-sampling method is compared with the proposed method using actual semiconductor test data. As a result, sampling method using SVM is effective in generating robust model for yield prediction.

Keywords: Yield Prediction, Semiconductor Test Process, Support Vector Machine, Under Sampling

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Authors: Indah Kurniawaty, Yoki Yulizar, Haryo Satrya Oktaviano, Adam Kusuma Rianto

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Magnesium oxide nanoparticles (MgO NP) were successfully synthesized in this study using a one-pot green synthesis mediated by Calliandra calothyrsus leaf extract (CLE). CLE was prepared by maceration of the leaf using methanol with a ratio of 1:5 for 7 days. Secondary metabolites in CLE, such as alkaloids and flavonoids, served as a weak base provider and capping agent in the formation of MgO NP. CLE Fourier Transform Infra-Red (FTIR) spectra peak at 3255 cm-1, 1600 cm-1, 1384 cm-1, 1205 cm-1, 1041 cm-1, and 667 cm-1 showing the presence of vibrations O-H stretching, N-H bending, C-C stretching, C-N stretching and N-H wagging. During the experiment, different CLE volumes and calcined temperatures were used, resulting in a variety of structures. Energy Dispersive X-ray Spectrometer (EDS) and FTIR were used to characterize metal oxide particles. MgO diffraction patterns at 2θ of 36.9°; 42.9°; 62.2°; 74.6°; and 78.5° can be assigned to crystal planes (111), (200), (220), (311), and (222), respectively. Scanning Electron Microscopy (SEM) was used to characterize the surface morphology. The morphology ranged from sphere to flower-like resulting in crystallite sizes of 28 nm, 23 nm, 12 nm, and 9 nm.

Keywords: Calliandra calothyrsus, green-synthesis, magnesium oxide, nanoparticle.

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Authors: Ki-Young Kim, Jae-Ho Lim, Deok-Min Kim, Seok-Yoon Kim

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Average current analysis checking the impact of current flow is very important to guarantee the reliability of semiconductor systems. As semiconductor process technologies improve, the coupling capacitance often become bigger than self capacitances. In this paper, we propose an analytic technique for analyzing average current on interconnects in multi-conductor structures. The proposed technique has shown to yield the acceptable errors compared to HSPICE results while providing computational efficiency.

Keywords: current moment, interconnect modeling, reliability analysis, worst-case switching

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Authors: Hung-Pei Hsu, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Ming-Tsung Shih, Chan-Hsiang Chang, Shih-Chuan Tseng, Min-Yan Lin, Shih-Wen Hsu

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In this paper, we propose a novel metal oxide semiconductor field effect transistor with L-shaped channel structure (LMOS), and several type of L-shaped structures are also designed, studied and compared with the conventional MOSFET device for the same average gate length (Lavg). The proposed device electrical characteristics are analyzed and evaluated by three dimension (3-D) ISE-TCAD simulator. It can be confirmed that the LMOS devices have higher on-state drain current and both lower drain-induced barrier lowering (DIBL) and subthreshold swing (S.S.) than its conventional counterpart has. In addition, the transconductance and voltage gain properties of the LMOS are also improved.

Keywords: Average gate length (Lavg), drain-induced barrier lowering (DIBL), L-shaped channel MOSFET (LMOS), subthreshold swing (S.S.).

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Authors: Saleh H. Abud, Z. Hassan, F. K. Yam

Abstract:

Characteristics of MSM photodetector based on a porous In_0.08Ga_0.92N thin film were reported. Nanoporous structures of n-type In_0.08Ga_0.92N/AlN/Si thin films were synthesized by photoelectrochemical (PEC) etching at a ratio of 1:4 of HF:C₂H₅OH solution for 15min. The structural and optical properties of pre- and post-etched thin films were investigated. Field emission scanning electron microscope and atomic force microscope images showed that the pre-etched thin film has a sufficiently smooth surface over a large region and the roughness increased for porous film. Blue shift has been observed in photoluminescence emission peak at 300 K for porous sample. The photoluminescence intensity of the porous film indicated that the optical properties have been enhanced. A high work function metals (Pt and Ni) were deposited as a metal contact on the porous films. The rise and recovery times of the devices were investigated at 390nm chopped light. Finally, the sensitivity and quantum efficiency were also studied.

Keywords: Porous InGaN, photoluminescence, SMS photodetector.

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Authors: Padmanabhan Balasubramanian, C. Ardil

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In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.

Keywords: Reed-Muller forms, Logic function, Hammingdistance, Algebraic factorization, Low power design.

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Authors: P. Acosta-Santamaría, A. Ibatá-Soto, A. López-Vásquez

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Organic compounds in wastewaters coming from textile and pharmaceutical industry generated multiple harmful effects on the environment and the human health. One of them is the methyl orange (MeO), an azoic dye considered to be a recalcitrant compound. The heterogeneous photocatalysis emerges as an alternative for treating this type of hazardous compounds, through the generation of OH radicals using radiation and a semiconductor oxide. According to the author’s knowledge, catalysts such as TiO₂ doped with metals show high efficiency in degrading MeO; however, this presents economic limitations on industrial scale. Black sand can be considered as a naturally doped catalyst because in its structure is common to find compounds such as titanium, iron and aluminum oxides, also elements such as zircon, cadmium, manganese, etc. This study reports the photocatalytic activity of the mineral black sand used as semiconductor in the discoloration of MeO by oxidation and reduction photocatalytic techniques. For this, magnetic composites from the mineral were prepared (RM, M1, M2 and NM) and their activity were tested through MeO discoloration while TiO₂ was used as reference. For the fractions, chemical, morphological and structural characterizations were performed using Scanning Electron Microscopy with Energy Dispersive X-Ray (SEM-EDX), X-Ray Diffraction (XRD) and X-Ray Fluorescence (XRF) analysis. M2 fraction showed higher MeO discoloration (93%) in oxidation conditions at pH 2 and it could be due to the presence of ferric oxides. However, the best result to reduction process was using M1 fraction (20%) at pH 2, which contains a higher titanium percentage. In the first process, hydrogen peroxide (H₂O₂) was used as electron donor agent. According to the results, black sand mineral can be used as natural semiconductor in photocatalytic process. It could be considered as a photocatalyst precursor in such processes, due to its low cost and easy access.

Keywords: Black sand mineral, methyl orange, oxidation, photocatalysis, reduction.

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Authors: T. P. Lu, B. N. Hwang, T. Z. Liou, Y. L. Lin

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Developing a supply chain management (SCM) system is costly, but important. However, because of its complicated nature, not many of such projects are considered successful. Few research publications directly relate to key success factors (KSFs) for implementing a SCM system. Motivated by the above, this research proposes a hierarchy of KSFs for SCM system implementation in the semiconductor industry by using a two-step approach. First, the literature review indicates the initial hierarchy. The second step includes a focus group approach to finalize the proposed KSF hierarchy by extracting valuable experiences from executives and managers that actively participated in a project, which successfully establish a seamless SCM integration between the world's largest semiconductor foundry manufacturing company and the world's largest assembly and testing company. Future project executives may refer the resulting KSF hierarchy as a checklist for SCM system implementation in semiconductor or related industries.

Keywords: Focus group, key success factors, supply chain management, semiconductor industry.

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Authors: Aïssa Manallah, Mohamed Bouafia

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Ellipsometry is an optical method based on the study of the behavior of polarized light. The light reflected on a surface induces a change in the polarization state which depends on the characteristics of the material (complex refractive index and thickness of the different layers constituting the device). The purpose of this work is to determine the optical properties of semiconductor thin films by ellipsometry. This paper describes the experimental aspects concerning the semiconductor samples, the SE400 ellipsometer principle, and the results obtained by direct measurements of ellipsometric parameters and modelling using appropriate software.

Keywords: Ellipsometry, optical constants, semiconductors, thin films.

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Authors: Zhenguo Vincent Chia, Sheung Yan Simon Ng, Minkyu Je

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This paper presents CMOS Current Mode Logic (CML) circuits for a high speed Digital to Analog Converter (DAC) using standard CMOS 65nm process. The CML circuits have the propagation delay advantage over its conventional CMOS counterparts due to smaller output voltage swing and tunable bias current. The CML circuits proposed in this paper can achieve a maximum propagation delay of only 9.3ps, which can satisfy the stringent requirement for the 5 GHz high speed DAC application. Another advantage for CML circuits is its dynamic symmetry characteristic resulting in a reduction of an additional inverter. Simulation results show that the proposed CML circuits can operate from 1.08V to 1.3V with temperature ranging from -40 to +120°C.

Keywords: Conventional, Current Mode Logic, DAC, Decoder

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Authors: Ella C. Linganiso, Bonex W. Mwakikunga, Trilock Singh, Sanjay Mathur, Odireleng M. Ntwaeaborwa

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The use of nanostructured semiconducting material to catalyze degradation of environmental pollutants still receives much attention to date. One of the desired characteristics for pollutant degradation under ultra-violet visible light is the materials with extended carrier charge separation that allows for electronic transfer between the catalyst and the pollutants. In this work, zinc oxide n-type semiconductor vertically aligned structures were fabricated on silicon (100) substrates using the chemical bath deposition method. The as-synthesized structures were treated with nickel and sulphur. X-ray diffraction, scanning electron microscopy, energy dispersive X-ray spectroscopy were used to characterize the phase purity, structural dimensions and elemental composition of the obtained structures respectively. Photoluminescence emission measurements showed a decrease in both the near band edge emission as well as the defect band emission upon addition of nickel and sulphur with different concentrations. This was attributed to increased charger-carrier-separation due to the presence of Ni-S material on ZnO surface, which is linked to improved charge transfer during photocatalytic reactions.

Keywords: Carrier-charge-separation, nickel, sulphur, zinc oxide, photoluminescence.

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Authors: Kittipong Tripetch

Abstract:

This paper proposes for the first time symbolic formula of the power spectrum of CMOS Cross Couple Oscillator and its modified circuit. Many principles existed to derived power spectrum in microwave textbook such as impedance, admittance parameters, ABCD, H parameters, etc. It can be compared by graph of power spectrum which methodology is the best from the point of view of practical measurement setup such as condition of impedance parameter which used superposition of current to derived (its current injection at the other port of the circuit is zero, which is impossible in reality). Four graphs of impedance parameters of cross couple oscillator are proposed. After that four graphs of scattering parameters of CMOS cross coupled oscillator will be shown.

Keywords: Optimization, power spectrum, impedance parameter, scattering parameter.

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Authors: Arash Azizi Mazreah, Mohammad Reza Sahebi, Mohammad T. Manzuri Shalmani

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To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode.

Keywords: SRAM Cell, leakage current, cell area.

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Authors: Fasil Endalamaw

Abstract:

Digital magnitude comparators based on Gate Diffusion Input (GDI) implementation technique are high speed and area-efficient, and they consume less power as compared to other implementation techniques. However, they are less efficient for some logic gates and have no full voltage swing. In this paper, we made a performance comparison between the GDI implementation technique and other implementation methods, such as Static CMOS, Pass Transistor Logic (PTL), and Transmission Gate (TG) in 90 nm, 120 nm, and 180 nm CMOS technologies using BSIM4 MOS model. We proposed a methodology (hybrid implementation) of implementing digital magnitude comparators which significantly improved the power, speed, area, and voltage swing requirements. Simulation results revealed that the hybrid implementation of digital magnitude comparators show a 10.84% (power dissipation), 41.6% (propagation delay), 47.95% (power-delay product (PDP)) improvement compared to the usual GDI implementation method. We used Microwind & Dsch Version 3.5 as well as the Tanner EDA 16.0 tools for simulation purposes.

Keywords: Efficient, gate diffusion input, high speed, low power, CMOS.

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Authors: Ingy A. El-Khouly, Khaled S. El-Kilany, Aziz E. El-Sayed

Abstract:

The process of wafer fabrication is arguably the most technologically complex and capital intensive stage in semiconductor manufacturing. This large-scale discrete-event process is highly reentrant, and involves hundreds of machines, restrictions, and processing steps. Therefore, production control of wafer fabrication facilities (fab), specifically scheduling, is one of the most challenging problems that this industry faces. Dispatching rules have been extensively applied to the scheduling problems in semiconductor manufacturing. Moreover, lot release policies are commonly used in this manufacturing setting to further improve the performance of such systems and reduce its inherent variability. In this work, simulation is used in the scheduling of re-entrant flow shop manufacturing systems with an application in semiconductor wafer fabrication; where, a simulation model has been developed for the Intel Five-Machine Six Step Mini-Fab using the ExtendTM simulation environment. The Mini-Fab has been selected as it captures the challenges involved in scheduling the highly re-entrant semiconductor manufacturing lines. A number of scenarios have been developed and have been used to evaluate the effect of different dispatching rules and lot release policies on the selected performance measures. Results of simulation showed that the performance of the Mini-Fab can be drastically improved using a combination of dispatching rules and lot release policy.

Keywords: Dispatching rules, lot release policy, re-entrant flowshop, semiconductor manufacturing.

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Authors: Ali A. Alshatwi, Vaiyapuri S. Periasamy, Jegan Athinarayanan

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Engineered nanoparticles’ usage rapidly increased in various applications in the last decade due to their unusual properties. However, there is an ever increasing concern to understand their toxicological effect in human health. Particularly, metal and metal oxide nanoparticles have been used in various sectors including biomedical, food and agriculture. But their impact on human health is yet to be fully understood. In this present investigation, we assessed the toxic effect of engineered nanoparticles (ENPs) including Ag, MgO and Co3O4 nanoparticles (NPs) on human mesenchymal stem cells (hMSC) adopting cell viability and cellular morphological changes as tools The results suggested that silver NPs are more toxic than MgO and Co3O4NPs. The ENPs induced cytotoxicity and nuclear morphological changes in hMSC depending on dose. The cell viability decreases with increase in concentration of ENPs. The cellular morphology studies revealed that ENPs damaged the cells. These preliminary findings have implications for the use of these nanoparticles in food industry with systematic regulations.

Keywords: Cobalt oxide, Human mesenchymal stem cells, MgO, Silver.

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Authors: PoiSim Khiew, MuiYen Ho, ThianKhoonTan, WeeSiong Chiu, Roslinda Shamsudin, Muhammad Azmi Abd-Hamid, ChinHua Chia

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In the present work, we have developed a symmetric electrochemical capacitor based on the nanostructured iron oxide (Fe3O4)-activated carbon (AC) nanocomposite materials. The physical properties of the nanocomposites were characterized by Scanning Electron Microscopy (SEM) and Brunauer-Emmett-Teller (BET) analysis. The electrochemical performances of the composite electrode in 1.0 M Na2SO3 and 1.0 M Na2SO4 aqueous solutions were evaluated using cyclic voltammetry (CV) and electrochemical impedance spectroscopy (EIS). The composite electrode with 4 wt% of iron oxide nanomaterials exhibits the highest capacitance of 86 F/g. The experimental results clearly indicate that the incorporation of iron oxide nanomaterials at low concentration to the composite can improve the capacitive performance, mainly attributed to the contribution of the pseudocapacitance charge storage mechanism and the enhancement on the effective surface area of the electrode. Nevertheless, there is an optimum threshold on the amount of iron oxide that needs to be incorporated into the composite system. When this optimum threshold is exceeded, the capacitive performance of the electrode starts to deteriorate, as a result of the undesired particle aggregation, which is clearly indicated in the SEM analysis. The electrochemical performance of the composite electrode is found to be superior when Na2SO3 is used as the electrolyte, if compared to the Na2SO4 solution. It is believed that Fe3O4 nanoparticles can provide favourable surface adsorption sites for sulphite (SO3 2-) anions which act as catalysts for subsequent redox and intercalation reactions.

Keywords: Metal oxide nanomaterials, Electrochemical Capacitor, Double Layer Capacitance, Pseduocapacitance

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Authors: Z. Abdolldhi, A. A. Ziaee M., A. Afshar

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In this paper the combination of thermal oxidation and electrochemical anodizing processes is used to produce titanium oxide layers. The response of titanium alloy Ti6Al4V to oxidation processes at various temperatures and electrochemical anodizing in various voltages are investigated. Scanning electron microscopy (SEM); X-Ray Diffraction (XRD) and porosity determination have been used to characterize the oxide layer thickness, surface morphology, oxide layer-substrate adhesion and porosity. In the first experiment, samples modified by thermal oxidation process then followed by electrochemical anodizing. Second experiment consists of surfaces modified by electrochemical anodizing process and then followed by thermal oxidation. The first method shows better properties than other one. In second experiment, Surfaces modified were achieved by thicker and more adherent thick oxide layers on titanium surface. The existence of an electrochemical anodized oxide layer did not improve the adhesion of thermal oxide layer. The high temperature, thermal formation of an oxide layer leads to a coarse oxide grain morphology and a complete oxidative particle. In addition, in high temperature oxidation porosity content is increased. The oxide layer of thermal oxidation and electrochemical anodizing processes; on Ti–6Al–4V substrate was covered with different colored oxide layers.

Keywords: Electrochemically anodizing, Porosity, Thermaloxidation, Ti6Al4 alloy.

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Authors: A.Nagoor Gani, J.Malarvizhi

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In this paper, the order, size and degree of the nodes of the isomorphic fuzzy graphs are discussed. Isomorphism between fuzzy graphs is proved to be an equivalence relation. Some properties of self complementary and self weak complementary fuzzy graphs are discussed.

Keywords: complementary fuzzy graphs, co-weak isomorphism, equivalence relation, fuzzy relation, weak isomorphism.

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Authors: Youngji Yoo, Seung Hwan Park, Daewoong An, Sung-Shick Kim, Jun-Geol Baek

Abstract:

The yield management system is very important to produce high-quality semiconductor chips in the semiconductor manufacturing process. In order to improve quality of semiconductors, various tests are conducted in the post fabrication (FAB) process. During the test process, large amount of data are collected and the data includes a lot of information about defect. In general, the defect on the wafer is the main causes of yield loss. Therefore, analyzing the defect data is necessary to improve performance of yield prediction. The wafer bin map (WBM) is one of the data collected in the test process and includes defect information such as the fail bit patterns. The fail bit has characteristics of spatial point patterns. Therefore, this paper proposes the feature extraction method using the spatial point pattern analysis. Actual data obtained from the semiconductor process is used for experiments and the experimental result shows that the proposed method is more accurately recognize the fail bit patterns.

Keywords: Semiconductor, wafer bin map (WBM), feature extraction, spatial point patterns, contour map.

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Authors: M. Kheirandish, S. Borhani

Abstract:

In this experiment Polystyrene/Zinc-oxide (PS/ZnO) nanocomposite fibers were produced by electrospinning technique using limonene as a green solvent. First, the morphology of electrospun pure polystyrene (PS) and PS/ZnO nanocomposite fibers investigated by SEM. Results showed the PS fiber diameter decreased by increasing concentration of Zinc Oxide nanoparticles (ZnO NPs). Thermo Gravimetric Analysis (TGA) results showed thermal stability of nanocomposites increased by increasing ZnO NPs in PS electrospun fibers. Considering Differential Scanning Calorimeter (DSC) thermograms for electrospun PS fibers indicated that introduction of ZnO NPs into fibers affects the glass transition temperature (Tg) by reducing it. Also, UV protection properties of nanocomposite fibers were increased by increasing ZnO concentration. Evaluating the effect of metal oxide NPs amount on mechanical properties of electrospun layer showed that tensile strength and elasticity modulus of the electrospun layer of PS increased by addition of ZnO NPs. X-ray diffraction (XRD) pattern of nanopcomposite fibers confirmed the presence of NPs in the samples.

Keywords: Electrospininng, nanoparticle, polystyrene, ZnO.

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Authors: Spyridon Nikolaidis

Abstract:

A modeling approach for CMOS gates is presented based on the use of the equivalent inverter. A new model for the inverter has been developed using a simplified transistor current model which incorporates the nanoscale effects for the planar technology. Parametric expressions for the output voltage are provided as well as the values of the output and supply current to be compatible with the CCS technology. The model is parametric according the input signal slew, output load, transistor widths, supply voltage, temperature and process. The transistor widths of the equivalent inverter are determined by HSPICE simulations and parametric expressions are developed for that using a fitting procedure. Results for the NAND gate shows that the proposed approach offers sufficient accuracy with an average error in propagation delay about 5%.

Keywords: CMOS gate modeling, Inverter modeling, transistor current model, timing model.

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