Search results for: wafer bin map (WBM)

Authors: Ian Kree, Davina Chin Lee Yien

Abstract:

This paper presents Cost per Equivalent Wafer Out, which we find useful in wafer fab operational cost monitoring and controlling. It removes the loading and product mix effect in the cost variance analysis. The operation heads, therefore, could immediately focus on identifying areas for cost improvement. Without this, they would have to measure the impact of the loading variance and product mix variance between actual and budgeted prior to make any decision on cost improvement. Cost per Equivalent Wafer Out, thereby, increases efficiency in wafer fab operational cost monitoring and controlling.

Keywords: Cost Control, Cost Variance, Operational Expenditure, Semiconductor.

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Authors: Tim Giesen, Christian Fischmann, Fabian Böttinger, Alexander Ehm, Alexander Verl

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In a state-of-the-art industrial production line of photovoltaic products the handling and automation processes are of particular importance and implication. While processing a fully functional crystalline solar cell an as-cut photovoltaic wafer is subject to numerous repeated handling steps. With respect to stronger requirements in productivity and decreasing rejections due to defects the mechanical stress on the thin wafers has to be reduced to a minimum as the fragility increases by decreasing wafer thicknesses. In relation to the increasing wafer fragility, researches at the Fraunhofer Institutes IPA and CSP showed a negative correlation between multiple handling processes and the wafer integrity. Recent work therefore focused on the analysis and optimization of the dry wafer stack separation process with compressed air. The achievement of a wafer sensitive process capability and a high production throughput rate is the basic motivation in this research.

Keywords: Automation, Photovoltaic Manufacturing, Thin Wafer, Material Handling

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Authors: Z. W. Zhong, C. Xu, W. K. Choi

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To build a thin fan-out wafer-level package, the package had to be ground to a thin level. In this work, the influence of the grinding processes on the strength of the fan-out wafer-level packages was investigated. After different grinding processes, all specimens were placed on a three-point-bending fixture installed on a universal tester for three-point-bending testing, and the strength of the fan-out wafer-level packages was measured. The experiments revealed that the average flexure strength increased with the decreasing surface roughness height of the fan-out wafer-level package tested. The grinding processes had a significant influence on the strength of the fan-out wafer-level packages investigated.

Keywords: FOWLP strength, surface roughness, three-point bending, grinding.

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Authors: Sheng-Ming Huang, Nan-Chyuan Tsai, Chih-Che Lin, Chun-Chi Lin

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An innovative design for intelligent Chemical Mechanical Polishing (CMP) system is proposed and verified by experiments in this report. On-line measurement and real-time feedback are integrated to eliminate the shortcomings of traditional approaches, e.g., the batch-to-batch discrepancy of required polishing time, over consumption of chemical slurry, and non-uniformity across the wafer. The major advantage of the proposed method is that the finish of local surface roughness can be consistent, no matter where the inner-ring region or outer-ring region is concerned. Secondly, it is able to eliminate the Edge effect. Conventionally, the interfacial induced stress near the wafer edge is generally much higher than that near the wafer center. At last, by using the proposed intelligent chemical mechanical polishing strategy, the cost of the entire machining cycle can be much reduced while the quality of the finished goods certainly upgraded.

Keywords: Chemical Mechanical Polishing, Active Magnetic Actuator, On-Line Measurement.

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Authors: N. Asadi, M. Jackson

Abstract:

Today, the central role of industrial robots in automation in general and in material handling in particular is crystal clear. Based on the current status of Photovoltaics and by focusing on lightweight material handling, PV industry has turned into a potential candidate for introducing a fresh “pick and place" robot technology. Thus, to examine the industry needs in this regard, firstly the best suited applications for such robotic automation,and then the essential prerequisites in PV industry should be identified. The objective of this paper is to present holistic views on the industry trends, general automation status and existing challenges facing lightweight robotic material handling in PV Silicon Wafer and Thin Film technologies. The results of this study show that currently no uniform pick and place solution prevails among PV Silicon Wafer manufacturers and the industry calls for a new robot solution to satisfy its needs in new directions.

Keywords: Automation, Material handling, Photovoltaic, Robot.

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Authors: Vincent King Soon Wong, Hong Seng Ng, Florinna Sim

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Negative Bias Temperature Instability (NBTI) is one of the critical degradation mechanisms in semiconductor device reliability that causes shift in the threshold voltage (Vth). However, thorough understanding of this reliability failure mechanism is still unachievable due to a recovery characteristic known as NBTI recovery. This paper will demonstrate the severity of NBTI recovery as well as one of the effective methods used to mitigate, which is the minimization of measurement system delays. Comparison was done in between two measurement systems that have significant differences in measurement delays to show how NBTI recovery causes result deviations and how fast measurement systems can mitigate NBTI recovery. Another method to minimize NBTI recovery without the influence of measurement system known as Fast Wafer Level Reliability (FWLR) NBTI was also done to be used as reference.

Keywords: Fast vs slow BTI, Fast wafer level reliability, Negative bias temperature instability, NBTI measurement system, metal-oxide-semiconductor field-effect transistor, MOSFET, NBTI recovery, reliability.

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Authors: Youngji Yoo, Seung Hwan Park, Daewoong An, Sung-Shick Kim, Jun-Geol Baek

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The yield management system is very important to produce high-quality semiconductor chips in the semiconductor manufacturing process. In order to improve quality of semiconductors, various tests are conducted in the post fabrication (FAB) process. During the test process, large amount of data are collected and the data includes a lot of information about defect. In general, the defect on the wafer is the main causes of yield loss. Therefore, analyzing the defect data is necessary to improve performance of yield prediction. The wafer bin map (WBM) is one of the data collected in the test process and includes defect information such as the fail bit patterns. The fail bit has characteristics of spatial point patterns. Therefore, this paper proposes the feature extraction method using the spatial point pattern analysis. Actual data obtained from the semiconductor process is used for experiments and the experimental result shows that the proposed method is more accurately recognize the fail bit patterns.

Keywords: Semiconductor, wafer bin map (WBM), feature extraction, spatial point patterns, contour map.

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Authors: Ingy A. El-Khouly, Khaled S. El-Kilany, Aziz E. El-Sayed

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The process of wafer fabrication is arguably the most technologically complex and capital intensive stage in semiconductor manufacturing. This large-scale discrete-event process is highly reentrant, and involves hundreds of machines, restrictions, and processing steps. Therefore, production control of wafer fabrication facilities (fab), specifically scheduling, is one of the most challenging problems that this industry faces. Dispatching rules have been extensively applied to the scheduling problems in semiconductor manufacturing. Moreover, lot release policies are commonly used in this manufacturing setting to further improve the performance of such systems and reduce its inherent variability. In this work, simulation is used in the scheduling of re-entrant flow shop manufacturing systems with an application in semiconductor wafer fabrication; where, a simulation model has been developed for the Intel Five-Machine Six Step Mini-Fab using the ExtendTM simulation environment. The Mini-Fab has been selected as it captures the challenges involved in scheduling the highly re-entrant semiconductor manufacturing lines. A number of scenarios have been developed and have been used to evaluate the effect of different dispatching rules and lot release policies on the selected performance measures. Results of simulation showed that the performance of the Mini-Fab can be drastically improved using a combination of dispatching rules and lot release policy.

Keywords: Dispatching rules, lot release policy, re-entrant flowshop, semiconductor manufacturing.

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Authors: T. Brettschneider, C. Dorrer, H. Suy, T. Braun, E. Jung, R. Hoofman, M. Bründel, R. Zengerle, F. Lärmer

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We present an integration approach of a CMOS biosensor into a polymer based microfluidic environment suitable for mass production. It consists of a wafer-level-package for the silicon die and laser bonding process promoted by an intermediate hot melt foil to attach the sensor package to the microfluidic chip, without the need for dispensing of glues or underfiller. A very good condition of the sensing area was obtained after introducing a protection layer during packaging. A microfluidic flow cell was fabricated and shown to withstand pressures up to Δp = 780 kPa without leakage. The employed biosensors were electrically characterized in a dry environment.

Keywords: CMOS biosensor, laser bonding, silicon polymer integration, wafer level packaging.

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Authors: Sheng-Shu Cheng, Fong-Jung Yu

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C-control chart assumes that process nonconformities follow a Poisson distribution. In actuality, however, this Poisson distribution does not always occur. A process control for semiconductor based on a Poisson distribution always underestimates the true average amount of nonconformities and the process variance. Quality is described more accurately if a compound Poisson process is used for process control at this time. A cumulative sum (CUSUM) control chart is much better than a C control chart when a small shift will be detected. This study calculates one-sided CUSUM ARLs using a Markov chain approach to construct a CUSUM control chart with an underlying Poisson-Gamma compound distribution for the failure mechanism. Moreover, an actual data set from a wafer plant is used to demonstrate the operation of the proposed model. The results show that a CUSUM control chart realizes significantly better performance than EWMA.

Keywords: Nonconformities, Compound Poisson distribution, CUSUM control chart.

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Authors: Luc Conti, Dimitry Dumont-Fillon, Harald van Lintel, Eric Chappel

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Flow control valves comprise a silicon flexible membrane that deflects against a substrate, usually made of glass, containing pillars, an outlet hole, and anti-stiction features. However, there is a strong interest in using silicon instead of glass as substrate material, as it would simplify the process flow by allowing the use of well controlled anisotropic etching. Moreover, specific devices demanding a bending of the substrate would also benefit from the inherent outstanding mechanical strength of monocrystalline silicon. Unfortunately, direct Si-Si bonding is not easily achieved with highly structured wafers since residual stress may prevent the good adhesion between wafers. Using a thermoplastic polymer, such as parylene, as intermediate layer is not well adapted to this design as the wafer-to-wafer alignment is critical. An alternative anodic bonding method using an intermediate borosilicate layer has been successfully tested. This layer has been deposited onto the silicon substrate. The bonding recipe has been adapted to account for the presence of the SOI buried oxide and intermediate glass layer in order not to exceed the breakdown voltage. Flow control valves dedicated to infusion of viscous fluids at very high pressure have been made and characterized. The results are compared to previous data obtained using the standard anodic bonding method.

Keywords: Anodic bonding, evaporated glass, microfluidic valve, drug delivery.

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Authors: T. Patcharawit, C. Kansomket, N. Wongnaree, W. Kritsrikan, T. Yingnakorn, S. Khumkoa

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Recovery of pure copper and silver from end-of-life photovoltaic (PV) panels was investigated in this paper using an effective hybrid pyro-hydrometallurgical process. In the first step of waste treatment, solar panel waste was first dismantled to obtain a PV sheet to be cut and calcined at 500 °C, to separate out PV ribbon from glass cullet, ash, and volatile while the silicon wafer containing silver finger was collected for recovery. In the second step of metal recovery, copper recovery from PV ribbon was via 1-3 M HCl leaching with SnCl₂ and H₂O₂ additions in order to remove the tin-lead coating on the ribbon. The leached copper band was cleaned and subsequently melted as an anode for the next step of electrorefining. Stainless steel was set as the cathode with CuSO₄ as an electrolyte, and at a potential of 0.2 V, high purity copper of 99.93% was obtained at 96.11% recovery after 24 hours. For silver recovery, the silicon wafer containing silver finger was leached using HNO₃ at 1-4 M in an ultrasonic bath. In the next step of precipitation, silver chloride was then obtained and subsequently reduced by sucrose and NaOH to give silver powder prior to oxy-acetylene melting to finally obtain pure silver metal. The integrated recycling process is considered to be economical, providing effective recovery of high purity metals such as copper and silver while other materials such as aluminum, copper wire, glass cullet can also be recovered to be reused commercially. Compounds such as PbCl₂ and SnO₂ obtained can also be recovered to enter the market.

Keywords: Electrorefining, leaching, calcination, PV ribbon, silver finger, solar panel.

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Authors: C. Virgilio, J. Carlier, P. Campistron, M. Toubal, P. Garnier, L. Broussous, V. Thomy, B. Nongaillard

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Wetting efficiency of microstructures or nanostructures patterned on Si wafers is a real challenge in integrated circuits manufacturing. In fact, bad or non-uniform wetting during wet processes limits chemical reactions and can lead to non-complete etching or cleaning inside the patterns and device defectivity. This issue is more and more important with the transistors size shrinkage and concerns mainly high aspect ratio structures. Deep Trench Isolation (DTI) structures enabling pixels’ isolation in imaging devices are subject to this phenomenon. While low-frequency acoustic reflectometry principle is a well-known method for Non Destructive Test applications, we have recently shown that it is also well suited for nanostructures wetting characterization in a higher frequency range. In this paper, we present a high-frequency acoustic reflectometry characterization of DTI wetting through a confrontation of both experimental and modeling results. The acoustic method proposed is based on the evaluation of the reflection of a longitudinal acoustic wave generated by a 100 µm diameter ZnO piezoelectric transducer sputtered on the silicon wafer backside using MEMS technologies. The transducers have been fabricated to work at 5 GHz corresponding to a wavelength of 1.7 µm in silicon. The DTI studied structures, manufactured on the wafer frontside, are crossing trenches of 200 nm wide and 4 µm deep (aspect ratio of 20) etched into a Si wafer frontside. In that case, the acoustic signal reflection occurs at the bottom and at the top of the DTI enabling its characterization by monitoring the electrical reflection coefficient of the transducer. A Finite Difference Time Domain (FDTD) model has been developed to predict the behavior of the emitted wave. The model shows that the separation of the reflected echoes (top and bottom of the DTI) from different acoustic modes is possible at 5 Ghz. A good correspondence between experimental and theoretical signals is observed. The model enables the identification of the different acoustic modes. The evaluation of DTI wetting is then performed by focusing on the first reflected echo obtained through the reflection at Si bottom interface, where wetting efficiency is crucial. The reflection coefficient is measured with different water / ethanol mixtures (tunable surface tension) deposited on the wafer frontside. Two cases are studied: with and without PFTS hydrophobic treatment. In the untreated surface case, acoustic reflection coefficient values with water show that liquid imbibition is partial. In the treated surface case, the acoustic reflection is total with water (no liquid in DTI). The impalement of the liquid occurs for a specific surface tension but it is still partial for pure ethanol. DTI bottom shape and local pattern collapse of the trenches can explain these incomplete wetting phenomena. This high-frequency acoustic method sensitivity coupled with a FDTD propagative model thus enables the local determination of the wetting state of a liquid on real structures. Partial wetting states for non-hydrophobic surfaces or low surface tension liquids are then detectable with this method.

Keywords: Wetting, acoustic reflectometry, gigahertz, semiconductor.

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Authors: N. Santatriniaina, J. Deseure, T.Q. Nguyen, H. Fontaine, C. Beitia, L. Rakotomanana

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Nowadays, with the increasing of the wafer's size and the decreasing of critical size of integrated circuit manufacturing in modern high-tech, microelectronics industry needs a maximum attention to challenge the contamination control. The move to 300 [mm] is accompanied by the use of Front Opening Unified Pods for wafer and his storage. In these pods an airborne cross contamination may occur between wafers and the pods. A predictive approach using modeling and computational methods is very powerful method to understand and qualify the AMCs cross contamination processes. This work investigates the required numerical tools which are employed in order to study the AMCs cross-contamination transfer phenomena between wafers and FOUPs. Numerical optimization and finite element formulation in transient analysis were established. Analytical solution of one dimensional problem was developed and the calibration process of physical constants was performed. The least square distance between the model (analytical 1D solution) and the experimental data are minimized. The behavior of the AMCs intransient analysis was determined. The model framework preserves the classical forms of the diffusion and convection-diffusion equations and yields to consistent form of the Fick's law. The adsorption process and the surface roughness effect were also traduced as a boundary condition using the switch condition Dirichlet to Neumann and the interface condition. The methodology is applied, first using the optimization methods with analytical solution to define physical constants, and second using finite element method including adsorption kinetic and the switch of Dirichlet to Neumann condition.

Keywords: AMCs, FOUP, cross-contamination, adsorption, diffusion, numerical analysis, wafers, Dirichlet to Neumann, finite elements methods, Fick’s law, optimization.

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Authors: Wai Pan Chan, Minkyu Je

Abstract:

A precision CMOS chopping amplifier is adopted in this work to improve a CMOS temperature sensor high sensitive enough for intracranial temperature monitoring. An amplified temperature sensitivity of 18.8 ± 3*0.2 mV/oC is attained over the temperature range from 20 oC to 80 oC from a given 10 samples of the same wafer. The analog frontend design outputs the temperature dependent and the temperature independent signals which can be directly interfaced to a 10 bit ADC to accomplish an accurate temperature instrumentation system.

Keywords: Chopping, analog frontend, CMOS temperature sensor, traumatic brain injury (TBI), intracranial temperature monitoring.

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Authors: Siti Kudnie Sahari, Jane Chai Hai Sing, Khairuddin Ab. Hamid

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Shrunken patterning for integrated device manufacturing requires surface cleanliness and surface smoothness in wet chemical processing [1]. It is necessary to control all process parameters perfectly especially for the common cleaning technique RCA clean (SC-1 and SC-2) [2]. In this paper the characteristic and effect of surface preparation parameters are discussed. The properties of RCA wet chemical processing in silicon technology is based on processing time, temperature, concentration and megasonic power of SC-1 and QDR. An improvement of wafer surface preparation by the enhanced variables of the wet cleaning chemical process is proposed.

Keywords: RCA, SC-1, SC-2, QDR

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Authors: L. Chen, X. P. Ouyang, Z. B. Zhang, J. F. Zhang, J. L. Liu

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Ultrafast doped zinc oxide crystal promised us a good opportunity to build new instruments for ICF fusion neutron measurement. Two pulsed neutron detectors based on ZnO crystal wafer have been conceptually designed, the superfast ZnO timing detector and the scintillation recoil proton neutron detection system. The structure of these detectors was presented, and some characters were studied as well. The new detectors could be much faster than existing systems, and would be more competent for ICF neutron diagnostics.

Keywords: ICF fusion neutron detection, proton recoil telescope, superfast timing, ZnO crystal

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Authors: Qing Fang, Lianxi Jia, Junfeng Song, Chao Li, Xianshu Luo, Mingbin Yu, Guoqiang Lo

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In this paper, we demonstrated a 1 × 4 silicon photonic cascaded arrayed waveguide grating, which is fabricated on a SOI wafer with a 220 nm top Si layer and a 2µm buried oxide layer. The measured on-chip transmission loss of this cascaded arrayed waveguide grating is ~ 5.6 dB, including the fiber-to-waveguide coupling loss. The adjacent crosstalk is 33.2 dB. Compared to the normal single silicon photonic arrayed waveguide grating with a crosstalk of ~ 12.5 dB, the crosstalk of this device has been dramatically increased.

Keywords: Silicon photonic, arrayed waveguide grating, high-crosstalk, cascaded structure.

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Authors: A. Karsenty, A. Chelly

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Ultrathin (UTD) and Nanoscale (NSD) SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46nm and 1.6nm respectively, were fabricated using a selective “gate recessed” process on the same silicon wafer. The electrical transport characterization at room temperature has shown a large difference between the two kinds of devices and has been interpreted in terms of a huge unexpected series resistance. Electrical characteristics of the Nanoscale device, taken in the linear region, can be analytically derived from the ultrathin device ones. A comparison of the structure and composition of the layers, using advanced techniques such as Focused Ion Beam (FIB) and High Resolution TEM (HRTEM) coupled with Energy Dispersive X-ray Spectroscopy (EDS), contributes an explanation as to the difference of transport between the devices.

Keywords: Nanoscale Devices, SOI MOSFET, Analytical Model, Electron Transport.

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Authors: Kuan-Yu Chiu, Yin-Hsuan Chen, Tung-Han Chuang

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Ti/Ni/Ag/Sn-metallized Si chips were bonded to Ni/Pd/Au-surface finished DBC (Direct Bonding Copper) alumina substrate through the formation of an Ag3Sn intermetallic interlayer by solid–liquid interdiffusion bonding method. The results indicated that the holes and gaps at the bonding interface could be effectively prevented. The intermetallic phases at the bonding interface between the Si/Ti/Ni/Ag/Sn wafer and the DBC substrate were identified as Ag3Sn, Ni3Sn4, and Ni3Sn2. The average bonding strength was about 19.75 MPa, and the maximum bonding strength reached 35.24 MPa.

Keywords: BGBM, Backside Grinding and Backside Metallization, SLID bonding, Solid–liquid Interdiffusion Bonding, Si/Ti/Ni/Sn, Si/Ti/Ni/Ag/Sn, intermetallic compound.

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Authors: W. Z. Wang, S. Todd, S. B. Dolmanan, K. B. Lee, L. Yuan, H. F. Sun, S. L. Selvaraj, M.Krishnakumar, G. Q. Lo, S. Tripathy

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The crystalline quality of the AlGaN/GaN high electron mobility transistor (HEMT) structure grown on a 200 mm silicon substrate has been investigated using UV-visible micro- Raman scattering and photoluminescence (PL). The visible Raman scattering probes the whole nitride stack with the Si substrate and shows the presence of a small component of residual in-plane stress in the thick GaN buffer resulting from a wafer bowing, while the UV micro-Raman indicates a tensile interfacial stress induced at the top GaN/AlGaN/AlN layers. PL shows a good crystal quality GaN channel where the yellow band intensity is very low compared to that of the near-band-edge transition. The uniformity of this sample is shown by measurements from several points across the epiwafer.

Keywords: Raman, photo luminescence, AlGaN/GaN, HEMT.

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Authors: J. Mohammadpour, G. E. Lau, S. Cheng, A. Lee

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Numerical study was conducted using two synthetic jet actuators attached underneath a micro-channel. By fixing the oscillating frequency and diaphragm amplitude, the effects on the heat transfer within the micro-channel were investigated with two synthetic jets being in-phase and 180° out-of-phase at different orifice spacing. There was a significant benefit identified with two jets being 180° out-of-phase with each other at the orifice spacing of 2 mm. By having this configuration, there was a distinct pattern of vortex forming which disrupts the main channel flow as well as promoting thermal mixing at high velocity within the channel. Therefore, this configuration achieved higher cooling performance compared to the other cases studied in terms of the reduction in the maximum temperature and cooling uniformity in the silicon wafer.

Keywords: Synthetic jets, microchannel, electronic cooling, computational fluid dynamics.

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Authors: Kaige Shi, Chao Jiang, Xin Li

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The swirl gripper is an electrically activated noncontact handling device that uses swirling airflow to generate a lifting force. This force can be used to pick up a workpiece placed underneath the swirl gripper without any contact. It is applicable, for example, in the semiconductor wafer production line, where contact must be avoided during the handling and moving of a workpiece to minimize damage. When a workpiece levitates underneath a swirl gripper, the gap height between them is crucial for safe handling. Therefore, in this paper, we propose a method to estimate the levitation gap height by detecting pressure at two points. The method is based on theoretical model of the swirl gripper, and has been experimentally verified. Furthermore, the force between the gripper and the workpiece can also be estimated using the detected pressure. As a result, the nonlinear relationship between the force and gap height can be linearized by adjusting the rotating speed of the fan in the swirl gripper according to the estimated force and gap height. The linearized relationship is expected to enhance handling stability of the workpiece.

Keywords: Swirl gripper, noncontact handling, levitation, gap height estimation.

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Authors: Sae-Rom Pak, Seung Hwan Park, Jeong Ho Cho, Daewoong An, Cheong-Sool Park, Jun Seok Kim, Jun-Geol Baek

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It is important to predict yield in semiconductor test process in order to increase yield. In this study, yield prediction means finding out defective die, wafer or lot effectively. Semiconductor test process consists of some test steps and each test includes various test items. In other world, test data has a big and complicated characteristic. It also is disproportionably distributed as the number of data belonging to FAIL class is extremely low. For yield prediction, general data mining techniques have a limitation without any data preprocessing due to eigen properties of test data. Therefore, this study proposes an under-sampling method using support vector machine (SVM) to eliminate an imbalanced characteristic. For evaluating a performance, randomly under-sampling method is compared with the proposed method using actual semiconductor test data. As a result, sampling method using SVM is effective in generating robust model for yield prediction.

Keywords: Yield Prediction, Semiconductor Test Process, Support Vector Machine, Under Sampling

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Authors: Zainudin Kornain, Azman Jalar, Rozaidi Rasid, Fong Chee Seng

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Void formation in underfill is considered as failure in flip chip manufacturing process. Void formation possibly caused by several factors such as poor soldering and flux residue during die attach process, void entrapment due moisture contamination, dispense pattern process and setting up the curing process. This paper presents the comparison of single step and two steps curing profile towards the void and black dots formation in underfill for Hi-CTE Flip Chip Ceramic Ball Grid Array Package (FC-CBGA). Statistic analysis was conducted to analyze how different factors such as wafer lot, sawing technique, underfill fillet height and curing profile recipe were affected the formation of voids and black dots. A C-Mode Scanning Aqoustic Microscopy (C-SAM) was used to scan the total count of voids and black dots. It was shown that the 2 steps curing profile provided solution for void elimination and black dots in underfill after curing process.

Keywords: black dots formation, curing profile, FC-CBGA, underfill, void formation,

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Authors: Ziba Omidi, Min-Ki Kim

Abstract:

This research presents the design, fabrication and application of a flavor sensor for an integrated electronic tongue and electronic nose that can allow rapid characterization of multi-component mixtures in a solution. The odor gas and liquid are separated using hydrophobic porous membrane in micro fluidic channel. The sensor uses an array composed of microbeads in micromachined cavities localized on silicon wafer. Sensing occurs via colorimetric and fluorescence changes to receptors and indicator molecules that are attached to termination sites on the polymeric microbeads. As a result, the sensor array system enables simultaneous and near-real-time analyses using small samples and reagent volumes with the capacity to incorporate significant redundancies. One of the key parts of the system is a passive pump driven only by capillary force. The hydrophilic surface of the fluidic structure draws the sample into the sensor array without any moving mechanical parts. Since there is no moving mechanical component in the structure, the size of the fluidic structure can be compact and the fabrication becomes simple when compared to the device including active microfluidic components. These factors should make the proposed system inexpensive to mass-produce, portable and compatible with biomedical applications.

Keywords: Optical Sensor, Semiconductor manufacturing, Smell sensor, Taste sensor.

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Authors: A. A. Abaker Omer, H. B. Mohamed Balh, W. Liu, A. Abas, J. Yu, S. Li, W. Ma, W. El Kolaly, Y. Y. Ahmed Abuker

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We have discovered an important technical solution that could make new approaches in the processing of wet silicon etching, especially in the production of photovoltaic cells. During its inferior light-trapping and structural properties, the inverted pyramid structure outperforms the conventional pyramid textures and black silicone. The traditional pyramid textures and black silicon can only be accomplished with more advanced lithography, laser processing, etc. Importantly, our data demonstrate the feasibility of an inverted pyramidal structure of silicon via one-step Cu-catalyzed chemical etching (CCCE) in Cu (NO₃)₂/HF/H₂O₂/H₂O solutions. The effects of etching time and reaction temperature on surface geometry and light trapping were systematically investigated. The conclusion shows that the inverted pyramid structure has ultra-low reflectivity of ~4.2% in the wavelength of 300~1000 nm; introduce of Cu particles can significantly accelerate the dissolution of the silicon wafer. The etching and the inverted pyramid structure formation mechanism are discussed. Inverted pyramid structure with outstanding anti-reflectivity includes useful applications throughout the manufacture of semi-conductive industry-compatible solar cells, and can have significant impacts on industry colleagues and populations.

Keywords: Cu-catalyzed chemical etching, inverted pyramid nanostructured, reflection, solar cells.

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Authors: Matthias Kirmse, Uwe Petersohn, Elief Paffrath

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As in today's semiconductor industries test costs can make up to 50 percent of the total production costs, an efficient test error detection becomes more and more important. In this paper, we present a new machine learning approach to test error detection that should provide a faster recognition of test system faults as well as an improved test error recall. The key idea is to learn a classifier ensemble, detecting typical test error patterns in wafer test results immediately after finishing these tests. Since test error detection has not yet been discussed in the machine learning community, we define central problem-relevant terms and provide an analysis of important domain properties. Finally, we present comparative studies reflecting the failure detection performance of three individual classifiers and three ensemble methods based upon them. As base classifiers we chose a decision tree learner, a support vector machine and a Bayesian network, while the compared ensemble methods were simple and weighted majority vote as well as stacking. For the evaluation, we used cross validation and a specially designed practical simulation. By implementing our approach in a semiconductor test department for the observation of two products, we proofed its practical applicability.

Keywords: Ensemble methods, fault detection, machine learning, semiconductor test.

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Authors: Ching-Feng Chen, Ching-Chih Tsai

Abstract:

With the size of the transistor gradually approaching the physical limit, it challenges the persistence of Moore’s Law due to such issues of the short channel effect and the development of the high numerical aperture (NA) lithography equipment. In the context of the ever-increasing technical requirements of portable devices and high-performance computing (HPC), relying on the law continuation to enhance the chip density will no longer support the prospects of the electronics industry. Weighing the chip’s power consumption-performance-area-cost-cycle time to market (PPACC) is an updated benchmark to drive the evolution of the advanced wafer nanometer (nm). The advent of two and half- and three-dimensional (2.5 and 3D)- Very-Large-Scale Integration (VLSI) packaging based on Through Silicon Via (TSV) technology has updated the traditional die assembly methods and provided the solution. This overview investigates the up-to-date and cutting-edge packaging technologies for 2.5D and 3D integrated circuits (IC) based on the updated transistor structure and technology nodes. We conclude that multi-chip solutions for 2.5D and 3D IC packaging can prolong Moore’s Law.

Keywords: Moore’s Law, High Numerical Aperture, Power Consumption-Performance-Area-Cost-Cycle Time to Market, PPACC, 2.5 and 3D-Very-Large-Scale Integration Packaging, Through Silicon Vi.

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Authors: Tonislav Ivanov, Oleksii Nedashkivskyi, Denis Babeshko, Vadim Pinskiy, Matthew Putman

Abstract:

Training a machine learning model for object detection that generalizes well is known to benefit from a training dataset with diverse examples. However, training datasets usually contain many repeats of common examples of a class and lack rarely seen examples. This is due to the process commonly used during human annotation where a person would proceed sequentially through a list of images labeling a sufficiently high total number of examples. Instead, the method presented involves an active process where, after the initial labeling of several images is completed, the next subset of images for labeling is selected by an algorithm. This process of algorithmic image selection and manual labeling continues in an iterative fashion. The algorithm used for the image selection is a deep learning algorithm, based on the U-shaped architecture, which quantifies the presence of unseen data in each image in order to find images that contain the most novel examples. Moreover, the location of the unseen data in each image is highlighted, aiding the labeler in spotting these examples. Experiments performed using semiconductor wafer data show that labeling a subset of the data, curated by this algorithm, resulted in a model with a better performance than a model produced from sequentially labeling the same amount of data. Also, similar performance is achieved compared to a model trained on exhaustive labeling of the whole dataset. Overall, the proposed approach results in a dataset that has a diverse set of examples per class as well as more balanced classes, which proves beneficial when training a deep learning model.

Keywords: Computer vision, deep learning, object detection, semiconductor.

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