Search results for: CMOS gate modeling

Authors: Ankit Mitra

Abstract:

Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay, read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling improves the Read Noise Margin and static power dissipation is reduced by using Dual-V_t transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE using 90nm CMOS process.

Keywords: CMOS, Dual-Port, Data Retention Voltage, 8T SRAM, Leakage Current, Noise Margin, Loop-cutting, Single-ended.

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Authors: Mazhar B. Tayel, Amr H. Yassin

Abstract:

A proposed small-signal model parameters for a pseudomorphic high electron mobility transistor (PHEMT) is presented. Both extrinsic and intrinsic circuit elements of a smallsignal model are determined using genetic algorithm (GA) as a stochastic global search and optimization tool. The parameters extraction of the small-signal model is performed on 200-μm gate width AlGaAs/InGaAs PHEMT. The equivalent circuit elements for a proposed 18 elements model are determined directly from the measured S- parameters. The GA is used to extract the parameters of the proposed small-signal model from 0.5 up to 18 GHz.

Keywords: PHEMT, Genetic Algorithms, small signal modeling, optimization.

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Authors: Song Meng, Dianfu Ma, Yongwang Zhao, Jianxin Li

Abstract:

Cooperative visual modeling is more and more necessary in our complicated world. A collaborative environment which supports interactive operation and communication is required to increase work efficiency. We present a collaborative visual modeling framework which collaborative platform could be built on. On this platform, cooperation and communication is available for designers from different regions. This framework, which is different from other collaborative frameworks, contains a uniform message format, a message handling mechanism and other functions such as message pretreatment and Role-Communication-Token Access Control (RCTAC). We also show our implementation of this framework called Orchestra Designer, which support BPLE workflow modeling cooperatively online.

Keywords: colllaborative framework; visual modeling; message handling mechanism

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Authors: Zoltan Theisz, Gergely Mezei

Abstract:

Modern industrial automation relies on service oriented concepts of Internet of Things (IoT) device modeling in order to provide a flexible and extendable environment for service meta-repository. However, state-of-the-art meta-modeling techniques prefer design-time modeling, which results in a heavy usage of class sometimes unnecessary static subtyping. Although this approach benefits from clear-cut object-oriented design principles, it also seals the model repository for further dynamic extensions. In this paper, a dynamic multi-level modeling approach is introduced that enables dynamic subtyping through a more relaxed partial instantiation mechanism. The approach is demonstrated on a simple sensor network example.

Keywords: Meta-modeling, dynamic subtyping, DMLA, industrial automation, arrowhead.

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Authors: Hidetoshi Nonaka

Abstract:

This paper presents an interactive modeling system of uniform polyhedra using the isomorphic graphs. Especially, Kepler-Poinsot solids are formed by modifications of dodecahedron and icosahedron.

Keywords: Kepler-Poinsot solid, Shape modeling, Polyhedralgraph, Graph drawing.

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Authors: A. Retbi, M. Khalidi Idrissi, S. Bennani

Abstract:

The success of an e-learning system is highly dependent on the quality of its educational content and how effective, complete, and simple the design tool can be for teachers. Educational modeling languages (EMLs) are proposed as design languages intended to teachers for modeling diverse teaching-learning experiences, independently of the pedagogical approach and in different contexts. However, most existing EMLs are criticized for being too abstract and too complex to be understood and manipulated by teachers. In this paper, we present a visual EML that simplifies the process of designing learning scenarios for teachers with no programming background. Based on the conceptual framework of the activity theory, our resulting visual EML focuses on using Domainspecific modeling techniques to provide a pedagogical level of abstraction in the design process.

Keywords: Educational modeling language, Domain Specific Modeling, authoring systems, learning scenario.

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Authors: Bassam Atieh Rajabi, Sai Peck Lee

Abstract:

Business Process Modeling (BPM) is the first and most important step in business process management lifecycle. Graph based formalism and rule based formalism are the two most predominant formalisms on which process modeling languages are developed. BPM technology continues to face challenges in coping with dynamic business environments where requirements and goals are constantly changing at the execution time. Graph based formalisms incur problems to react to dynamic changes in Business Process (BP) at the runtime instances. In this research, an adaptive and flexible framework based on the integration between Object Oriented diagramming technique and Petri Net modeling language is proposed in order to support change management techniques for BPM and increase the representation capability for Object Oriented modeling for the dynamic changes in the runtime instances. The proposed framework is applied in a higher education environment to achieve flexible, updatable and dynamic BP.

Keywords: Business Process Modeling, Change Management, Graph Based Modeling, Rule Based Modeling, Object Oriented PetriNet.

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Authors: Kyong-min Lee, Moon Soo Chang, PooGyeon Park

Abstract:

In this paper, we propose a geometric modeling of illumination on the patterned image containing etching transistor. This image is captured by a commercial camera during the inspection of a TFT-LCD panel. Inspection of defect is an important process in the production of LCD panel, but the regional difference in brightness, which has a negative effect on the inspection, is due to the uneven illumination environment. In order to solve this problem, we present a geometric modeling of illumination consisting of an interpolation using the least squares method and 3D modeling using bezier surface. Our computational time, by using the sampling method, is shorter than the previous methods. Moreover, it can be further used to correct brightness in every patterned image.

Keywords: Bezier, defect, geometric modeling, illumination, inspection, LCD, panel.

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Authors: K. M. Tan, A. Anvar, T.F. Lu

Abstract:

A sophisticated simulator provides a cost-effective measure to carry out preliminary mission testing and diagnostic while reducing potential failures for real life at sea trials. The presented simulation framework covers three key areas: AUV modeling, sensor modeling, and environment modeling. AUV modeling mainly covers the area of AUV dynamics. Sensor modeling deals with physics and mathematical models that govern each sensor installed onto the AUV. Environment model incorporates the hydrostatic, hydrodynamics, and ocean currents that will affect the AUV in a real-time mission. Based on this designed simulation framework, custom scenarios provided by the user can be modeled and its corresponding behaviors can be observed. This paper focuses on the accuracy of the simulated data from AUV model and environmental model derived from a developed AUV test-bed which was jointly upgraded by DSTO and the University of Adelaide. The main contribution of this paper is to experimentally verify the accuracy of the proposed simulation framework.

Keywords: Autonomous Underwater Vehicle (AUV), simulator, framework, robotics, maritime robot, modeling.

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Authors: Cheng-Hsien Chang, Jyi-Tsong Lin, Po-Hsieh Lin, Hung-Pei Hsu, Chan-Hsiang Chang, Ming-Tsung Shih, Shih-Chuan Tseng, Min-Yan Lin

Abstract:

In this paper, we have proposed a novel FinFET with extended body under the poly gate, which is called EB-FinFET, and its characteristic is demonstrated by using three-dimensional (3-D) numerical simulation. We have analyzed and compared it with conventional FinFET. The extended body height dependence on the drain induced barrier lowering (DIBL) and subthreshold swing (S.S) have been also investigated. According to the 3-D numerical simulation, the proposed structure has a firm structure, an acceptable short channel effect (SCE), a reduced series resistance, an increased on state drain current (I on) and a large normalized I DS. Furthermore, the structure can also improve corner effect and reduce self-heating effect due to the extended body. Our results show that the EBFinFET is excellent for nanoscale device.

Keywords: SOI, FinFET, tri-gate, self-heating effect.

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Authors: K. E. Kaharudin, A. H. Hamidon, F. Salehuddin

Abstract:

Vertical Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is believed to suppress various short channel effect problems. The gate to channel coupling in vertical DG-MOSFET are doubled, thus resulting in higher current density. By having two gates, both gates are able to control the channel from both sides and possess better electrostatic control over the channel. In order to ensure that the transistor possess a superb turn-off characteristic, the subs-threshold swing (SS) must be kept at minimum value (60-90mV/dec). By utilizing SILVACO TCAD software, an n-channel vertical DG-MOSFET was successfully designed while keeping the sub-threshold swing (SS) value as minimum as possible. From the observation made, the value of sub-threshold swing (SS) was able to be varied by adjusting the height of the silicon pillar. The minimum value of sub-threshold swing (SS) was found to be 64.7mV/dec with threshold voltage (V_TH) of 0.895V. The ideal height of the vertical DG-MOSFET pillar was found to be at 0.265 µm.

Keywords: DG-MOSFET, pillar, SCE, vertical

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Authors: Jianping Hu, Xiaolei Sheng

Abstract:

This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz.

Keywords: Low power, Register file, Complementarypass-transistor logic, Adiabatic logic, Single-phase power clock.

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Authors: Aouattou Nabila, Saighi Mohamed, Fekih Malika

Abstract:

The modeling of water transfer in the unsaturated zone uses techniques and methods of the soil physics to solve the Richards-s equation. However, there is a disaccord between the size of the measurements provided by the soil physics and the size of the fields of hydrological modeling problem, to which is added the strong spatial variability of soil hydraulic properties. The objective of this work was to develop a methodology to estimate the hydrodynamic parameters for modeling water transfers at different hydrological scales in the soil-plant atmosphere systems.

Keywords: Hydraulic properties, Modeling, Unsaturated zone, Transfer, Water

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Authors: Jacek Kuraś, Jacek Lembas, Marek Skomorowski

Abstract:

In this paper, we introduce GODYS-PC software package for modeling, simulating and analyzing dynamic systems. To illustrate the use of GODYS-PC we present a few examples which concern modeling and simulating of engineering systems. In order to compare GODYS-PC with widely used in academia and industry Simulink®, the same examples are provided both in GODYS-PC and Simulink®.

Keywords: Modeling, simulating and analyzing dynamicsystems.

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Authors: Himanshu Payal, Sachin Maheshwari, Pushpendra S. Bharti

Abstract:

Electrical discharge machining (EDM), a non-conventional machining process, finds wide applications for shaping difficult-to-cut alloys. Process modeling of EDM is required to exploit the process to the fullest. Process modeling of EDM is a challenging task owing to involvement of so many electrical and non-electrical parameters. This work is an attempt to model the EDM process using artificial neural network (ANN). Experiments were carried out on die-sinking EDM taking Inconel 825 as work material. ANN modeling has been performed using experimental data. The prediction ability of trained network has been verified experimentally. Results indicate that ANN can predict the values of performance measures of EDM satisfactorily.

Keywords: Artificial neural network, EDM, metal removal rate, modeling, surface roughness.

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Authors: Hung-Pei Hsu, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Ming-Tsung Shih, Chan-Hsiang Chang, Shih-Chuan Tseng, Min-Yan Lin, Shih-Wen Hsu

Abstract:

In this paper, we propose a novel metal oxide semiconductor field effect transistor with L-shaped channel structure (LMOS), and several type of L-shaped structures are also designed, studied and compared with the conventional MOSFET device for the same average gate length (Lavg). The proposed device electrical characteristics are analyzed and evaluated by three dimension (3-D) ISE-TCAD simulator. It can be confirmed that the LMOS devices have higher on-state drain current and both lower drain-induced barrier lowering (DIBL) and subthreshold swing (S.S.) than its conventional counterpart has. In addition, the transconductance and voltage gain properties of the LMOS are also improved.

Keywords: Average gate length (Lavg), drain-induced barrier lowering (DIBL), L-shaped channel MOSFET (LMOS), subthreshold swing (S.S.).

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Authors: Wei Zhang

Abstract:

With the rapid development of deep learning, neural network and deep learning algorithms play a significant role in various practical applications. Due to the high accuracy and good performance, Convolutional Neural Networks (CNNs) especially have become a research hot spot in the past few years. However, the size of the networks becomes increasingly large scale due to the demands of the practical applications, which poses a significant challenge to construct a high-performance implementation of deep learning neural networks. Meanwhile, many of these application scenarios also have strict requirements on the performance and low-power consumption of hardware devices. Therefore, it is particularly critical to choose a moderate computing platform for hardware acceleration of CNNs. This article aimed to survey the recent advance in Field Programmable Gate Array (FPGA)-based acceleration of CNNs. Various designs and implementations of the accelerator based on FPGA under different devices and network models are overviewed, and the versions of Graphic Processing Units (GPUs), Application Specific Integrated Circuits (ASICs) and Digital Signal Processors (DSPs) are compared to present our own critical analysis and comments. Finally, we give a discussion on different perspectives of these acceleration and optimization methods on FPGA platforms to further explore the opportunities and challenges for future research. More helpfully, we give a prospect for future development of the FPGA-based accelerator.

Keywords: Deep learning, field programmable gate array, FPGA, hardware acceleration, convolutional neural networks, CNN.

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Authors: Haridas Kuruveettil, Dongning Zhao, Cheong Jia Hao, Minkyu Je

Abstract:

We present the design of Analog front end (AFE) low noise pre-amplifier implemented in a high voltage 0.18-µm CMOS technology for  a three dimensional ultrasound  bio microscope (3D UBM) application. The fabricated chip has 4X16 pre-amplifiers implemented to interface   a 2-D array of    high frequency capacitive micro-machined ultrasound transducers (CMUT). Core AFE cell consists of a high-voltage pulser in the transmit path, and a low-noise transimpedance amplifier in the receive path. Proposed system offers a high image resolution by the use of high frequency CMUTs with associated high performance imaging electronics integrated together.  Performance requirements and the design methods of the high bandwidth transimpedance amplifier are described in the paper. A single cell of transimpedance (TIA) amplifier and the bias circuit occupies a silicon area of 250X380 µm² and the full chip occupies a total silicon area of 10x6.8 mm².

Keywords: Ultrasound, analog front end, medical imaging, beam forming, biomicroscope, transimpedance gain.

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand Tan Kong Yew

Abstract:

This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), and ion sensor electronics.

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand, Tan Kong Yew

Abstract:

This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 Rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics.

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Authors: Ahmad Habibizad Navin, Mehdi Naghian Fesharaki, Mirkamal Mirnia, Mohamad Teshnelab, Ehsan Shahamatnia

Abstract:

In this paper we introduce new data oriented modeling of uniform random variable well-matched with computing systems. Due to this conformity with current computers structure, this modeling will be efficiently used in statistical inference.

Keywords: Uniform random variable, Data oriented modeling, Statistical inference, Prodigraph, Statistically complete tree, Uniformdigital probability digraph, Uniform n-complete probability tree.

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Authors: Radek Němec

Abstract:

Today's business environment requires that companies have access to highly relevant information in a matter of seconds. Modern Business Intelligence tools rely on data structured mostly in traditional dimensional database schemas, typically represented by star schemas. Dimensional modeling is already recognized as a leading industry standard in the field of data warehousing although several drawbacks and pitfalls were reported. This paper focuses on the analysis of another data warehouse modeling technique - the anchor modeling, and its characteristics in context with the standardized dimensional modeling technique from a query performance perspective. The results of the analysis show information about performance of queries executed on database schemas structured according to principles of each database modeling technique.

Keywords: Data warehousing, anchor modeling, star schema, anchor schema, query performance.

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Authors: T. Vigneswaran, B. Mukundhan, P. Subbarami Reddy

Abstract:

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal.Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.

Keywords: Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI).

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Authors: Kwa-Sur Tam

Abstract:

This paper reviews various approaches that have been used for the modeling and simulation of large-scale engineering systems and determines their appropriateness in the development of a RICS modeling and simulation tool. Bond graphs, linear graphs, block diagrams, differential and difference equations, modeling languages, cellular automata and agents are reviewed. This tool should be based on linear graph representation and supports symbolic programming, functional programming, the development of noncausal models and the incorporation of decentralized approaches.

Keywords: Interdisciplinary, dynamic, functional programming, object-oriented.

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Authors: C. Kalamani, V. Abishek Karthick, S. Anitha, K. Kavin Kumar

Abstract:

The fault tolerant system plays a crucial role in the critical applications which are being used in the present scenario. A fault may change the functionality of circuits. Aim of this paper is to design multiplier using fault tolerant hybrid full adder. Fault tolerant hybrid full adder is designed to check and repair any fault in the circuit using self-checking circuit and the self-repairing circuit. Further, the use of conventional logic circuits may result in more area, delay as well as power consumption. In order to reduce these parameters of the circuit, GDI (Gate Diffusion Input) techniques with less number of transistors are used compared to conventional full adder circuit. This reduces the area, delay and power consumption. The proposed method solves the major problems occurring in the most crucial and critical applications.

Keywords: Gate diffusion input, hybrid full adder, self-checking, fault tolerant.

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Authors: Raman Paranjape

Abstract:

We present a new approach to evaluation of Cyber Security in Power Systems using the method of modeling the power systems Infrastructure using software agents. Interfaces between module and the home smart meter are recognized as the primary points of intrusion.

Keywords: Power Systems, Modeling and Simulation, Agent systems.

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Authors: Jihye Jeon

Abstract:

This paper analyzes the conceptual framework of three statistical methods, multiple regression, path analysis, and structural equation models. When establishing research model of the statistical modeling of complex social phenomenon, it is important to know the strengths and limitations of three statistical models. This study explored the character, strength, and limitation of each modeling and suggested some strategies for accurate explaining or predicting the causal relationships among variables. Especially, on the studying of depression or mental health, the common mistakes of research modeling were discussed.

Keywords: Multiple regression, path analysis, structural equation models, statistical modeling, social and psychological phenomenon.

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Authors: Shilpi Lavania

Abstract:

As the frequency of operation has attained a range of GHz and signal rise time continues to increase interconnect technology is suffering due to various high frequency effects as well as ground bounce problem. In some recent studies a high frequency effect i.e. skin effect has been modeled and its drawbacks have been discussed. This paper strives to make an impression on the advantage side of modeling skin effect for interconnect line. The proposed method has considered a CMOS with RC interconnect. Delay and noise considering ground bounce problem and with skin effect are discussed. The simulation results reveal an advantage of considering skin effect for minimization of ground bounce problem during the working of the model. Noise and delay variations with temperature are also presented.

Keywords: Interconnect, Skin effect, Ground Bounce, Delay, Noise.

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Authors: Ala'eddin A. Saif , Z. A. Z. Jamal, Z. Sauli, P. Poopalan

Abstract:

The ferroelectric behavior of barium strontium titanate (BST) in thin film form has been investigated in order to study the possibility of using BST for ferroelectric gate-field effect transistor (FeFET) for memory devices application. BST thin films have been fabricated as Al/BST/Pt/SiO2/Si-gate configuration. The variation of the dielectric constant (ε) and tan δ with frequency have been studied to ensure the dielectric quality of the material. The results show that at low frequencies, ε increases as the Ba content increases, whereas at high frequencies, it shows the opposite variation, which is attributed to the dipole dynamics. tan δ shows low values with a peak at the mid-frequency range. The ferroelectric behavior of the Al/BST/Pt/SiO2/Si has been investigated using C-V characteristics. The results show that the strength of the ferroelectric hysteresis loop increases as the Ba content increases; this is attributed to the grain size and dipole dynamics effect.

Keywords: BST thin film, Electrical properties, Ferroelectrichysteresis, Ferroelectric FET.

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Authors: David M. Lucas, Charles W. Jarrett

Abstract:

In the culture of Thailand, the Yak serve as a mediated icon representing strength, power, and mystical protection not only for the Buddha, but for population of worshipers. Originating from the forests of China, the Yak continues to stand guard at the gates of Buddhist temples. The Yak represents Thai culture in the hearts of Thai people. This paper presents a qualitative study regarding the curious mix of media, culture, and religion that projects the Yak of Thailand as a larger than life message throughout the political, cultural, and religious spheres. The gate guardians, or gods as they are sometimes called, appear throughout the religious temples of Asian cultures. However, the Asian cultures demonstrate differences in artistic renditions (or presentations) of such sentinels. Thailand gate guards (the Yak) stand in front of many Buddhist temples, and these iconic figures display unique features with varied symbolic significance. The temple (or wat), plays a vital role in every community; and, for many people, Thailand’s temples are the country’s most endearing sights. The authors applied folknography as a methodology to illustrate the importance of the Thai Yak in serving as meaningful icons that transcend not only time, but the culture, religion, and mass media. The Yak represents mythical, religious, artistic, cultural, and militaristic significance for the Thai people. Data collection included interviews, focus groups, and natural observations. This paper summarizes the perceptions of the Thai people concerning their gate sentries and the relationship, communication, connection, and the enduring respect that Thai people hold for their guardians of the gates.

Keywords: Communication, Culture, Folknography, Icon, Image, Media, Protection, Religion, Yak.

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