Search results for: single-chip circuit

Authors: Ki-Jin Kim, Sanghoon Park, K. H. Ahn

Abstract:

A way of generating millimeter wave I/Q signal using inductive resonator matched poly-phase filter is suggested. Normally the poly-phase filter generates quite accurate I/Q phase and magnitude but the loss of the filter is considerable due to series connection of passive RC components. This loss term directly increases system noise figure when the poly-phase filter is used in RF Front-end. The proposed matching method eliminates above mentioned loss and in addition provides gain on the passive filter. The working algorithm is illustrated by mathematical analysis. The generated I/Q signal is used in implementing millimeter wave phase shifter for the 60 GHz communication system to verify its effectiveness. The circuit is fabricated in 90 nm TSMC RF CMOS process under 1.2 V supply voltage. The measurement results showed that the suggested method improved gain by 6.5 dB and noise by 2.3 dB. The summary of the proposed I/Q generation is compared with previous works.

Keywords: Millimeter Wave Circuits, Local Distribution, I/Q Generator.

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Authors: Yusmeeraz Yusof, Yoshiyuki Yanagimoto, Shigeyasu Uno, Kazuo Nakazato

Abstract:

We demonstrate a nonfaradaic electrochemical impedance spectroscopy measurement of biochemically modified gold plated electrodes using a two-electrode system. The absence of any redox indicator in the impedance measurements provide more precise and accurate characterization of the measured bioanalyte at molecular resolution. An equivalent electrical circuit of the electrodeelectrolyte interface was deduced from the observed impedance data of saline solution at low and high concentrations. The detection of biomolecular interactions was fundamentally correlated to electrical double-layer variation at modified interface. The investigations were done using 20mer deoxyribonucleic acid (DNA) strands without any label. Surface modification was performed by creating mixed monolayer of the thiol-modified single-stranded DNA and a spacer thiol (mercaptohexanol) by a two-step self-assembly method. The results clearly distinguish between the noncomplementary and complementary hybridization of DNA, at low frequency region below several hundreds Hertz.

Keywords: Biosensor, electrical double-layer, impedance spectroscopy, label free DNA.

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Authors: Miroslav Popelka, Jakub Nožička

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In this paper we deal with using Lego Mindstorms in simulation of robotic systems with respect to cost reduction. Lego Mindstorms kit contains broad variety of hardware components which are required to simulate, program and test the robotics systems in practice. Algorithm programming went in development environment supplied together with Lego kit as in programming language C# as well. Algorithm following the line, which we dealt with in this paper, uses theoretical findings from area of controlling circuits. PID controller has been chosen as controlling circuit whose individual components were experimentally adjusted for optimal motion of robot tracking the line. Data which are determined to process by algorithm are collected by sensors which scan the interface between black and white surfaces followed by robot. Based on discovered facts Lego Mindstorms can be considered for low-cost and capable kit to simulate real robotics systems.

Keywords: LEGO Mindstorms, PID controller, low-cost robotics systems, line follower, sensors, programming language C#, EV3 Home Edition Software.

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Authors: K. Diwakar, K. Aanandha Saravanan, C. Senthilpari

Abstract:

Higher order ΔΣ Modulator (DSM) is basically an unstable system. The approximate conditions for stability cannot be used for the design of a DSM for industrial applications where risk is involved. The existing second order, single stage, single bit, unity feedback gain , discrete DSM cannot be used for the normalized full range (-1 to +1) of an input signal since the DSM becomes unstable when the input signal is above ±0.55. The stability is also not guaranteed for input signals of amplitude less than ±0.55. In the present paper, the above mentioned second order DSM is modified with input signal dependent forward path gain. The proposed DSM is suitable for industrial applications where one needs the digital representation of the analog input signal, during each sampling period. The proposed DSM can operate almost for the full range of input signals (-0.95 to +0.95) without causing instability, assuming that the second integrator output should not exceed the circuit supply voltage, ±15 Volts.

Keywords: DSM, stability, SNR, state variables.

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Authors: Labar Hocine, Dgeghader Yacine, Kelaiaia Mounia Samira, Bounaya Kamel

Abstract:

To maximise furnace production it-s necessary to optimise furnace control, with the objectives of achieving maximum power input into the melting process, minimum network distortion and power-off time, without compromise on quality and safety. This can be achieved with on the one hand by an appropriate electrode control and on the other hand by a minimum of AC transformer switching. Electrical arc is a stochastic process; witch is the principal cause of power quality problems, including voltages dips, harmonic distortion, unbalance loads and flicker. So it is difficult to make an appropriate model for an Electrical Arc Furnace (EAF). The factors that effect EAF operation are the melting or refining materials, melting stage, electrode position (arc length), electrode arm control and short circuit power of the feeder. So arc voltages, current and power are defined as a nonlinear function of the arc length. In this article we propose our own empirical function of the EAF and model, for the mean stages of the melting process, thanks to the measurements in the steel factory.

Keywords: Modelling, electrical arc, melting, power, EAF, steel.

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Authors: P. Selvam, S. Senthil Kumar

Abstract:

Maximum Power Point Tracking (MPPT) has played a vital role to enhance the efficiency of solar photovoltaic (PV) power generation under varying atmospheric temperature and solar irradiation. However, it is hard to track the maximum power point using conventional linear controllers due to the natural inheritance of nonlinear I-V and P-V characteristics of solar PV systems. Fuzzy Logic Controller (FLC) is suitable for nonlinear system control applications and eliminating oscillations, circuit complexities present in the conventional perturb and observation and incremental conductance methods respectively. Hence, in this paper, FLC is proposed for tracking exact MPPT of solar PV power generation system under varying solar irradiation conditions. The effectiveness of the proposed FLC-based MPPT controller is validated through simulation and analysis using MATLAB/Simulink.

Keywords: Fuzzy logic controller, maximum power point tracking, photovoltaic.

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Authors: Khalil Monfaredi, Hassan Faraji Baghtash, Majid Abbasi

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In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple current mirror with input and output voltage requirements less than that of a simple current mirror is presented. These features are achieved with very simple structure avoiding extra large node impedances to ensure high bandwidth operation. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Such outstanding features of this current mirror as high output impedance ~384K, low input impedance~6.4, wide bandwidth~178MHz, low input voltage ~ 362mV, low output voltage ~ 38mV and low current transfer error ~4% (all at 50μA) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35μm CMOS technology with HSPICE are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror.

Keywords: Analog circuits, Current mirror, high frequency, Low power, Low voltage.

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Authors: Zdena Lahodová, Michal Koleška, Ladislav Viererbl

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This article summarizes ways to verify neutron fluence for neutron transmutation doping of silicon with phosphorus on the LVR-15 reactor. Neutron fluence is determined using activation detectors placed along the crystal in a strip or encapsulated in a rod holder. Holders are placed at the centre of a water-filled capsule or in an aluminum or silicon ingot that simulates a real single crystal. If the diameter of the crystal is significantly less than the capsule diameter and water from the primary circuit enters the free space in the capsule, neutron interaction in the water changes neutron fluence, affecting axial irradiation homogeneity. The effect of moving the capsule vertically in the channel relative to maximum neutron fluence in the reactor core was also measured. Even a small shift of the capsule-s centre causes great irradiation inhomogeneity. This effect was measured using activation detectors, and was also confirmed by MCNP calculation.

Keywords: Irradiation homogeneity, neutron fluence, neutron transmutation doping, rotational channel.

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Authors: K. Ramash Kumar, S. Jeevananthan

Abstract:

The object of this paper is to design and analyze a proportional – integral (PI) control for positive output elementary super lift Luo converter (POESLLC), which is the start-of-the-art DC-DC converter. The positive output elementary super lift Luo converter performs the voltage conversion from positive source voltage to positive load voltage. This paper proposes a development of PI control capable of providing the good static and dynamic performance compared to proportional – integralderivative (PID) controller. Using state space average method derives the dynamic equations describing the positive output elementary super lift luo converter and PI control is designed. The simulation model of the positive output elementary super lift Luo converter with its control circuit is implemented in Matlab/Simulink. The PI control for positive output elementary super lift Luo converter is tested for transient region, line changes, load changes, steady state region and also for components variations.

Keywords: DC-DC converter, Positive output elementarysuper lift Luo converter (POESLLC), Proportional – Integral (PI)control.

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Authors: Wenji Zhu, Yigang He

Abstract:

This paper presents a new method of analog fault diagnosis based on back-propagation neural networks (BPNNs) using wavelet decomposition and fractal dimension as preprocessors. The proposed method has the capability to detect and identify faulty components in an analog electronic circuit with tolerance by analyzing its impulse response. Using wavelet decomposition to preprocess the impulse response drastically de-noises the inputs to the neural network. The second preprocessing by fractal dimension can extract unique features, which are the fed to a neural network as inputs for further classification. A comparison of our work with [1] and [6], which also employs back-propagation (BP) neural networks, reveals that our system requires a much smaller network and performs significantly better in fault diagnosis of analog circuits due to our proposed preprocessing techniques.

Keywords: Analog circuits, fault diagnosis, tolerance, wavelettransform, fractal dimension, box dimension.

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Authors: Wook-Won Kim, Sung-Yul Kim, Jin-O Kim

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The fault current levels through the electric devices have a significant impact on failure probability. New fault current results in exceeding the rated capacity of circuit breaker and switching equipments and changes operation characteristic of overcurrent relay. In order to solve these problems, SFCL (Superconducting Fault Current Limiter) has rising as one of new alternatives so as to improve these problems. A fault current reduction differs depending on installed location. Therefore, a location of SFCL is very important. Also, SFCL decreases the fault current, and it prevents surrounding protective devices to be exposed to fault current, it then will bring a change of reliability. In this paper, we propose method which determines the optimal location when SFCL is installed in power system. In addition, the reliability about the power system which SFCL was installed is evaluated. The efficiency and effectiveness of this method are also shown by numerical examples and the reliability indices are evaluated in this study at each load points. These results show a reliability change of a system when SFCL was installed.

Keywords: Superconducting Fault Current Limiter, OptimalLocation, Reliability

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Authors: Muhammad H. Rais,

Abstract:

Truncated multiplier is a good candidate for digital signal processing (DSP) applications including finite impulse response (FIR) and discrete cosine transform (DCT). Through truncated multiplier a significant reduction in Field Programmable Gate Array (FPGA) resources can be achieved. This paper presents for the first time a comparison of resource utilization of Spartan-3AN and Virtex-5 implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The Virtex-5 FPGA shows significant improvement as compared to Spartan-3AN FPGA device. The Virtex-5 FPGA device shows better performance with a percentage ratio of number of occupied slices for standard to truncated multipliers is increased from 40% to 73.86% as compared to Spartan- 3AN is decreased from 68.75% to 58.78%. Results show that the anomaly in Spartan-3AN FPGA device average connection and maximum pin delay have been efficiently reduced in Virtex-5 FPGA device.

Keywords: Digital Signal Processing (DSP), FieldProgrammable Gate Array (FPGA), Spartan-3AN, TruncatedMultiplier, Virtex-5, VHDL.

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Authors: Guo-Ming Sung, Naga Raju Naik R.

Abstract:

Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.

Keywords: high-speed, low-power, flip-flop, sense-amplifier

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Authors: Wisuwat Plodpradista

Abstract:

Tubular linear induction motor (TLIM) can be used as a capsule pump in a large pneumatic capsule pipeline (PCP) system. Parametric performance evaluation of the designed 1-meter diameter PCP-TLIM system yields encouraging results for practical implementation. The capsule thrust and speed inside the TLIM pump can be calculated from the combination of the PCP fluid mechanics and the TLIM equations. The TLIM equivalent circuits derived from those of the conventional three-phase induction motor are used as a model to predict the static test results of a small-scale PCP-TLIM system. In this paper, additional dynamic tests are performed on the same small-scale PCP-TLIM system with two capsules of different diameters. The behaviors of the capsule inside the pump are observed and analyzed. The dynamic performances from the dynamic tests are compared with the theoretical predictions based on the TLIM equivalent circuit model.

Keywords: Pneumatic capsule pipeline, Tubular linear induction motor

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Authors: M. Sedighizadeh, A. Rezazadeh

Abstract:

In this paper presents a technique for developing the computational efficiency in simulating double output induction generators (DOIG) with two rotor circuits where stator transients are to be included. Iterative decomposition is used to separate the flux– Linkage equations into decoupled fast and slow subsystems, after which the model order of the fast subsystems is reduced by neglecting the heavily damped fast transients caused by the second rotor circuit using integral manifolds theory. The two decoupled subsystems along with the equation for the very slowly changing slip constitute a three time-scale model for the machine which resulted in increasing computational speed. Finally, the proposed method of reduced order in this paper is compared with the other conventional methods in linear and nonlinear modes and it is shown that this method is better than the other methods regarding simulation accuracy and speed.

Keywords: DOIG, Iterative separation, Integral manifolds, Reduced order.

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Authors: Rahim Sotoudeh Bahreini, Alireza Foroughi Nematollahi, Akbar Jafari

Abstract:

This study investigates the mechanism of a Gyratory crusher-located in Golgohar mining and industrial Co. specifically with a focus on stresses distribution and fatigue failure of its main shaft. At first step, the cross section of the fractured shaft is studied, and the crack growth is analyzed. Then, the rotational motion of the shaft and the oil temperature of oil circuit of equipment are monitored. Condition monitoring is used to help finding a better modification. Based on the results of this study, the main causes of shaft failure are identified, and corrective solution is offered to increase crusher performance, especially its main shaft life. To predict the efficiency of the proposed modification, finite element simulation is performed, and its results are compared with the similar modified cases. The comparison and interpretation of simulation results confirm the efficiency of proposed corrective method.

Keywords: Fatigue failure, finite element method, gyratory crusher, condition monitoring.

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Authors: Ionel Zagan, Vasile Gheorghita Gaitan

Abstract:

The development of CPUs and of real-time systems based on them made it possible to use time at increasingly low resolutions. Together with the scheduling methods and algorithms, time organizing has been improved so as to respond positively to the need for optimization and to the way in which the CPU is used. This presentation contains both a detailed theoretical description and the results obtained from research on improving the performances of the nMPRA (Multi Pipeline Register Architecture) processor by implementing specific functions in hardware. The proposed CPU architecture has been developed, simulated and validated by using the FPGA Virtex-7 circuit, via a SoC project. Although the nMPRA processor hardware structure with five pipeline stages is very complex, the present paper presents and analyzes the tests dedicated to the implementation of the CPU and of the memory on-chip for instructions and data. In order to practically implement and test the entire SoC project, various tests have been performed. These tests have been performed in order to verify the drivers for peripherals and the boot module named Bootloader.

Keywords: Hardware scheduler, nMPRA processor, real-time systems, scheduling methods.

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Authors: M. Fadlallah, G. Ghibaudo, C. G. Theodorou

Abstract:

The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.

Keywords: Low-frequency noise, Random Telegraph Noise, Dynamic Variation, SRRV.

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Authors: Mohamed Zellagui, Abdelaziz Chaghi

Abstract:

This paper presents the impact study of apparent reactance injected by series Flexible AC Transmission System (FACTS) i.e. Thyristor Controlled Series Reactor (TCSR) on the measured impedance of a 400 kV single electrical transmission line in the presence of phase to earth fault with fault resistance. The study deals with an electrical transmission line of Eastern Algerian transmission networks at Group Sonelgaz (Algerian Company of Electrical and Gas) compensated by TCSR connected at midpoint of the line. This compensator used to inject active and reactive powers is controlled by three TCSR-s. The simulations results investigate the impacts of the TCSR on the parameters of short circuit calculation and parameters of measured impedance by distance relay in the presence of earth fault for three cases study.

Keywords: TCSR, Transmission line, Apparent reactance, Earth fault, Symmetrical components, Distance protection, Measured impedance.

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Authors: Jun Sung Go, Jong Kang Park, Jong Tae Kim

Abstract:

As semi-conductor manufacturing technology evolves; the single event transient problem becomes more significant issue. Single event transient has a critical impact on both combinational and sequential logic circuits, so it is important to evaluate the soft error tolerance of the circuits at the design stage. In this paper, we present a soft error detecting simulation using scan chain. The simulation model generates a single event transient randomly in the circuit, and detects the soft error during the execution of the test patterns. We verified this model by inserting a scan chain in an 8051 microprocessor using 65 nm CMOS technology. While the test patterns generated by ATPG program are passing through the scan chain, we insert a single event transient and detect the number of soft errors per sub-module. The experiments show that the soft error rates per cell area of the SFR module is 277% larger than other modules.

Keywords: Scan chain, single event transient, soft error, 8051 processor.

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Authors: Kemal Tutuncu, Recai Ozcan

Abstract:

Having done in this study, air-conditioning automation for patisserie shopwindow was designed. In the cooling sector it is quite important to cooling up the air temperature in the shopwindow within short time interval. Otherwise the patisseries inside of the shopwindow will be spoilt in a few days. Additionally the humidity is other important parameter for the patisseries kept in shopwindow. It must be raised up to desired level in a quite short time. Traditional patisserie shopwindows only allow controlling temperature manually. There is no humidity control and humidity is supplied by fans that are directed to the water at the bottom of the shopwindows. In this study, humidity and temperature sensors (SHT11), PIC, AC motor controller, DC motor controller, ultrasonic nebulizer and other electronic circuit members were used to simulate air conditioning automation for patisserie shopwindow in proteus software package. The simulation results showed that temperature and humidity values are adjusted in desired time duration by openloop control technique. Outer and inner temperature and humidity values were used for control mechanism.

Keywords: Air conditioning automation, temperature and humidity, SHT11, AC motor controller, open-loop control.

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Authors: P. V. V. Rama Rao, B. Kali Prasanna, Y. T. R. Palleswari

Abstract:

Renewable energy is derived from natural processes that are replenished constantly. Included in the definition is electricity and heat generated from solar, wind, ocean, hydropower, biomass, geothermal resources, and bio-fuels and hydrogen derived from renewable resources. Each of these sources has unique characteristics which influence how and where they are used. This paper presents the modeling the simulation of solar and hydro hybrid energy sources in MATLAB/SIMULINK environment. It simulates all quantities of Hybrid Electrical Power system (HEPS) such as AC output current of the inverter that injected to the load/grid, load current, grid current. It also simulates power output from PV and Hydraulic Turbine Generator (HTG), power delivered to or from grid and finally power factor of the inverter for PV, HTG and grid. The proposed circuit uses instantaneous p-q (real-imaginary) power theory.

Keywords: Photovoltaic Array, Hydraulic Turbine Generator, Electrical Utility (EU), Hybrid Electrical Power Supply.

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Authors: Malik I. Al-Amayreh, Mohammad I. Kilani, Ahmed S. Al-Salaymeh

Abstract:

This work presents a Computational Fluid Dynamics (CFD) simulation of a butterfly valve used to control the flow of combustible gas mixture in an industrial process setting.The work uses CFD simulation to analyze the flow characteristics in the vicinity of the valve, including the pressure distributions and Frequency spectrum of the pressure pulsations downstream the valves and the vortex shedding allow predicting the torque fluctuations acting on the valve shaft and the possibility of generating mechanical vibration and resonance.These fluctuations are due to aerodynamic torque resulting from fluid turbulence and vortex shedding in the valve vicinity. The valve analyzed is located in a pipeline between two opposing 90o elbows, which exposes the valve and the surrounding structure to the turbulence generated upstream and downstream the elbows at either end of the pipe.CFD simulations show that the best location for the valve from a vibration point of view is in the middle of the pipe joining the elbows.

Keywords: Butterfly Valve Vibration Analysis, Computational Fluid Dynamics, Fluid Flow Circuit Design, Fluid Mechanics.

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Authors: Ionel Zagan, Vasile Gheorghita Gaitan

Abstract:

Minimizing the response time to asynchronous events in a real-time system is an important factor in increasing the speed of response and an interesting concept in designing equipment fast enough for the most demanding applications. The present article will present the results regarding the validation of the nMPRA (Multi Pipeline Register Architecture) architecture using the FPGA Virtex-7 circuit. The nMPRA concept is a hardware processor with the scheduler implemented at the processor level; this is done without affecting a possible bus communication, as is the case with the other CPU solutions. The implementation of static or dynamic scheduling operations in hardware and the improvement of handling interrupts and events by the real-time executive described in the present article represent a key solution for eliminating the overhead of the operating system functions. The nMPRA processor is capable of executing a preemptive scheduling, using various algorithms without a software scheduler. Therefore, we have also presented various scheduling methods and algorithms used in scheduling the real-time tasks.

Keywords: nMPRA architecture, pipeline processor, preemptive scheduling, real-time system.

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Authors: Ji-Hye Kim, Sung-Gaun Kim

Abstract:

Electro-hydraulic power steering (EHPS) system for the fuel rate reduction and steering feel improvement is comprised of ECU including the logic which controls the steering system and BL DC motor and produces the best suited cornering force, BLDC motor, high pressure pump integrated module and basic oil-hydraulic circuit of the commercial HPS system. Electro-hydraulic system can be studied in two ways such as experimental and computer simulation. To get accurate results in experimental study of EHPS system, the real boundary management is necessary which is difficult task. And the accuracy of the experimental results depends on the preparation of the experimental setup and accuracy of the data collection. The computer simulation gives accurate and reliable results if the simulation is carried out considering proper boundary conditions. So, in this paper, each component of EHPS was modeled, and the model-based analysis and control logic was designed by using AMESim

Keywords: Power steering system, Electro-Hydraulic power steering (EHPS) system, Modeling of EHPS system, Analysis modeling.

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Authors: Nur Syarafina Binti Othman, Tsubasa Jindo, Makato Yamada, Miho Tsuyama, Hitoshi Nakano

Abstract:

A novel method to produce a fast high voltage solid states switch using Insulated Gate Bipolar Transistors (IGBTs) is presented for discharge-pumped gas lasers. The IGBTs are connected in series to achieve a high voltage rating. An avalanche transistor is used as the gate driver. The fast pulse generated by the avalanche transistor quickly charges the large input capacitance of the IGBT, resulting in a switch out of a fast high-voltage pulse. The switching characteristic of fast-high voltage solid state switch has been estimated in the multi-stage series-connected IGBT with the applied voltage of several tens of kV. Electrical circuit diagram and the mythology of fast-high voltage solid state switch as well as experimental results obtained are presented.

Keywords: High voltage, IGBT, Solid states switch.

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Authors: Sunil Jadav, Rajeevan Chandel Munish Vashishath

Abstract:

Today’s VLSI networks demands for high speed. And in this work the compact form mathematical model for current mode signalling in VLSI interconnects is presented.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect. The on-chip inductance effect is dominant at lower technology node is emulated into an equivalent resistance. First order transfer function is designed using finite difference equation, Laplace transform and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. The novel proposed current mode model shows superior performance as compared to voltage mode signalling. Analysis shows that current mode signalling in VLSI interconnects provides 2.8 times better delay performance than voltage mode. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.

Keywords: Current Mode, Voltage Mode, VLSI Interconnect.

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Authors: Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert

Abstract:

The evolution of logic circuits, which falls under the heading of evolvable hardware, is carried out by evolutionary algorithms. These algorithms are able to automatically configure reconfigurable devices. One of main difficulties in developing evolvable hardware with the ability to design functional electrical circuits is to choose the most favourable EA features such as fitness function, chromosome representations, population size, genetic operators and individual selection. Until now several researchers from the evolvable hardware community have used and tuned these parameters and various rules on how to select the value of a particular parameter have been proposed. However, to date, no one has presented a study regarding the size of the chromosome representation (circuit layout) to be used as a platform for the evolution in order to increase the evolvability, reduce the number of generations and optimize the digital logic circuits through reducing the number of logic gates. In this paper this topic has been thoroughly investigated and the optimal parameters for these EA features have been proposed. The evolution of logic circuits has been carried out by an extrinsic evolvable hardware system which uses (1+λ) evolution strategy as the core of the evolution.

Keywords: Evolvable hardware, genotype size, computational intelligence, design of logic circuits.

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Authors: Chih-Ming Wang, Chih-Yu Wen, Ying-Chung Chen, Chun-Chieh Wang, Chien-Chung Hsu, Jui-Yang Chang, Jyun-Min Lin

Abstract:

In this study, we developed a complementary electrochromic device consisting of WO₃ and NiO films fabricated by rf-magnetron sputtered. The electrochromic properties of WO₃ and NiO films were investigated using cyclic voltammograms (CV), performed on WO₃ and NiO films immersed in an electrolyte of 1 M LiClO₄ in propylene carbonate (PC). Optical and electrochemical of the films, as a function of coloration–bleaching cycle, were characterized using an UV-Vis-NIR spectrophotometer and cyclic voltammetry (CV). After investigating the properties of WO₃ film, NiO film, and complementary electrochromic devices, we concluded that this device provides good reversibility, low power consumption of -2.5 V in color state, high variation of transmittance of 58.96%, changes in optical density of 0.81 and good memory effect under open-circuit conditions. In addition, electrochromic component penetration rate can be retained below 20% within 24h, showing preferred memory features; however, component coloring and bleaching response time are about 33s.

Keywords: Complementary electrochromic device, Rf-magnetron sputtered, Transmittance, Memory effect, Optical density change

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Authors: Vishal Awasthi, Krishna Raj

Abstract:

Unwanted side effects because of spectral aliasing and spectral imaging during signal processing would be the major concern over the sampling rate alteration. Multirate-multistage implementation of digital filter could come about a large computational saving than single rate filter suitable for sample rate conversion. This implementation can further improve through high-level architectural transformation in circuit level. Reallocating registers and  relocating flip-flops across logic gates through retiming certainly a prominent sequential transformation technology, that optimize hardware circuits to achieve faster clocking speed without affecting the functionality. In this paper, we proposed an efficient compensated cascade Integrator comb (CIC) decimation filter structure that analyze the consequence of filter order variation which has a retimed FIR filter being compensator while using the cutset retiming technique and achieved an improvement in the passband droop by 14% to 39%, in computation time by 38.04%, 25.78%, 12.21%, 6.69% and 4.44% and reduction in path delay by 62.27%, 72%, 86.63%, 91.56% and 94.42% of 3, 6, 8, 12 and 24 order filter respectively than the non-retimed CIC compensation filter.

Keywords: Multirate Filtering, CIC decimation filter, Compensation theory, Retiming, Retiming algorithm, Filter order, Synchronous dataflow graph.

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