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Design of an Efficient Retimed CIC Compensation Filter

Authors: Vishal Awasthi, Krishna Raj

Abstract:

Unwanted side effects because of spectral aliasing and spectral imaging during signal processing would be the major concern over the sampling rate alteration. Multirate-multistage implementation of digital filter could come about a large computational saving than single rate filter suitable for sample rate conversion. This implementation can further improve through high-level architectural transformation in circuit level. Reallocating registers and  relocating flip-flops across logic gates through retiming certainly a prominent sequential transformation technology, that optimize hardware circuits to achieve faster clocking speed without affecting the functionality. In this paper, we proposed an efficient compensated cascade Integrator comb (CIC) decimation filter structure that analyze the consequence of filter order variation which has a retimed FIR filter being compensator while using the cutset retiming technique and achieved an improvement in the passband droop by 14% to 39%, in computation time by 38.04%, 25.78%, 12.21%, 6.69% and 4.44% and reduction in path delay by 62.27%, 72%, 86.63%, 91.56% and 94.42% of 3, 6, 8, 12 and 24 order filter respectively than the non-retimed CIC compensation filter.

Keywords: retiming, Multirate Filtering, Compensation Theory, CIC decimation filter, Retiming algorithm, Filter order, Synchronous dataflow graph

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1093428

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References:


[1] E. B. Hogenauer, "An Economical Class of Digital Filters for Decimation and Interpolation", IEEE Trans. on Acoustics, Speech, and Signal Processing, Vol. ASSP-29, pp. 155-162, April 1981.
[2] E. Leiserson, F. M. Rose, and J. B. Saxe., "Optimizing Synchronous Circuitry by Retiming” Proc. of the IIIrd Caltech Conference in Advanced Research in VLS., pages 86–116, Rockville, MD, 1983.
[3] Jovanovic Dolecek and Fred Harris, "Design of CIC Compensator Filter in a Digital IF Receiver”, IEEE Trans. on Circuits and Systems 2008.
[4] Gordana Jovanovic Dolecek and Fred Harris, "On Design of Two-Stage CIC Compensation Filter”, IEEE International Symposium on Industrial Electronics, Seoul, Korea , pp. 903-908, July 5-8, 2009
[5] G. J. Dolecek and M. Laddomada, "An Economical Class of Droop-Compensated Generalized Comb Filters: Analysis and Design”, IEEE Transactions on Circuits and Systems-II, Vol. 57, No.4, pp. 275-279, April 2010.
[6] Alfonso Fernandez-Vazquez, Gordana Jovanovic Dolecek, "Passband and Stopband CIC Improvement based on Efficient IIR Filter Structure”, IEEE Transactions on Circuits and Systems, 2010.
[7] Koichi Ichige, Mamoru Iwaki and Rokuya Ishii, "Accurate Estimation of MinimumFilter Length for Optimum FIR Digital Filters” IEEE Trans. On Circuits And Systems-II: Analog And Digital Signal Processing, Vol. 47, No. 10, pp. 1006-1016, October 2000
[8] Puru Gupta and Tarun Kumar Rawat, " A VLSI DSP Design and Implementation of All Pole Lattice Filter using Retiming Methodology” International Journal of Electronics Signals and Systems (IJESS), Vol-1 Iss-4, 2012
[9] Vojin Zivojnovic and Rainer Schoenen , "On Retiming Of Multirate DSP Algorithms” Integrated Systems for Signal Processing (IS2), Aachen University of Technology,Germany
[10] J. Kwentus, Z. Jiang, and A. N. Willson, Jr., "Application of filter sharpening to cascaded integrator-comb decimation filters,” IEEE Transactions on Signal Processing, vol.45, pp.457-467, February 1997.
[11] Kei-Yong Khoo , Zhan Yu, Wilson, A.N.., "Efficient high-speed CIC decimation filter”, Eleventh Annual IEEE International ASIC Conference, California, pp. 251-254, 13-16 Sep 1998
[12] Shih-Hsu Huang; Feng-Pin Lu; Wei-Chieh Yu and Yow-Tyng Nieh, "Race-condition-aware retiming” International Symposium on VLSI Design, Automation and Test (VLSI-TSA), 2005.
[13] Cong, J. and Xin Yuan, "Multilevel global placement with retiming” IEEE Conference on design automation, 2003.
[14] Chu, E. F. Y. Young, D. K. Y. Tong, and S. Dechu, "Retiming with interconnect and gate delay” in Proc. International Conference on Computer-Aided Design, pages 221–226, 2003.
[15] H. Zhou. Deriving, "A new efficient algorithm for min-period retiming” in Proc. Asian and South Pacific Design Automation Conference, 2005.
[16] H. Zhou and C. Lin., "Retiming for wire pipelining in system-on-chip” IEEE Transactions on Computer Aided Design, 23(9):1338–1345, September 2004.
[17] Dolecek, G.J., Carmona, J.D. "Generalized CIC-cosine decimation filter”, IEEE Symposium on Industrial Electronics & Applications (ISIEA), Mexico, pp. 640-645, 3-5 Oct. 2010
[18] Pecotic, M.G., Molnar, G. ; Vucic, M. "Design of CIC compensators with SPT coefficients based on interval analysis”, Proceedings of the 35th International Convention MIPRO, Croatia, pp. 123-128, 21-25 May 2012.
[19] Y. Diao and Y. L. Wu, "A Fast Retiming Algorithm Integrated with Rewiring for Flip-Flop Reductions” 12th International Conference on Computer-Aided Design and Computer Graphics, 2011.
[20] Yagain, D.; Krishna, A.V. and Chennapnoor, S. "Design optimization platform for synthesizable high speed digital filters using retiming technique” 10th IEEE International Conference on Semiconductor Electronics (ICSE), 2012.
[21] Tracy C. Denk and Keshab K. Parhi, "Exhaustive Scheduling and Retiming of Digital Signal Processing Systems” IEEE Transactions On Circuits And Systems-II: Analog And Digital Signal Processing, Vol. 45, No. 7, July 1998.
[22] Jia Wang and Hai Zhou, "An efficient incremental algorithm for min-area retiming” 45th ACM/IEEE Design Automation Conference, 2008.
[23] N. Liveris, C. Lin, J. Wang, H. Zhou, and P. Banerjee, "Retiming for synchronous data flow graphs,” Proc. of IEEE Asia and South Pacific Design Automation Conference, pp. 480–485, 2007.
[24] Das, D.; Jia Wang and Hai Zhou I., "An efficient incremental algorithm for min-period retiming under general delay model” 15th Asia and South Pacific Conference on Design Automation (ASP-DAC), 2010.
[25] G. J. Dolecek and Fred Harris, "Design of wideband CIC compensator filter for a digital IF receiver”, Digital Signal Processing 19, ELSEVIER, pp. 827–837, April, 2009.
[26] H. K. Yang and W. M. Snelgrove, "High Speed Polyphase CIC Decimation Filters", Proceeding of 1996 IEEE International Conference On Communications, pp. II.229- II.233, Atlanta, US, May 1996.
[27] Yonghong Gao, Lihong Jia, Tenhunen, H. "A partial-polyphase VLSI architecture for very high speed CIC decimation filters”, Twelfth Annual IEEE International ASIC/SOC Conference, Stockholm, pp. 391-395, 1999.