Search results for: P-type adiabatic circuits.

Authors: Abdelrahman A. H. Abdelrahim, Gharib Subhi Mahmoud, Sherzod Turaev, Azeddine Messikh

Abstract:

Quantum gates are the basic building blocks in the quantum circuits model. These gates can be implemented using adiabatic or non adiabatic processes. Adiabatic models can be controlled using auxiliary qubits, whereas non adiabatic models can be simplified by using one single-shot implementation. In this paper, the controlled adiabatic evolutions is combined with the single-shot implementation to obtain quantum gates with controlled non adiabatic evolutions. This is an important improvement which can speed the implementation of quantum gates and reduce the errors due to the long run in the adiabatic model. The robustness of our scheme to different types of errors is also investigated.

Keywords: Adiabatic evolutions, non adiabatic evolutions, controlled adiabatic evolutions, quantum rotation gates, dephasing rates, master equation.

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Authors: Hong Li, Linfeng Li, Jianping Hu

Abstract:

With rapid technology scaling, the proportion of the static power consumption catches up with dynamic power consumption gradually. To decrease leakage consumption is becoming more and more important in low-power design. This paper presents a power-gating scheme for P-DTGAL (p-type dual transmission gate adiabatic logic) circuits to reduce leakage power dissipations under deep submicron process. The energy dissipations of P-DTGAL circuits with power-gating scheme are investigated in different processes, frequencies and active ratios. BSIM4 model is adopted to reflect the characteristics of the leakage currents. HSPICE simulations show that the leakage loss is greatly reduced by using the P-DTGAL with power-gating techniques.

Keywords: Leakage reduction, low power, deep submicronCMOS circuits, P-type adiabatic circuits.

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Authors: Jianping Hu, Xiaolei Sheng

Abstract:

This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz.

Keywords: Low power, Register file, Complementarypass-transistor logic, Adiabatic logic, Single-phase power clock.

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Authors: Shiv Shankar Mishra, S. Wairya, R. K. Nagaria, S. Tiwari

Abstract:

New methodologies for XOR-XNOR circuits are proposed to improve the speed and power as these circuits are basic building blocks of many arithmetic circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. The performance of the XOR-XNOR circuits based on TSMC 0.18μm process models at all range of the supply voltage starting from 0.6V to 3.3V is evaluated by the comparison of the simulation results obtained from HSPICE. Simulation results reveal that the proposed circuit exhibit lower PDP and EDP, more power efficient and faster when compared with best available XOR-XNOR circuits in the literature.

Keywords: Exclusive-OR (XOR), Exclusive-NOR (XNOR), High speed, Low power, Arithmetic Circuits.

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Authors: E. Elgendy, J. Schmidt

Abstract:

Drop-in of R-22 alternatives in refrigeration and air conditioning systems requires a redesign of system components to improve system performance and reliability with the alternative refrigerants. The present paper aims at design adiabatic capillary tubes for R-22 alternatives such as R-417A, R-422D and R-438A. A theoretical model has been developed and validated with the available experimental data from literature for R-22 over a wide range of both operating and geometrical parameters. Predicted lengths of adiabatic capillary tube are compared with the lengths of the capillary tube needed under similar experimental conditions and majority of predictions are found to be within 4.4% of the experimental data. Hence, the model has been applied for R-417A, R- 422D and R-438A and capillary tube selection charts and correlations have been computed. Finally a comparison between the selected refrigerants and R-22 has been introduced and the results showed that R-438A is the closest one to R-22.

Keywords: Adiabatic flow, Capillary tube, R-22 alternatives, Rating charts, Modelling.

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Authors: Shipra Upadhyay , R. K. Nagaria, R. A. Mishra

Abstract:

In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adder circuit exhibits the energy saving of 70% to the conventional CMOS full adder circuit, at 100 MHz frequency and 1.8V operating voltage.

Keywords: Adiabatic, CEPAL, full adder, power clock

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Authors: Zhenguo Vincent Chia, Sheung Yan Simon Ng, Minkyu Je

Abstract:

This paper presents CMOS Current Mode Logic (CML) circuits for a high speed Digital to Analog Converter (DAC) using standard CMOS 65nm process. The CML circuits have the propagation delay advantage over its conventional CMOS counterparts due to smaller output voltage swing and tunable bias current. The CML circuits proposed in this paper can achieve a maximum propagation delay of only 9.3ps, which can satisfy the stringent requirement for the 5 GHz high speed DAC application. Another advantage for CML circuits is its dynamic symmetry characteristic resulting in a reduction of an additional inverter. Simulation results show that the proposed CML circuits can operate from 1.08V to 1.3V with temperature ranging from -40 to +120°C.

Keywords: Conventional, Current Mode Logic, DAC, Decoder

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Authors: Abdulatif A. M. Shaban

Abstract:

Transient simulation of power electronic circuits is of considerable interest to the designer. The switching nature of the devices used permits development of specialized algorithms which allow a considerable reduction in simulation time compared to general purpose simulation algorithms. This paper describes a method used to simulate a power electronic circuits using the SIMULINK toolbox within MATLAB software. Theoretical results are presented provides the basis of transient analysis of a power electronic circuits.

Keywords: Modelling, Simulation.

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Authors: Mohd. Hasan, Ajmal Kafeel, S. D. Pable

Abstract:

Ultra-low-power (ULP) circuits have received widespread attention due to the rapid growth of biomedical applications and Battery-less Electronics. Subthreshold region of transistor operation is used in ULP circuits. Major research challenge in the subthreshold operating region is to extract the ULP benefits with minimal degradation in speed and robustness. Process, Voltage and Temperature (PVT) variations significantly affect the performance of subthreshold circuits. Designed performance parameters of ULP circuits may vary largely due to temperature variations. Hence, this paper investigates the effect of temperature variation on device and circuit performance parameters at different biasing voltages in the subthreshold region. Simulation results clearly demonstrate that in deep subthreshold and near threshold voltage regions, performance parameters are significantly affected whereas in moderate subthreshold region, subthreshold circuits are more immune to temperature variations. This establishes that moderate subthreshold region is ideal for temperature immune circuits.

Keywords: Subthreshold, temperature variations, ultralow power.

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Authors: J. Hajri, H. Hrizi, N. Sboui, H. Baudrand

Abstract:

This paper presents a study of SIW circuits (Substrate Integrated Waveguide) with a rigorous and fast original approach based on Iterative process (WCIP). The theoretical suggested study is validated by the simulation of two different examples of SIW circuits. The obtained results are in good agreement with those of measurement and with software HFSS.

Keywords: Convergence study, HFSS, Modal decomposition, SIW Circuits, WCIP Method.

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Authors: K. Maria Agnes, J. Joshua Bapu

Abstract:

This paper impart the design and testing of Nanotechnology based sequential circuits using multiplexer conservative QCA (MX-CQCA) logic gates, which is easily testable using only two vectors. This method has great prospective in the design of sequential circuits based on reversible conservative logic gates and also smashes the sequential circuits implemented in traditional gates in terms of testability. Reversible circuits are similar to usual logic circuits except that they are built from reversible gates. Designs of multiplexer conservative QCA logic based two vectors testable double edge triggered (DET) sequential circuits in VHDL language are also accessible here; it will also diminish intricacy in testing side. Also other types of sequential circuits such as D, SR, JK latches are designed using this MX-CQCA logic gate. The objective behind the proposed design methodologies is to amalgamate arithmetic and logic functional units optimizing key metrics such as garbage outputs, delay, area and power. The projected MX-CQCA gate outshines other reversible gates in terms of the intricacy, delay.

Keywords: Conservative logic, Double edge triggered (DET) flip flop, majority voters, MX-CQCA gate, reversible logic, Quantum dot Cellular automata.

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Authors: Cecília Reis, J. A. Tenreiro Machado, J. Boaventura Cunha

Abstract:

This paper analyses the performance of a genetic algorithm using a new concept, namely a fractional-order dynamic fitness function, for the synthesis of combinational logic circuits. The experiments reveal superior results in terms of speed and convergence to achieve a solution.

Keywords: Circuit design, fractional-order systems, genetic algorithms, logic circuits.

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Authors: E. Farshidi

Abstract:

In this paper, based on a novel synthesis, a set of new simplified circuit design to implement the linguistic-hedge operations for adjusting the fuzzy membership function set is presented. The circuits work in current-mode and employ floating-gate MOS (FGMOS) transistors that operate in weak inversion region. Compared to the other proposed circuits, these circuits feature severe reduction of the elements number, low supply voltage (0.7V), low power consumption (<200nW), immunity from body effect and wide input dynamic range (>60dB). In this paper, a set of fuzzy linguistic hedge circuits, including absolutely, very, much more, more, plus minus, more or less and slightly, has been implemented in 0.18 mm CMOS process. Simulation results by Hspice confirm the validity of the proposed design technique and show high performance of the circuits.

Keywords: Current-mode, Linguistic-Hedge, Fuzzy Logic, lowpower

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Authors: K. Jaroensutasinee

Abstract:

The general global behavior of particle S a non-linear (Q - xy)2 potential cannot be revealed a Poincare surface of section method (PSS) because inost trajectories take practically infinitely long time to integrate numerically before they come back to the surface. In this study as an alternative to PSS, a multiple scale perturbation is applied to analyze global adiabatic, non-adiabatic and chaotic behavior of particles in this potential. It was found that the results can be summarized as a form of a Fermi-like map. Additionally, this method gives a variation of global stochasticity criteria with Q.

Keywords: Multiple Scak Perturbation The Poincare Surface or Section, Fermi Map

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Authors: Shiang-Hwua Yu, Po-Hsun Wu

Abstract:

This study introduces two types of self-oscillating circuits that are frequently found in power electronics applications. Special effort is made to relate the circuits to the analogous mechanical systems of some important scientific inventions: Galileo’s pendulum clock and Coulomb’s friction model. A little touch of related history and philosophy of science will hopefully encourage curiosity, advance the understanding of self-oscillating systems and satisfy the aspiration of some students for scientific literacy. Finally, the two self-oscillating circuits are applied to design a simple class-D audio amplifier.

Keywords: Self-oscillation, sigma-delta modulator, pendulum clock, Coulomb friction, class-D amplifier.

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Authors: Cecília Reis, J. A. Tenreiro Machado, J. Boaventura Cunha

Abstract:

This paper analyses the performance of a genetic algorithm using a new concept, namely a fractional-order dynamic fitness function, for the synthesis of combinational logic circuits. The experiments reveal superior results in terms of speed and convergence to achieve a solution.

Keywords: Circuit design, fractional-order systems, genetic algorithms, logic circuits

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Authors: Hasan Çiçekli, Ahmet Gökçen, Uğur Çam

Abstract:

In this paper, a comparative performance analysis of mostly used four nonlinearity cancellation techniques used to realize the passive resistor by MOS transistors, is presented. The comparison is done by using an integrator circuit which is employing sequentially Op-amp, OTRA and ICCII as active element. All of the circuits are implemented by MOS-C realization and simulated by PSPICE program using 0.35μm process TSMC MOSIS model parameters. With MOS-C realization, the circuits became electronically tunable and fully integrable which is very important in IC design. The output waveforms, frequency responses, THD analysis results and features of the nonlinearity cancellation techniques are also given.

Keywords: Integrator circuits, MOS-C realization, nonlinearity cancellation, tunable resistors.

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Authors: Konstantin Movsovic, Emanuele Stomeo, Tatiana Kalganova

Abstract:

The evolutionary design of electronic circuits, or evolvable hardware, is a discipline that allows the user to automatically obtain the desired circuit design. The circuit configuration is under the control of evolutionary algorithms. Several researchers have used evolvable hardware to design electrical circuits. Every time that one particular algorithm is selected to carry out the evolution, it is necessary that all its parameters, such as mutation rate, population size, selection mechanisms etc. are tuned in order to achieve the best results during the evolution process. This paper investigates the abilities of evolution strategy to evolve digital logic circuits based on programmable logic array structures when different mutation rates are used. Several mutation rates (fixed and variable) are analyzed and compared with each other to outline the most appropriate choice to be used during the evolution of combinational logic circuits. The experimental results outlined in this paper are important as they could be used by every researcher who might need to use the evolutionary algorithm to design digital logic circuits.

Keywords: Evolvable hardware, evolutionary algorithm, digitallogic circuit, mutation rate.

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Authors: P.K. Sharma, B. Bhargava, S. Akashe

Abstract:

Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.

Keywords: Stack, 6T SRAM cell, low power, threshold voltage

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Authors: Santanu Santra, Utpal Roy

Abstract:

The most important mathematical operation for any computing system is addition. An efficient adder can be of greater assistance in designing of any arithmetic circuits. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology to create electronic circuits for computing devices and suitable candidate for next generation of computing systems. The article presents a modest approach to implement a novel XOR gate. The gate is simple in structure and powerful in terms of implementing digital circuits. By applying the XOR gate, the hardware requirement for a QCA circuit can be decrease and circuits can be simpler in level, clock phase and cell count. In order to verify the functionality of the proposed device some implementation of Half Adder (HA) and Full Adder (FA) is checked by means of computer simulations using QCA-Designer tool. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, Computing system, Majority gate, QCA, QCA Designer.

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Authors: Juhi Faridi, Mohd. Ajmal Kafeel

Abstract:

The advancements in the field of Artificial Intelligence (AI) and technology has led to an evolution of an intelligent era. Neural networks, having the computational power and learning ability similar to the brain is one of the key AI technologies. Neuromorphic computing system (NCS) consists of the synaptic device, neuronal circuit, and neuromorphic architecture. Memristor are a promising candidate for neuromorphic computing systems, but when it comes to neuromorphic computing, the conductance behavior of the synaptic memristor or neuronal memristor needs to be studied thoroughly in order to fathom the neuroscience or computer science. Furthermore, there is a need of more simulation work for utilizing the existing device properties and providing guidance to the development of future devices for different performance requirements. Hence, development of NCS needs more simulation work to make use of existing device properties. This work aims to provide an insight to build neuronal circuits using memristors to achieve a Memristor based NCS.  Here we throw a light on the research conducted in the field of memristors for building analog and digital circuits in order to motivate the research in the field of NCS by building memristor based neural circuits for advanced AI applications. This literature is a step in the direction where we describe the various Key findings about memristors and its analog and digital circuits implemented over the years which can be further utilized in implementing the neuronal circuits in the NCS. This work aims to help the electronic circuit designers to understand how the research progressed in memristors and how these findings can be used in implementing the neuronal circuits meant for the recent progress in the NCS.

Keywords: Analog circuits, digital circuits, memristors, neuromorphic computing systems.

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Authors: Santanu Santra, Utpal Roy

Abstract:

Quantum-dot Cellular Automata (QCA) is one of the most substitute emerging nanotechnologies for electronic circuits, because of lower power consumption, higher speed and smaller size in comparison with CMOS technology. The basic devices, a Quantum-dot cell can be used to implement logic gates and wires. As it is the fundamental building block on nanotechnology circuits. By applying XOR gate the hardware requirements for a QCA circuit can be decrease and circuits can be simpler in terms of level, delay and cell count. This article present a modest approach for implementing novel optimized XOR gate, which can be applied to design many variants of complex QCA circuits. Proposed XOR gate is simple in structure and powerful in terms of implementing any digital circuits. In order to verify the functionality of the proposed design some complex implementation of parity generator and parity checker circuits are proposed and simulating by QCA Designer tool and compare with some most recent design. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, CMOS technology, Logic gates, QCA Designer, Quantum-dot Cellular Automata (QCA).

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Authors: Soojin Kim, Kyeongsoon Cho

Abstract:

This paper describes the pipeline architecture of high-speed modified Booth multipliers. The proposed multiplier circuits are based on the modified Booth algorithm and the pipeline technique which are the most widely used to accelerate the multiplication speed. In order to implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The speed of the multipliers is greatly improved by properly deciding the number of pipeline stages and the positions for the pipeline registers to be inserted. We described the proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits using 0.13um standard cell library. The resultant multiplier circuits show better performance than others. Since the proposed multipliers operate at GHz ranges, they can be used in the systems requiring very high performance.

Keywords: multiplier, pipeline, high-speed, modified Boothalgorithm.

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Authors: S. Grace Sahaya Sheba, R. Omegala Priakumari

Abstract:

Polyethylene glycol (PEG) is a condensation polymer of ethylene oxide and water. It is soluble in water and in many organic solvents. PEG is used to make emulsifying agents, detergents, soaps, plasticizers, ointments etc. Ethanol (C₂H₅OH) also known as ethyl alcohol is a well-known organic compound and has wide applications in chemical industry as it is used as a solvent for paint, varnish, in preserving biological specimens, used as a fuel mixed with petrol etc. Though their chemical and physical properties are already studied, still because of their uses in day to day life the authors thought it is better to study some more of their physical properties like ultrasonic velocity and hence adiabatic compressibility, free length, etc. A detailed study of such properties and some excess parameters like excess adiabatic compressibility, excess free volume and few more in the liquid mixtures of these two compounds with PEG as a solute and Ethanol as a solvent at various mole fractions may throw some light on deeper understanding of molecular interaction between the solute and the solvent supported by NMR, IR etc. Hence the present research work is on ultrasonics/allied studies on these two liquid mixtures. Ultrasonic velocity (U), density (ρ) and viscosity (η) at room temperature and at different mole fraction from 0 to 0.055 of ethanol in PEG have been experimentally carried out by the authors. Acoustical parameters such as adiabatic compressibility (β), free volume (V_f), acoustic impedance (Z), internal pressure (π_i), intermolecular free length (L_f) and relaxation time (τ) were calculated from the experimental data. We have calculated excess parameters like excess adiabatic compressibility (β^E), excess internal pressure (π_i^E) free length (L_f^E) and excess acoustic impedance (Z^E) etc for these two chosen liquid mixtures. The excess compressibility is positive and maximum around a mole fraction 0.007 and excess internal pressure is negative and maximum at the same mole fraction and longer free length. The results are analyzed and it may be concluded that the molecular interactions between the solute and the solvent is not strong and it may be weak. Appropriate graphs are drawn.

Keywords: Adiabatic Compressibility, Binary mixture, Induce dipole, Polarizability, Ultrasonic.

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Authors: Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert

Abstract:

Evolvable hardware (EHW) is a developing field that applies evolutionary algorithm (EA) to automatically design circuits, antennas, robot controllers etc. A lot of research has been done in this area and several different EAs have been introduced to tackle numerous problems, as scalability, evolvability etc. However every time a specific EA is chosen for solving a particular task, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade the selection of the right parameters for the EA-s components for solving different “test-problems" has been investigated. In this paper the behaviour of mutation rate for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies the number of inputs of each logic gates, the functionality (for example from AND to NOR) and the connectivity between logic gates. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates for the evolved circuits. The experimental results found provide the behaviour of the mutation rate during evolution for the design and optimization of simple logic circuits. The experimental results propose the best mutation rate to be used for designing combinational logic circuits. The research presented is particular important for those who would like to implement a dynamic mutation rate inside the evolutionary algorithm for evolving digital circuits. The researches on the mutation rate during the last 40 years are also summarized.

Keywords: Design of logic circuit, evolutionary computation, evolvable hardware, mutation rate.

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Authors: Shane D. Inder, Mehrdad Khamooshi

Abstract:

Efficient energy storage is a crucial factor in facilitating the uptake of renewable energy resources. Among the many options available for energy storage systems required to balance imbalanced supply and demand cycles, compressed air energy storage (CAES) is a proven technology in grid-scale applications. This paper reviews the current state of micro scale CAES technology and describes a micro-scale advanced adiabatic CAES (A-CAES) system, where heat generated during compression is stored for use in the discharge phase. It will also describe a thermodynamic model, developed in EES (Engineering Equation Solver) to evaluate the performance and critical parameters of the discharge phase of the proposed system. Three configurations are explained including: single turbine without preheater, two turbines with preheaters, and three turbines with preheaters. It is shown that the micro-scale A-CAES is highly dependent upon key parameters including; regulator pressure, air pressure and volume, thermal energy storage temperature and flow rate and the number of turbines. It was found that a micro-scale AA-CAES, when optimized with an appropriate configuration, could deliver energy input to output efficiency of up to 70%.

Keywords: CAES, adiabatic compressed air energy storage, expansion phase, micro generation, thermodynamic.

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Authors: Mir Shahriar Emami

Abstract:

Although it is fully impossible to ensure that a software system is quite secure, developing an acceptable secure software system in a convenient platform is not unreachable. In this paper, we attempt to analyze software development life cycle (SDLC) models from the hardware systems and circuits point of view. To date, the SDLC models pay merely attention to the software security from the software perspectives. In this paper, we present new features for SDLC stages to emphasize the role of systems and circuits in developing secure software system through the software development stages, the point that has not been considered previously in the SDLC models.

Keywords: Systems and circuits security, software security, software process engineering, SDLC, SSDLC.

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Authors: S. Summart, C. Saetiaw, T. Thosdeekoraphat, C. Thongsopa

Abstract:

This article presents new current-mode oscillator circuits using CDTAs which is designed from block diagram. The proposed circuits consist of two CDTAs and two grounded capacitors. The condition of oscillation and the frequency of oscillation can be adjusted by electronic method. The circuits have high output impedance and use only grounded capacitors without any external resistor which is very appropriate to future development into an integrated circuit. The results of PSPICE simulation program are corresponding to the theoretical analysis.

Keywords: Current-mode, Quadrature Oscillator, Block Diagram, CDTA.

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Authors: Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert

Abstract:

The evolution of logic circuits, which falls under the heading of evolvable hardware, is carried out by evolutionary algorithms. These algorithms are able to automatically configure reconfigurable devices. One of main difficulties in developing evolvable hardware with the ability to design functional electrical circuits is to choose the most favourable EA features such as fitness function, chromosome representations, population size, genetic operators and individual selection. Until now several researchers from the evolvable hardware community have used and tuned these parameters and various rules on how to select the value of a particular parameter have been proposed. However, to date, no one has presented a study regarding the size of the chromosome representation (circuit layout) to be used as a platform for the evolution in order to increase the evolvability, reduce the number of generations and optimize the digital logic circuits through reducing the number of logic gates. In this paper this topic has been thoroughly investigated and the optimal parameters for these EA features have been proposed. The evolution of logic circuits has been carried out by an extrinsic evolvable hardware system which uses (1+λ) evolution strategy as the core of the evolution.

Keywords: Evolvable hardware, genotype size, computational intelligence, design of logic circuits.

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Authors: Swanti Satsangi, Ashish Gulati, Prem Kumar Kalra, C. Patvardhan

Abstract:

Due to the non- intuitive nature of Quantum algorithms, it becomes difficult for a classically trained person to efficiently construct new ones. So rather than designing new algorithms manually, lately, Genetic algorithms (GA) are being implemented for this purpose. GA is a technique to automatically solve a problem using principles of Darwinian evolution. This has been implemented to explore the possibility of evolving an n-qubit circuit when the circuit matrix has been provided using a set of single, two and three qubit gates. Using a variable length population and universal stochastic selection procedure, a number of possible solution circuits, with different number of gates can be obtained for the same input matrix during different runs of GA. The given algorithm has also been successfully implemented to obtain two and three qubit Boolean circuits using Quantum gates. The results demonstrate the effectiveness of the GA procedure even when the search spaces are large.

Keywords: Ancillas, Boolean functions, Genetic algorithm, Oracles, Quantum circuits, Scratch bit

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