New Design Methodologies for High Speed Low Power XOR-XNOR Circuits

Authors: Shiv Shankar Mishra, S. Wairya, R. K. Nagaria, S. Tiwari

Abstract:

New methodologies for XOR-XNOR circuits are proposed to improve the speed and power as these circuits are basic building blocks of many arithmetic circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. The performance of the XOR-XNOR circuits based on TSMC 0.18μm process models at all range of the supply voltage starting from 0.6V to 3.3V is evaluated by the comparison of the simulation results obtained from HSPICE. Simulation results reveal that the proposed circuit exhibit lower PDP and EDP, more power efficient and faster when compared with best available XOR-XNOR circuits in the literature.

Keywords: Exclusive-OR (XOR), Exclusive-NOR (XNOR), High speed, Low power, Arithmetic Circuits.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1073647

References:

[1] N. Weste, and K. Eshranghian, "Principles of CMOS VLSI Design: A System Perspective," Reading MA: Addison-Wesley, 1993
[2] S.M. Kang, and Y. Leblibici, "CMOS Digital Integrated Circuits: Analysis and Design," Tata McGraw Hill, 2003.
[3] J.Rabaey, "Digital Integrated Circuits: A Design Prospective," Prentice- Hall, Englewood Cliffs, NJ, 1996.
[4] Sung-Chuan Fang, Jyh-Ming Wang, and Wu-Shiung Feng, "A New Direct design for three-input XOR function on the transistor level," IEEE trans. Circuits Syst. I: Fundamental theory and Applications, vol. 43, no. 4, April 1996.
[5] H. T. Bui, Y. Wang, and Y. Jiang, "Design and analysis of low-power 10 transistor full adders using XOR-XNOR gates," IEEE trans. Circuits Syst. II, Analog Digit. Signal Process, vol.49, no. 1, pp. 25-30, Jan. 2002.
[6] D. Radhakrishanan, "Low-voltage low-power CMOS full adder," in Proc. IEE Circuits Devices Syst., vol. 148, Feb. 2001.
[7] K. H. Cheng, and C. S. Huang, "The novel efficient design of XOR/XNOR function for adder applications," in Proc. IEEE Int. Conf. Elect., Circuits Syst. Vol. 1, Sept. 5-8, 1999, pp. 29-32.
[8] J. M. Wang, S. C. Fang , and W. S. Feng, "New efficient designs for XOR and XNOR functions on the transistor level," IEEE J. Solid-State Circuits, Vol. 29, no. 7, pp. 780-786, Jul. 1994.
[9] H.T. Bui, A.K. Al-Sheraidah, and Y. Wang, "New 4- transistor XOR and XNOR designs" in Proc. 2nd IEEE Asia Pacific conf. ASICs, 2000, pp. 25-28.
[10] M. Vesterbacka, "A New six-transistor CMOS XOR Circuits with complementary output," to appear in Proc. 42nd Midwest Symp. On Circuits and Systems, Las Cruces, NM, Aug. 8-11, 1999.
[11] M.A. Elgamel, S. Goel, and M.A. Bayoumi, "Noise tolerant low voltage XOR-XNOR for fast arithmetic," in Proc. Great Lake Symp. VLSI, Washington DC, Apr. 28-29, 2003, pp. 285-288.
[12] R. Zimmermann, and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079-1090, Jul. 1997.
[13] D. Radhakrishanan, S. R. Whitaker, and G. K. Maki, "Formal design procedures for pass-transistor switching circuits," IEEE J. Solid- State Circuits, vol. SC-20. no. 3, pp. 531-536, Jun. 1985.
[14] C. Pedron, and A. Stauffer, "Analysis and synthesis of combinational pass transistor switching circuits," IEEE Trans. Computer- Aided Design Integr. Circuit Syst., vol. 7, no. 7, pp. 775-786, Jul. 1988.
[15] A. M. Shams, T. K. Darwish, and M. A. Bayoumi, "Performance analysis of low-power 1-bit CMOS full adder cells," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, pp. 20-29, Feb. 2002.
[16] S. Goel, M. E. Elgamel, M. A. Bayouni, and Y. Hanafy, "Design Methodologies for high- performance Noise-tolerant XOR-XNOR Circuits", IEEE Trans. Circuits and Syst. I, vol. 53, no. 4, April 2006.