%0 Journal Article
	%A  Shiv Shankar Mishra and  S. Wairya and  R. K. Nagaria and  S. Tiwari
	%D 2009
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 31, 2009
	%T New Design Methodologies for High Speed Low Power XOR-XNOR Circuits
	%U https://publications.waset.org/pdf/9897
	%V 31
	%X New methodologies for XOR-XNOR circuits are
proposed to improve the speed and power as these circuits are basic
building blocks of many arithmetic circuits. This paper evaluates and
compares the performance of various XOR-XNOR circuits. The
performance of the XOR-XNOR circuits based on TSMC 0.18μm
process models at all range of the supply voltage starting from 0.6V
to 3.3V is evaluated by the comparison of the simulation results
obtained from HSPICE. Simulation results reveal that the proposed
circuit exhibit lower PDP and EDP, more power efficient and faster
when compared with best available XOR-XNOR circuits in the
	%P 1427 - 1433