Commenced in January 2007
Paper Count: 30067
SCR-Stacking Structure with High Holding Voltage for I/O and Power Clamp
Abstract:In this paper, we proposed a novel SCR (Silicon Controlled Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O and power clamp. The proposed device has a higher holding voltage characteristic than conventional SCR. These characteristics enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in term of individual design parameters (D1, D2, D3). They are investigated by using the Synopsys TCAD simulator. As a result of simulation, holding voltage increased with different design parameters. The holding voltage of the proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD device with the high holding voltage is proposed. In the simulation results, 2-stack has holding voltage of 6.8V and 3-stack has holding voltage of 10.5V. The simulation results show that holding voltage of stacking structure can be larger than the operation voltage of high-voltage application.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1107469Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF
 Albert Z, H. Wang, On-Chip ESD Protection for Integrated devices 2nd ed. Springer, US, 2002
 R.G Wagner, J. Soden and C.F. Hawkins ‘Extend and Cost of EOS/ESD Damage in an IC Manufacturing Process’, in Porc. of the 15th EOS/ESD Symp., pp49-55, 1993.
 V. Vashchenko, A. Sinkevitch, V.F., “Physical Limitaions of Semiconductor Devices, Springer, p.340, 2008
 C. Russ, M. P. J. Mergens, J. Armer, P. Jozwiak, G.Kolluri, L. Avery, and K. Vergaegem, “GGSCR: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep submicron CMOS processes,” in Proc. EOS/ESD Symp., 2001, pp.22-31.
 J. A. Salcedo, J. J. Liou, and J. C. Bernier, “Novel and robust silicon controlled rectifier (SCR) based devices fo on-chip ESD protection,” IEEE Electron device Lett., vol. 25, no. 9, pp. 658-660, September 2004.
 Markus P. J. Mergens, Christian C. Russ, et al, “ High holding current SCRs for ESD protection and latch-up immune IC operation,” Microelectronics Reliability, vol. 43, pp.993-1000, 2003.
 M.D Ker, et al., “How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on,” Journal of Electro- statics, Vol. 47, pp. 215-248, 1999.
 Yong Seo Koo, et al., “Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology,” Microelectronics Journal, Vol. 40, pp. 1007-1012, 2009.
 Sheng-Lyang Jang, et al., “Temperature-dependent dynamic triggering characteristics of SCR-type ESD protection devices,” Solid-State Electronics, Vol.45, pp. 2005-2009, 2001.
 W.Y Chen, et al., “Measurement on Snapback Holding voltage of High-Voltage LDMOS for Latch-up Consideration,” device and system, APCCAS 2008, pp. 61-64, 2008.
 Yong Seo Koo, “Electrical characteristics of novel SCR-based ESD protection for power clamp,” IEICE Electronics Express, vol.9, no.18,