Search results for: Paul Müller

Authors: Padmanabhan Balasubramanian, C. Ardil

Abstract:

In this paper, we consider the problem of logic simplification for a special class of logic functions, namely complementary Boolean functions (CBF), targeting low power implementation using static CMOS logic style. The functions are uniquely characterized by the presence of terms, where for a canonical binary 2-tuple, D(mj) ∪ D(mk) = { } and therefore, we have | D(mj) ∪ D(mk) | = 0 [19]. Similarly, D(Mj) ∪ D(Mk) = { } and hence | D(Mj) ∪ D(Mk) | = 0. Here, 'mk' and 'Mk' represent a minterm and maxterm respectively. We compare the circuits minimized with our proposed method with those corresponding to factored Reed-Muller (f-RM) form, factored Pseudo Kronecker Reed-Muller (f-PKRM) form, and factored Generalized Reed-Muller (f-GRM) form. We have opted for algebraic factorization of the Reed-Muller (RM) form and its different variants, using the factorization rules of [1], as it is simple and requires much less CPU execution time compared to Boolean factorization operations. This technique has enabled us to greatly reduce the literal count as well as the gate count needed for such RM realizations, which are generally prone to consuming more cells and subsequently more power consumption. However, this leads to a drawback in terms of the design-for-test attribute associated with the various RM forms. Though we still preserve the definition of those forms viz. realizing such functionality with only select types of logic gates (AND gate and XOR gate), the structural integrity of the logic levels is not preserved. This would consequently alter the testability properties of such circuits i.e. it may increase/decrease/maintain the same number of test input vectors needed for their exhaustive testability, subsequently affecting their generalized test vector computation. We do not consider the issue of design-for-testability here, but, instead focus on the power consumption of the final logic implementation, after realization with a conventional CMOS process technology (0.35 micron TSMC process). The quality of the resulting circuits evaluated on the basis of an established cost metric viz., power consumption, demonstrate average savings by 26.79% for the samples considered in this work, besides reduction in number of gates and input literals by 39.66% and 12.98% respectively, in comparison with other factored RM forms.

Keywords: Reed-Muller forms, Logic function, Hammingdistance, Algebraic factorization, Low power design.

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Authors: Paul Y. Oh, William E. Green

Abstract:

This paper describes a prototype aircraft that can fly slowly, safely and transmit wireless video for tasks like reconnaissance, surveillance and target acquisition. The aircraft is designed to fly in closed quarters like forests, buildings, caves and tunnels which are often spacious but GPS reception is poor. Envisioned is that a small, safe and slow flying vehicle can assist in performing dull, dangerous and dirty tasks like disaster mitigation, search-and-rescue and structural damage assessment.

Keywords: Unmanned aerial vehicles, autonomous collisionavoidance, optic flow, near-Earth environments

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Authors: Priyanka Gupta, Paul Verma, Kerry Hourigan, Jayesh Bellare, Sameer Jadhav

Abstract:

Understanding the consumption and production of various metabolites of fibroblast conditioned media is needed for its proper and optimized use in expansion of pluripotent stem cells. For this purpose, we have used the HPLC method to analyse the consumption of glucose and the production of lactate over time by mouse embryonic fibroblasts. The experimental data have also been compared with mathematical model fits. 0.025 moles of lactate was produced after 72 hrs while the glucose concentration decreased from 0.017 moles to 0.011 moles. The mathematical model was able to predict the trends of glucose consumption and lactate production.

Keywords: Conditioned media, HPLC, metabolite analysis, mouse embryonic fibroblast.

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Authors: Ibrahim F. Elbaba, Paul T. Williams

Abstract:

Hydrogen is regarded to play an important role in future energy systems because it can be produced from abundant resources and its combustion only generates water. The disposal of waste tyres is a major problem in environmental management throughout the world. The use of waste materials as a source of hydrogen is particularly of interest in that it would also solve a waste treatment problem. There is much interest in the use of alternative feedstocks for the production of hydrogen since more than 95% of current production is from fossil fuels. The pyrolysis of waste tyres for the production of liquid fuels, activated carbons and gases has been extensively researched. However, combining pyrolysis with gasification is a novel process that can gasify the gaseous products from pyrolysis. In this paper, an experimental investigation into the production of hydrogen and other gases from the bench scale pyrolysis-gasification of tyres has been investigated. Experiments were carried using a two stage system consisting of pyrolysis of the waste tyres followed by catalytic steam gasification of the evolved gases and vapours in a second reactor. Experiments were conducted at a pyrolysis temperature of 500 °C using Ni/Al2O3 as a catalyst. The results showed that there was a dramatic increase in gas yield and the potential H2 production when the gasification temperature was increased from 600 to 900 oC. Overall, the process showed that high yields of hydrogen can be produced from waste tyres.

Keywords: Catalyst, Hydrogen, Pyrolysis, Gasification, Tyre, Waste

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Authors: Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P., J. Raja paul perinbam

Abstract:

An efficient architecture for low jitter All Digital Phase Locked Loop (ADPLL) suitable for high speed SoC applications is presented in this paper. The ADPLL is designed using standard cells and described by Hardware Description Language (HDL). The ADPLL implemented in a 90 nm CMOS process can operate from 10 to 200 MHz and achieve worst case frequency acquisition in 14 reference clock cycles. The simulation result shows that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps at 100MHz. Since the digitally controlled oscillator (DCO) can achieve both high resolution and wide frequency range, it can meet the demands of system-level integration. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for System-on-Chip (SoC) applications.

Keywords: All Digital Phase Locked Loop (ADPLL), Systemon-Chip (SoC), Phase Locked Loop (PLL), Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL), Digitally Controlled Oscillator (DCO), Phase frequencydetector (PFD) and Voltage Controlled Oscillator (VCO).

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