Search results for: FieldProgrammable Gate Array (FPGA)
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 571

Search results for: FieldProgrammable Gate Array (FPGA)

421 Design and Optimization of Parity Generator and Parity Checker Based On Quantum-dot Cellular Automata

Authors: Santanu Santra, Utpal Roy

Abstract:

Quantum-dot Cellular Automata (QCA) is one of the most substitute emerging nanotechnologies for electronic circuits, because of lower power consumption, higher speed and smaller size in comparison with CMOS technology. The basic devices, a Quantum-dot cell can be used to implement logic gates and wires. As it is the fundamental building block on nanotechnology circuits. By applying XOR gate the hardware requirements for a QCA circuit can be decrease and circuits can be simpler in terms of level, delay and cell count. This article present a modest approach for implementing novel optimized XOR gate, which can be applied to design many variants of complex QCA circuits. Proposed XOR gate is simple in structure and powerful in terms of implementing any digital circuits. In order to verify the functionality of the proposed design some complex implementation of parity generator and parity checker circuits are proposed and simulating by QCA Designer tool and compare with some most recent design. Simulation results and physical relations confirm its usefulness in implementing every digital circuit.

Keywords: Clock, CMOS technology, Logic gates, QCA Designer, Quantum-dot Cellular Automata (QCA).

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420 Angles of Arrival Estimation with Unitary Partial Propagator

Authors: Youssef Khmou, Said Safi

Abstract:

In this paper, we investigated the effect of real valued transformation of the spectral matrix of the received data for Angles Of Arrival estimation problem.  Indeed, the unitary transformation of Partial Propagator (UPP) for narrowband sources is proposed and applied on Uniform Linear Array (ULA).

Monte Carlo simulations proved the performance of the UPP spectrum comparatively with Forward Backward Partial Propagator (FBPP) and Unitary Propagator (UP). The results demonstrates that when some of the sources are fully correlated and closer than the Rayleigh angular limit resolution of the broadside array, the UPP method outperforms the FBPP in both of spatial resolution and complexity.

Keywords: DOA, Uniform Linear Array, Narrowband, Propagator, Real valued transformation, Subspace, Unitary Operator.

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419 Lowering Error Floors by Concatenation of Low-Density Parity-Check and Array Code

Authors: Cinna Soltanpur, Mohammad Ghamari, Behzad Momahed Heravi, Fatemeh Zare

Abstract:

Low-density parity-check (LDPC) codes have been shown to deliver capacity approaching performance; however, problematic graphical structures (e.g. trapping sets) in the Tanner graph of some LDPC codes can cause high error floors in bit-error-ratio (BER) performance under conventional sum-product algorithm (SPA). This paper presents a serial concatenation scheme to avoid the trapping sets and to lower the error floors of LDPC code. The outer code in the proposed concatenation is the LDPC, and the inner code is a high rate array code. This approach applies an interactive hybrid process between the BCJR decoding for the array code and the SPA for the LDPC code together with bit-pinning and bit-flipping techniques. Margulis code of size (2640, 1320) has been used for the simulation and it has been shown that the proposed concatenation and decoding scheme can considerably improve the error floor performance with minimal rate loss.

Keywords: Concatenated coding, low–density parity–check codes, array code, error floors.

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418 A Very High Speed, High Resolution Current Comparator Design

Authors: Neeraj K. Chasta

Abstract:

This paper presents an idea for analog current comparison which compares input signal and reference currents with high speed and accuracy. Proposed circuit utilizes amplification properties of common gate configuration, where voltage variations of input current are amplified and a compared output voltage is developed. Cascaded inverter stages are used to generate final CMOS compatible output voltage. Power consumption of circuit can be controlled by the applied gate bias voltage. The comparator is designed and studied at 180nm CMOS process technology for a supply voltage of 3V.

Keywords: Current Mode, Comparator, High Resolution, High Speed.

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417 Fabrication and Characterization of Poly-Si Vertical Nanowire Thin Film Transistor

Authors: N. Shen, T. T. Le, H. Y. Yu, Z. X. Chen, K. T. Win, N. Singh, G. Q. Lo, D. -L. Kwong

Abstract:

In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 106, low drain-induced barrier lowering (DIBL) of 50 mV/V, and low sub-threshold slope SS~100mV/dec are demonstrated for a device with channel length of 100 nm.

Keywords: Nanowire (NW), Gate-all-around (GAA), polysilicon (poly-Si), thin-film transistor (TFT).

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416 A Reversible CMOS AD / DA Converter Implemented with Pseudo Floating-Gate

Authors: Omid Mirmotahari, Yngvar Berg, Ahmad Habibizad Navin

Abstract:

Reversible logic is becoming more and more prominent as the technology sets higher demands on heat, power, scaling and stability. Reversible gates are able at any time to "undo" the current step or function. Multiple-valued logic has the advantage of transporting and evaluating higher bits each clock cycle than binary. Moreover, we demonstrate in this paper, combining these disciplines we can construct powerful multiple-valued reversible logic structures. In this paper a reversible block implemented by pseudo floatinggate can perform AD-function and a DA-function as its reverse application.

Keywords: Reversible logic, bi-directional, Pseudo floating-gate(PFG), multiple-valued logic (MVL).

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415 Optimization Modeling of the Hybrid Antenna Array for the DoA Estimation

Authors: Somayeh Komeylian

Abstract:

The direction of arrival (DoA) estimation is the crucial aspect of the radar technologies for detecting and dividing several signal sources. In this scenario, the antenna array output modeling involves numerous parameters including noise samples, signal waveform, signal directions, signal number, and signal to noise ratio (SNR), and thereby the methods of the DoA estimation rely heavily on the generalization characteristic for establishing a large number of the training data sets. Hence, we have analogously represented the two different optimization models of the DoA estimation; (1) the implementation of the decision directed acyclic graph (DDAG) for the multiclass least-squares support vector machine (LS-SVM), and (2) the optimization method of the deep neural network (DNN) radial basis function (RBF). We have rigorously verified that the LS-SVM DDAG algorithm is capable of accurately classifying DoAs for the three classes. However, the accuracy and robustness of the DoA estimation are still highly sensitive to technological imperfections of the antenna arrays such as non-ideal array design and manufacture, array implementation, mutual coupling effect, and background radiation and thereby the method may fail in representing high precision for the DoA estimation. Therefore, this work has a further contribution on developing the DNN-RBF model for the DoA estimation for overcoming the limitations of the non-parametric and data-driven methods in terms of array imperfection and generalization. The numerical results of implementing the DNN-RBF model have confirmed the better performance of the DoA estimation compared with the LS-SVM algorithm. Consequently, we have analogously evaluated the performance of utilizing the two aforementioned optimization methods for the DoA estimation using the concept of the mean squared error (MSE).

Keywords: DoA estimation, adaptive antenna array, Deep Neural Network, LS-SVM optimization model, radial basis function, MSE.

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414 Impact of Process Variations on the Vertical Silicon Nanowire Tunneling FET (TFET)

Authors: Z. X. Chen, T. S. Phua, X. P. Wang, G. -Q. Lo, D. -L. Kwong

Abstract:

This paper presents device simulations on the vertical silicon nanowire tunneling FET (VSiNW TFET). Simulations show that a narrow nanowire and thin gate oxide is required for good performance, which is expected even for conventional MOSFETs. The gate length also needs to be more than the nanowire diameter to prevent short channel effects. An effect more unique to TFET is the need for abrupt source to channel junction, which is shown to improve the performance. The ambipolar effect suppression by reducing drain doping concentration is also explored and shown to have little or no effect on performance.

Keywords: Device simulation, MEDICI, tunneling FET (TFET), vertical silicon nanowire.

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413 Design and Testing of Nanotechnology Based Sequential Circuits Using MX-CQCA Logic in VHDL

Authors: K. Maria Agnes, J. Joshua Bapu

Abstract:

This paper impart the design and testing of Nanotechnology based sequential circuits using multiplexer conservative QCA (MX-CQCA) logic gates, which is easily testable using only two vectors. This method has great prospective in the design of sequential circuits based on reversible conservative logic gates and also smashes the sequential circuits implemented in traditional gates in terms of testability. Reversible circuits are similar to usual logic circuits except that they are built from reversible gates. Designs of multiplexer conservative QCA logic based two vectors testable double edge triggered (DET) sequential circuits in VHDL language are also accessible here; it will also diminish intricacy in testing side. Also other types of sequential circuits such as D, SR, JK latches are designed using this MX-CQCA logic gate. The objective behind the proposed design methodologies is to amalgamate arithmetic and logic functional units optimizing key metrics such as garbage outputs, delay, area and power. The projected MX-CQCA gate outshines other reversible gates in terms of the intricacy, delay.

Keywords: Conservative logic, Double edge triggered (DET) flip flop, majority voters, MX-CQCA gate, reversible logic, Quantum dot Cellular automata.

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412 Performance Analysis of Adaptive OFDM Pre and Post-FTT Beamforming System

Authors: S. Elnobi, Iman El-Zahaby, Amr M. Mahros

Abstract:

In mobile communication systems, performance and capacity are affected by multi-path fading, delay spread and Co-Channel Interference (CCI). For this reason Orthogonal Frequency Division Multiplexing (OFDM) and adaptive antenna array are used is required. The goal of the OFDM is to improve the system performance against Inter-Symbol Interference (ISI). An array of adaptive antennas has been employed to suppress CCI by spatial technique. To suppress CCI in OFDM systems two main schemes the pre-FFT and the post-FFT have been proposed. In this paper, through a system level simulation, the behavior of the pre-FFT and post-FFT beamformers for OFDM system has been investigated based on two algorithms namely, Least Mean Squares (LMS) and Recursive Least Squares (RLS). The performance of the system is also discussed in multipath fading channel system specified by 3GPP Long Term Evolution (LTE).

Keywords: OFDM, Beamforming, Adaptive Antennas Array.

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411 Selection of an Optimum Configuration of Solar PV Array under Partial Shaded Condition Using Particle Swarm Optimization

Authors: R. Ramaprabha

Abstract:

This paper presents an extraction of maximum energy from Solar Photovoltaic Array (SPVA) under partial shaded conditions by optimum selection of array size using Particle Swarm Optimization (PSO) technique. In this paper a detailed study on the output reduction of different SPVA configurations under partial shaded conditions have been carried out. A generalized MATLAB M-code based software model has been used for any required array size, configuration, shading patterns and number of bypass diodes. Comparative study has been carried out on different configurations by testing several shading scenarios. While the number of shading patterns and the rate of change are very low for stationary SPVA but these may be quite large for SPVA mounted on a mobile platforms. This paper presents the suitability of PSO technique to select optimum configuration for mobile arrays by calculating the global peak (GP) of different configurations and to transfer maximum power to the load.

Keywords: Global peak, Mobile PV arrays, Partial shading, optimization, PSO.

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410 Design of Wireless Readout System for Resonant Gas Sensors

Authors: S. Mohamed Rabeek, Mi Kyoung Park, M. Annamalai Arasu

Abstract:

This paper presents a design of a wireless read out system for tracking the frequency shift of the polymer coated piezoelectric micro electromechanical resonator due to gas absorption. The measure of this frequency shift indicates the percentage of a particular gas the sensor is exposed to. It is measured using an oscillator and an FPGA based frequency counter by employing the resonator as a frequency determining element in the oscillator. This system consists of a Gas Sensing Wireless Readout (GSWR) and an USB Wireless Transceiver (UWT). GSWR consists of an oscillator based on a trans-impedance sustaining amplifier, an FPGA based frequency readout, a sub 1GHz wireless transceiver and a micro controller. UWT can be plugged into the computer via USB port and function as a wireless module to transfer gas sensor data from GSWR to the computer through its USB port. GUI program running on the computer periodically polls for sensor data through UWT - GSWR wireless link, the response from GSWR is logged in a file for post processing as well as displayed on screen.

Keywords: Gas sensor, GSWR, micro-mechanical system, UWT, volatile emissions.

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409 Assessment of Solar Hydrogen Production in an Energetic Hybrid PV-PEMFC System

Authors: H. Rezzouk, M. Hatti, H. Rahmani, S. Atoui

Abstract:

This paper discusses the design and analysis of a hybrid PV-Fuel cell energy system destined to power a DC load. The system is composed of a photovoltaic array, a fuel cell, an electrolyzer and a hydrogen tank. HOMER software is used in this study to calculate the optimum capacities of the power system components that their combination allows an efficient use of solar resource to cover the hourly load needs. The optimal system sizing allows establishing the right balance between the daily electrical energy produced by the power system and the daily electrical energy consumed by the DC load using a 28 KW PV array, a 7.5 KW fuel cell, a 40KW electrolyzer and a 270 Kg hydrogen tank. The variation of powers involved into the DC bus of the hybrid PV-fuel cell system has been computed and analyzed for each hour over one year: the output powers of the PV array and the fuel cell, the input power of the elctrolyzer system and the DC primary load. Equally, the annual variation of stored hydrogen produced by the electrolyzer has been assessed. The PV array contributes in the power system with 82% whereas the fuel cell produces 18%. 38% of the total energy consumption belongs to the DC primary load while the rest goes to the electrolyzer.

Keywords: Electrolyzer, Hydrogen, Hydrogen Fueled Cell, Photovoltaic.

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408 Design and Implementation of Reed Solomon Encoder on FPGA

Authors: Amandeep Singh, Mandeep Kaur

Abstract:

Error correcting codes are used for detection and correction of errors in digital communication system. Error correcting coding is based on appending of redundancy to the information message according to a prescribed algorithm. Reed Solomon codes are part of channel coding and withstand the effect of noise, interference and fading. Galois field arithmetic is used for encoding and decoding reed Solomon codes. Galois field multipliers and linear feedback shift registers are used for encoding the information data block. The design of Reed Solomon encoder is complex because of use of LFSR and Galois field arithmetic. The purpose of this paper is to design and implement Reed Solomon (255, 239) encoder with optimized and lesser number of Galois Field multipliers. Symmetric generator polynomial is used to reduce the number of GF multipliers. To increase the capability toward error correction, convolution interleaving will be used with RS encoder. The Design will be implemented on Xilinx FPGA Spartan II.

Keywords: Galois Field, Generator polynomial, LFSR, Reed Solomon.

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407 Automatic Deactivation in Phased Array Probe for Human Prostate Magnetic Resonance Imaging at 1.5T

Authors: Fotios N. Vlachos, Anastasios D. Garetsos, Nikolaos K. Uzunoglu, Efstathios D. Gotsis

Abstract:

A four element prototype phased array surface probe has been designed and constructed to improve clinical human prostate spectroscopic data. The probe consists of two pairs of adjacent rectangular coils with an optimum overlap to reduce the mutual inductance. The two pairs are positioned on the anterior and the posterior pelvic region and two couples of varactors at the input of each coil undertake the procedures of tuning and matching. The probe switches off and on automatically during the consecutive phases of the MR experiment with the use of an analog switch that is triggered by a microcontroller. Experimental tests that were carried out resulted in high levels of tuning accuracy. Also, the switching mechanism functions properly for various applied loads and pulse sequence characteristics, producing only 10 μs of latency.

Keywords: Automatic tuning, prostate imaging, phased array, spectroscopy.

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406 Game-Tree Simplification by Pattern Matching and Its Acceleration Approach using an FPGA

Authors: Suguru Ochiai, Toru Yabuki, Yoshiki Yamaguchi, Yuetsu Kodama

Abstract:

In this paper, we propose a Connect6 solver which adopts a hybrid approach based on a tree-search algorithm and image processing techniques. The solver must deal with the complicated computation and provide high performance in order to make real-time decisions. The proposed approach enables the solver to be implemented on a single Spartan-6 XC6SLX45 FPGA produced by XILINX without using any external devices. The compact implementation is achieved through image processing techniques to optimize a tree-search algorithm of the Connect6 game. The tree search is widely used in computer games and the optimal search brings the best move in every turn of a computer game. Thus, many tree-search algorithms such as Minimax algorithm and artificial intelligence approaches have been widely proposed in this field. However, there is one fundamental problem in this area; the computation time increases rapidly in response to the growth of the game tree. It means the larger the game tree is, the bigger the circuit size is because of their highly parallel computation characteristics. Here, this paper aims to reduce the size of a Connect6 game tree using image processing techniques and its position symmetric property. The proposed solver is composed of four computational modules: a two-dimensional checkmate strategy checker, a template matching module, a skilful-line predictor, and a next-move selector. These modules work well together in selecting next moves from some candidates and the total amount of their circuits is small. The details of the hardware design for an FPGA implementation are described and the performance of this design is also shown in this paper.

Keywords: Connect6, pattern matching, game-tree reduction, hardware direct computation

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405 Laser Ultrasonic Imaging Based on Synthetic Aperture Focusing Technique Algorithm

Authors: Sundara Subramanian Karuppasamy, Che Hua Yang

Abstract:

In this work, the laser ultrasound technique has been used for analyzing and imaging the inner defects in metal blocks. To detect the defects in blocks, traditionally the researchers used piezoelectric transducers for the generation and reception of ultrasonic signals. These transducers can be configured into the sparse and phased array. But these two configurations have their drawbacks including the requirement of many transducers, time-consuming calculations, limited bandwidth, and provide confined image resolution. Here, we focus on the non-contact method for generating and receiving the ultrasound to examine the inner defects in aluminum blocks. A Q-switched pulsed laser has been used for the generation and the reception is done by using Laser Doppler Vibrometer (LDV). Based on the Doppler effect, LDV provides a rapid and high spatial resolution way for sensing ultrasonic waves. From the LDV, a series of scanning points are selected which serves as the phased array elements. The side-drilled hole of 10 mm diameter with a depth of 25 mm has been introduced and the defect is interrogated by the linear array of scanning points obtained from the LDV. With the aid of the Synthetic Aperture Focusing Technique (SAFT) algorithm, based on the time-shifting principle the inspected images are generated from the A-scan data acquired from the 1-D linear phased array elements. Thus the defect can be precisely detected with good resolution.

Keywords: Laser ultrasonics, linear phased array, nondestructive testing, synthetic aperture focusing technique, ultrasonic imaging.

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404 A Microcontroller Implementation of Constrained Model Predictive Control

Authors: Amira Kheriji Abbes, Faouzi Bouani, Mekki Ksouri

Abstract:

Model Predictive Control (MPC) is an established control technique in a wide range of process industries. The reason for this success is its ability to handle multivariable systems and systems having input, output or state constraints. Neverthless comparing to PID controller, the implementation of the MPC in miniaturized devices like Field Programmable Gate Arrays (FPGA) and microcontrollers has historically been very small scale due to its complexity in implementation and its computation time requirement. At the same time, such embedded technologies have become an enabler for future manufacturing enterprisers as well as a transformer of organizations and markets. In this work, we take advantage of these recent advances in this area in the deployment of one of the most studied and applied control technique in the industrial engineering. In this paper, we propose an efficient firmware for the implementation of constrained MPC in the performed STM32 microcontroller using interior point method. Indeed, performances study shows good execution speed and low computational burden. These results encourage to develop predictive control algorithms to be programmed in industrial standard processes. The PID anti windup controller was also implemented in the STM32 in order to make a performance comparison with the MPC. The main features of the proposed constrained MPC framework are illustrated through two examples.

Keywords: Embedded software, microcontroller, constrainedModel Predictive Control, interior point method, PID antiwindup, Keil tool, C/Cµ language.

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403 Integration of Resistive Switching Memory Cell with Vertical Nanowire Transistor

Authors: Xiang Li, Zhixian Chen, Zheng Fang, Aashit Kamath, Xinpeng Wang, Navab Singh, Guo-Qiang Lo, Dim-Lee Kwong

Abstract:

We integrate TiN/Ni/HfO2/Si RRAM cell with a vertical gate-all-around (GAA) nanowire transistor to achieve compact 4F2 footprint in a 1T1R configuration. The tip of the Si nanowire (source of the transistor) serves as bottom electrode of the memory cell. Fabricated devices with nanowire diameter ~ 50nm demonstrate ultra-low current/power switching; unipolar switching with 10μA/30μW SET and 20μA/30μW RESET and bipolar switching with 20nA/85nW SET and 0.2nA/0.7nW RESET. Further, the switching current is found to scale with nanowire diameter making the architecture promising for future scaling.

Keywords: RRAM, 1T1R, gate-all-around FET, nanowire FET, vertical MOSFETs

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402 Integrated Flavor Sensor Using Microbead Array

Authors: Ziba Omidi, Min-Ki Kim

Abstract:

This research presents the design, fabrication and application of a flavor sensor for an integrated electronic tongue and electronic nose that can allow rapid characterization of multi-component mixtures in a solution. The odor gas and liquid are separated using hydrophobic porous membrane in micro fluidic channel. The sensor uses an array composed of microbeads in micromachined cavities localized on silicon wafer. Sensing occurs via colorimetric and fluorescence changes to receptors and indicator molecules that are attached to termination sites on the polymeric microbeads. As a result, the sensor array system enables simultaneous and near-real-time analyses using small samples and reagent volumes with the capacity to incorporate significant redundancies. One of the key parts of the system is a passive pump driven only by capillary force. The hydrophilic surface of the fluidic structure draws the sample into the sensor array without any moving mechanical parts. Since there is no moving mechanical component in the structure, the size of the fluidic structure can be compact and the fabrication becomes simple when compared to the device including active microfluidic components. These factors should make the proposed system inexpensive to mass-produce, portable and compatible with biomedical applications.

Keywords: Optical Sensor, Semiconductor manufacturing, Smell sensor, Taste sensor.

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401 A Voltage Based Maximum Power Point Tracker for Low Power and Low Cost Photovoltaic Applications

Authors: Jawad Ahmad, Hee-Jun Kim

Abstract:

This paper describes the design of a voltage based maximum power point tracker (MPPT) for photovoltaic (PV) applications. Of the various MPPT methods, the voltage based method is considered to be the simplest and cost effective. The major disadvantage of this method is that the PV array is disconnected from the load for the sampling of its open circuit voltage, which inevitably results in power loss. Another disadvantage, in case of rapid irradiance variation, is that if the duration between two successive samplings, called the sampling period, is too long there is a considerable loss. This is because the output voltage of the PV array follows the unchanged reference during one sampling period. Once a maximum power point (MPP) is tracked and a change in irradiation occurs between two successive samplings, then the new MPP is not tracked until the next sampling of the PV array voltage. This paper proposes an MPPT circuit in which the sampling interval of the PV array voltage, and the sampling period have been shortened. The sample and hold circuit has also been simplified. The proposed circuit does not utilize a microcontroller or a digital signal processor and is thus suitable for low cost and low power applications.

Keywords: Maximum power point tracker, Sample and hold amplifier, Sampling interval, Sampling period.

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400 Noninvasive Disease Diagnosis through Breath Analysis Using DNA-Functionalized SWNT Sensor Array

Authors: Wenjun Zhang, Yunqing Du, Ming L. Wang

Abstract:

Noninvasive diagnostics of diseases via breath analysis has attracted considerable scientific and clinical interest for many years and become more and more promising with the rapid advancements in nanotechnology and biotechnology. The volatile organic compounds (VOCs) in exhaled breath, which are mainly blood borne, particularly provide highly valuable information about individuals’ physiological and pathophysiological conditions. Additionally, breath analysis is noninvasive, real-time, painless, and agreeable to patients. We have developed a wireless sensor array based on single-stranded DNA (ssDNA)-functionalized single-walled carbon nanotubes (SWNT) for the detection of a number of physiological indicators in breath. Seven DNA sequences were used to functionalize SWNT sensors to detect trace amount of methanol, benzene, dimethyl sulfide, hydrogen sulfide, acetone, and ethanol, which are indicators of heavy smoking, excessive drinking, and diseases such as lung cancer, breast cancer, and diabetes. Our test results indicated that DNA functionalized SWNT sensors exhibit great selectivity, sensitivity, and repeatability; and different molecules can be distinguished through pattern recognition enabled by this sensor array. Furthermore, the experimental sensing results are consistent with the Molecular Dynamics simulated ssDNAmolecular target interaction rankings. Thus, the DNA-SWNT sensor array has great potential to be applied in chemical or biomolecular detection for the noninvasive diagnostics of diseases and personal health monitoring.

Keywords: Breath analysis, DNA-SWNT sensor array, diagnosis, noninvasive.

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399 Bed Evolution under One-Episode Flushing in a Truck Sewer in Paris, France

Authors: Gashin Shahsavari, Gilles Arnaud-Fassetta, Roberto Bertilotti, Alberto Campisano, Fabien Riou

Abstract:

Sewer deposits have been identified as a major cause of dysfunctions in combined sewer systems regarding sewer management, which induces different negative consequents resulting in poor hydraulic conveyance, environmental damages as well as worker’s health. In order to overcome the problematics of sedimentation, flushing has been considered as the most operative and cost-effective way to minimize the sediments impacts and prevent such challenges. Flushing, by prompting turbulent wave effects, can modify the bed form depending on the hydraulic properties and geometrical characteristics of the conduit. So far, the dynamics of the bed-load during high-flow events in combined sewer systems as a complex environment is not well understood, mostly due to lack of measuring devices capable to work in the “hostile” in combined sewer system correctly. In this regards, a one-episode flushing issue from an opening gate valve with weir function was carried out in a trunk sewer in Paris to understand its cleansing efficiency on the sediments (thickness: 0-30 cm). During more than 1h of flushing within 5 m distance in downstream of this flushing device, a maximum flowrate and a maximum level of water have been recorded at 5 m in downstream of the gate as 4.1 m3/s and 2.1 m respectively. This paper is aimed to evaluate the efficiency of this type of gate for around 1.1 km (from the point -50 m to +1050 m in downstream from the gate) by (i) determining bed grain-size distribution and sediments evolution through the sewer channel, as well as their organic matter content, and (ii) identifying sections that exhibit more changes in their texture after the flush. For the first one, two series of sampling were taken from the sewer length and then analyzed in laboratory, one before flushing and second after, at same points among the sewer channel. Hence, a non-intrusive sampling instrument has undertaken to extract the sediments smaller than the fine gravels. The comparison between sediments texture after the flush operation and the initial state, revealed the most modified zones by the flush effect, regarding the sewer invert slope and hydraulic parameters in the zone up to 400 m from the gate. At this distance, despite the increase of sediment grain-size rages, D50 (median grainsize) varies between 0.6 mm and 1.1 mm compared to 0.8 mm and 10 mm before and after flushing, respectively. Overall, regarding the sewer channel invert slope, results indicate that grains smaller than sands (< 2 mm) are more transported to downstream along about 400 m from the gate: in average 69% before against 38% after the flush with more dispersion of grain-sizes distributions. Furthermore, high effect of the channel bed irregularities on the bed material evolution has been observed after the flush.

Keywords: Bed-material load evolution, combined sewer systems, flushing efficiency, sediment transport.

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398 The Design of PFM Mode DC-DC Converter with DT-CMOS Switch

Authors: Jae-Chang Kwak, Yong-Seo Koo

Abstract:

The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.

Keywords: DT-CMOS, PMIC, PFM, DC-DC converter.

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397 Dosimetric Comparison of aSi1000 EPID and ImatriXX 2-D Array System for Volumetric Modulated Arc and Intensity Modulated Radiotherapy Patient Specific Quality Assurance

Authors: Jayesh K., Ganesh T., Suganthi D., Mohan R., Rakesh C. J., Sarojkumar D. M., Jacob S. J.

Abstract:

Prior to the use of detectors, characteristics comparison study was performed and baseline established. In patient specific QA, the portal dosimetry mean values of area gamma, average gamma and maximum gamma were 1.02, 0.31 and 1.31 with standard deviation of 0.33, 0.03 and 0.14 for IMRT and the corresponding values were 1.58, 0.48 and 1.73 with standard deviation of 0.31, 0.06 and 0.66 for VMAT. With ImatriXX 2-D array system, on an average 99.35% of the pixels passed the criteria of 3%-3 mm gamma with standard deviation of 0.24 for dynamic IMRT. For VMAT, the average value was 98.16% with a standard deviation of 0.86. The results showed that both the systems can be used in patient specific QA measurements for IMRT and VMAT. The values obtained with the portal dosimetry system were found to be relatively more consistent compared to those obtained with ImatriXX 2-D array system.

Keywords: Gamma, IMRT, QA, TPS, VMAT.

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396 A Simple and Efficient Method for Accurate Measurement and Control of Power Frequency Deviation

Authors: S. J. Arif

Abstract:

In the presented technique, a simple method is given for accurate measurement and control of power frequency deviation. The sinusoidal signal for which the frequency deviation measurement is required is transformed to a low voltage level and passed through a zero crossing detector to convert it into a pulse train. Another stable square wave signal of 10 KHz is obtained using a crystal oscillator and decade dividing assemblies (DDA). These signals are combined digitally and then passed through decade counters to give a unique combination of pulses or levels, which are further encoded to make them equally suitable for both control applications and display units. The developed circuit using discrete components has a resolution of 0.5 Hz and completes measurement within 20 ms. The realized circuit is simulated and synthesized using Verilog HDL and subsequently implemented on FPGA. The results of measurement on FPGA are observed on a very high resolution logic analyzer. These results accurately match the simulation results as well as the results of same circuit implemented with discrete components. The proposed system is suitable for accurate measurement and control of power frequency deviation.

Keywords: Digital encoder for frequency measurement, frequency deviation measurement, measurement and control systems, power systems.

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395 Photovoltaic Array Sizing for PV-Electrolyzer

Authors: Panhathai Buasri

Abstract:

Hydrogen that used as fuel in fuel cell vehicles can be produced from renewable sources such as wind, solar, and hydro technologies. PV-electrolyzer is one of the promising methods to produce hydrogen with zero pollution emission. Hydrogen production from a PV-electrolyzer system depends on the efficiency of the electrolyzer and photovoltaic array, and sun irradiance at that site. In this study, the amount of hydrogen is obtained using mathematical equations for difference driving distance and sun peak hours. The results show that the minimum of 99 PV modules are used to generate 1.75 kgH2 per day for two vehicles.

Keywords: About four key words or phrases in alphabetical order, separated by commas.

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394 Performance Analysis of MUSIC, Root-MUSIC and ESPRIT DOA Estimation Algorithm

Authors: N. P. Waweru, D. B. O. Konditi, P. K. Langat

Abstract:

Direction of Arrival estimation refers to defining a mathematical function called a pseudospectrum that gives an indication of the angle a signal is impinging on the antenna array. This estimation is an efficient method of improving the quality of service in a communication system by focusing the reception and transmission only in the estimated direction thereby increasing fidelity with a provision to suppress interferers. This improvement is largely dependent on the performance of the algorithm employed in the estimation. Many DOA algorithms exists amongst which are MUSIC, Root-MUSIC and ESPRIT. In this paper, performance of these three algorithms is analyzed in terms of complexity, accuracy as assessed and characterized by the CRLB and memory requirements in various environments and array sizes. It is found that the three algorithms are high resolution and dependent on the operating environment and the array size. 

Keywords: Direction of Arrival, Autocorrelation matrix, Eigenvalue decomposition, MUSIC, ESPRIT, CRLB.

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393 Polarization Modulation by free-Standing Asymmetric Hole Arrays

Authors: Hong-Wen Hsieh, Shun-Tung Yen

Abstract:

We theoretically demonstrate modulation of light polarization by a crossed rectangular hole array with asymmetric arm lengths. There are two waveguide modes that can modulate the x- and y- polarized incident waves independently. A specific structure is proposed to convert a left-hand incident wave to a right-hand outgoing wave by transmission.

Keywords: Crossed rectangular hole array, extraordinary optical transmission, polarization modulation.

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392 Massively-Parallel Bit-Serial Neural Networks for Fast Epilepsy Diagnosis: A Feasibility Study

Authors: Si Mon Kueh, Tom J. Kazmierski

Abstract:

There are about 1% of the world population suffering from the hidden disability known as epilepsy and major developing countries are not fully equipped to counter this problem. In order to reduce the inconvenience and danger of epilepsy, different methods have been researched by using a artificial neural network (ANN) classification to distinguish epileptic waveforms from normal brain waveforms. This paper outlines the aim of achieving massive ANN parallelization through a dedicated hardware using bit-serial processing. The design of this bit-serial Neural Processing Element (NPE) is presented which implements the functionality of a complete neuron using variable accuracy. The proposed design has been tested taking into consideration non-idealities of a hardware ANN. The NPE consists of a bit-serial multiplier which uses only 16 logic elements on an Altera Cyclone IV FPGA and a bit-serial ALU as well as a look-up table. Arrays of NPEs can be driven by a single controller which executes the neural processing algorithm. In conclusion, the proposed compact NPE design allows the construction of complex hardware ANNs that can be implemented in a portable equipment that suits the needs of a single epileptic patient in his or her daily activities to predict the occurrences of impending tonic conic seizures.

Keywords: Artificial Neural Networks, bit-serial neural processor, FPGA, Neural Processing Element.

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