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Lowering Error Floors by Concatenation of Low-Density Parity-Check and Array Code

Authors: Cinna Soltanpur, Mohammad Ghamari, Behzad Momahed Heravi, Fatemeh Zare


Low-density parity-check (LDPC) codes have been shown to deliver capacity approaching performance; however, problematic graphical structures (e.g. trapping sets) in the Tanner graph of some LDPC codes can cause high error floors in bit-error-ratio (BER) performance under conventional sum-product algorithm (SPA). This paper presents a serial concatenation scheme to avoid the trapping sets and to lower the error floors of LDPC code. The outer code in the proposed concatenation is the LDPC, and the inner code is a high rate array code. This approach applies an interactive hybrid process between the BCJR decoding for the array code and the SPA for the LDPC code together with bit-pinning and bit-flipping techniques. Margulis code of size (2640, 1320) has been used for the simulation and it has been shown that the proposed concatenation and decoding scheme can considerably improve the error floor performance with minimal rate loss.

Keywords: concatenated coding, low–density parity–check codes, array code, error floors

Digital Object Identifier (DOI):

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[1] David J.C. MacKay and Radford M. Neal, "Near Shannon Limit Performance of Low Density Parity Check Codes," Electronics Letters, July 1996.
[2] Lin, S., & Costello, D. “Error Control Coding: Fundamentals and Applications,” Upper Saddle River, NJ: Prentice Hall, 2004.
[3] D. MacKay and M. Postol, “Weakness of margulis and ramanujan margulis low-density parity-check codes,” Electronic Notes in Theoretical Computer Science, vol. 74, 2003.
[4] T. Richardson, “Error floors of LDPC codes," in Proc. 41st Allerton Conf. Commun., Control, Computing, Allerton House, Monticello, IL, USA, Oct. 2003.
[5] T. Tian, C. Jones, J. Villasenor, and R. Wesel, “Construction of irregular ldpc codes with low error floors,” in Proc. of IEEE ICC ’03., vol. 5, pp. 3125–3129, May 2003.
[6] H. Xiao and A. Banihashemi, “Improved progressive-edge-growth (peg) construction of irregular ldpc codes,” IEEE Communications Letters, vol. 8, no. 12, pp. 715–717, Dec. 2004.
[7] E. Cavus and B. Daneshrad, “A performance improvement and error floor avoidance technique for belief propagation decoding of LDPC codes,” in Proc. 16th IEEE International Symposium Pers., Indoor Mobile Radio Commun., vol. 4, pp. 2386-2390, Sept. 2005.
[8] Chilappagari S.K., Sankaranarayanan S., Vasic B, ‘Error Floors of LDPC Codes on the Binary Symmetric Channel,”Proc. IEEE Conf. Comms ICC'06,pp.1089-1094, 2006.
[9] Zhang Y. and RyanW.E., “Toward Low LDPC-Code Floors: A Case Study,” IEEE Transactions on Communications, vol. 57, pp.1566-1573, 2009.
[10] Han Y. and Ryan Y. E. “Low-floor decoders for LDPC codes,” IEEE Transactions on Communications, vol. 57, pp. 1663 – 1673, June 2009.
[11] Kang J., Zhang L., Ding Z., and Lin S., “A Two-Stage Iterative Decoding of LDPC Codes for Lowering Error Floors,” IEEE "GLOBECOM", 2008.
[12] Ryan W.E., Lin S., “Channel Codes: Classical and Modern,” Cambridge Press, 2009
[13] D. M. Rankin and T. A. Gulliver, “Single parity-check product codes,” IEEE Transactions on Communications, vol. 49, pp. 1354–1362, Aug. 2001.
[14] MacKay D., and Postol M., “Weakness of margulis and ramanujan margulis low-density parity-check codes,” Electronic Notes in Theoretical Computer Science, vol. 74, 2003.
[15] Rosenthal, J., and Vontobel, P. O. “Constructions of LDPC codes using Ramanujan graphs and ideas from Margulis.” In Proceedings of the 38th Annual Allerton Conference on Communication, Control, and Computing, pp. 248, 2000.