Massively-Parallel Bit-Serial Neural Networks for Fast Epilepsy Diagnosis: A Feasibility Study

Authors: Si Mon Kueh, Tom J. Kazmierski

Abstract:

There are about 1% of the world population suffering from the hidden disability known as epilepsy and major developing countries are not fully equipped to counter this problem. In order to reduce the inconvenience and danger of epilepsy, different methods have been researched by using a artificial neural network (ANN) classification to distinguish epileptic waveforms from normal brain waveforms. This paper outlines the aim of achieving massive ANN parallelization through a dedicated hardware using bit-serial processing. The design of this bit-serial Neural Processing Element (NPE) is presented which implements the functionality of a complete neuron using variable accuracy. The proposed design has been tested taking into consideration non-idealities of a hardware ANN. The NPE consists of a bit-serial multiplier which uses only 16 logic elements on an Altera Cyclone IV FPGA and a bit-serial ALU as well as a look-up table. Arrays of NPEs can be driven by a single controller which executes the neural processing algorithm. In conclusion, the proposed compact NPE design allows the construction of complex hardware ANNs that can be implemented in a portable equipment that suits the needs of a single epileptic patient in his or her daily activities to predict the occurrences of impending tonic conic seizures.

Keywords: Artificial Neural Networks, bit-serial neural processor, FPGA, Neural Processing Element.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1124673

References:

[1] Y. Chen and W. du Plessis, “Neural network implementation on a fpga,” in Africon Conference in Africa, 2002. IEEE AFRICON. 6th, vol. 1, Oct 2002, pp. 337–342 vol.1.
[2] Akin, M. and Arserim, M. A. and Kiymik, M.K. and Turkoglu, I., “A new approach for diagnosing epilepsy by using wavelet transform and neural networks,” in Engineering in Medicine and Biology Society, 2001. Proceedings of the 23rd Annual International Conference of the IEEE, vol. 2, 2001, pp. 1596–1599 vol.2.
[3] M. Freeman and J. Austin, “Designing a binary neural network co-processor,” in Digital System Design, 2005. Proceedings. 8th Euromicro Conference on, Aug 2005, pp. 223–226.
[4] D. Roy Chowdhury, I. Gupta, and P. Pal Chaudhuri, “A low-cost high-capacity associative memory design using cellular automata,” Computers, IEEE Transactions on, vol. 44, no. 10, pp. 1260–1264, Oct 1995.
[5] A. Shafer, L. Parker, and E. Swartzlander, “The fully-serial pipelined multiplier,” in Signals, Systems and Computers (ASILOMAR), 2011 Conference Record of the Forty Fifth Asilomar Conference on, Nov 2011, pp. 1817–1822.
[6] M. Saleheen, H. Alemzadeh, A. Cheriyan, Z. Kalbarczyk, and R. Iyer, “An efficient embedded hardware for high accuracy detection of epileptic seizures,” in Biomedical Engineering and Informatics (BMEI), 2010 3rd International Conference on, vol. 5, Oct 2010, pp. 1889–1896.
[7] T. Matsumoto, Y. Shin, H. Takase, H. Kawanaka, and S. Tsuruoka, “A learning method for extended spikeprop without redundant spikes #x2014; automatic adjustment of hidden units,” in Soft Computing and Intelligent Systems (SCIS), 2014 Joint 7th International Conference on and Advanced Intelligent Systems (ISIS), 15th International Symposium on, Dec 2014, pp. 1465–1469.
[8] H. Fang, Y. Wang, and J. He, “Spiking neural networks for cortical neuronal spike train decoding,” Neural Computation, vol. 22, no. 4, pp. 1060–1085, April 2010.
[9] Izhikevich, E.M., “Simple model of spiking neurons,” Neural Networks, IEEE Transactions on, vol. 14, no. 6, pp. 1569–1572, Nov 2003.
[10] Cheng-Wen Ko, Hsiao-Wen Chung , “Automatic spike detection via an artificial neural network using raw EEG data: effects of data preparation and implications in the limitations of online recognition,” Clinical Neurophysiology - 1, vol. 111, no. 3, pp. 477–481, March 2000.
[11] J. Ko, C. Lu, M. Srivastava, J. Stankovic, A. Terzis, and M. Welsh, “Wireless sensor networks for healthcare,” Proceedings of the IEEE, vol. 98, no. 11, pp. 1947–1960, Nov 2010.
[12] B. Svensson and T. Nordstrom, “Execution of neural network algorithms on an array of bit-serial processors,” in Pattern Recognition, 1990. Proceedings., 10th International Conference on, vol. ii, June 1990, pp. 501–505 vol.2.
[13] T. J. Kazmierski and C. Leech, “Synthesis of application specific processor architectures for ultra-low energy consumption,” in Small Systems Simulation Symposium, February 2014. (Online). Available: http://eprints.soton.ac.uk/366668/