Search results for: CMOS Inverter

Authors: Apinan Aurasopon, Worawat Sa-ngiavibool

Abstract:

This paper proposes a feed-forward control in a halfbridge resonant dc link inverter. The configuration of feed-forward control is based on synchronous sigma-delta modulation and the halfbridge resonant dc link inverter consists of two inductors, one capacitor and two power switches. The simulation results show the proposed technique can reject non-ideal dc bus improving the total harmonic distortion.

Keywords: Feed-forward control, Resonant dc link inverter, Synchronous sigma-delta modulation.

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Authors: L. Ashok Kumar, N. Sujith Kumar

Abstract:

Most of the PV systems are designed with transformer for safety purpose with galvanic isolation. However, the transformer is big, heavy and expensive. Also, it reduces the overall frequency of the conversion stage. Generally PV inverter with transformer is having efficiency around 92%–94% only. To overcome these problems, transformerless PV system is introduced. It is smaller, lighter, cheaper and higher in efficiency. However, dangerous leakage current will flow between PV array and the grid due to the stray capacitance. There are different types of configurations available for transformerless inverters like H5, H6, HERIC, oH5, and Dual paralleled buck inverter. But each configuration is suffering from its own disadvantages like high conduction losses, shoot-through issues of switches, dead-time requirements at zero crossing instants of grid voltage to avoid grid shoot-through faults and MOSFET reverse recovery issues. The main objective of the proposed transformerless inverter is to address two key issues: One key issue for a transformerless inverter is that it is necessary to achieve high efficiency compared to other existing inverter topologies. Another key issue is that the inverter configuration should not have any shoot-through issues for higher reliability.

Keywords: Leakage current, common mode (CM), photovoltaic (PV) systems, pulse width modulation (PWM).

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Authors: S. Selvaperumal, M. S. Sivagamasundari

Abstract:

In this paper, selective harmonic elimination pulse width modulation technique is employed to eliminate lower order harmonics like third by determination of solving non-linear equations. The cascaded H-bridge five level inverter is driven by the Peripheral Interface Controlled (PIC) Microcontroller 16F877A. The performance of single phase cascaded H-bridge five level inverter with relevant to harmonics and a variety of switches with solar cell as its input source is simulated by employing MATLAB/Simulink. A hardware model is developed to verify the performance of the developed system.

Keywords: Multilevel inverter, cascaded H-Bridge multilevel inverter, total harmonic distortion, selective harmonic elimination pulse width modulation, MATLAB.

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Authors: Khaled A. Madi

Abstract:

Induction motors are being used in greater numbers throughout a wide variety of industrial and commercial applications because it provides many benefits and reliable device to convert the electrical energy into mechanical motion. In some application it-s desired to control the speed of the induction motor. Because of the physics of the induction motor the preferred method of controlling its speed is to vary the frequency of the AC voltage driving the motor. In recent years, with the microcontroller incorporated into an appliance it becomes possible to use it to generate the variable frequency AC voltage to control the speed of the induction motor. This study investigates the microcontroller based variable frequency power inverter. the microcontroller is provide the variable frequency pulse width modulation (PWM) signal that control the applied voltage on the gate drive, which is provides the required PWM frequency with less harmonics at the output of the power inverter. The fully controlled bridge voltage source inverter has been implemented with semiconductors power devices isolated gate bipolar transistor (IGBT), and the PWM technique has been employed in this inverter to supply the motor with AC voltage. The proposed drive system for three & single phase power inverter is simulated using Matlab/Simulink. The Matlab Simulation Results for the proposed system were achieved with different SPWM. From the result a stable variable frequency inverter over wide range has been obtained and a good agreement has been found between the simulation and hardware of a microcontroller based single phase inverter.

Keywords: Power, inverter, PWM, microcontroller.

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Authors: Z.A. Jaffery, Vinay Kumar Chandna, Sunil Kumar Chaudhary

Abstract:

This paper present a MATLAB-SIMULINK model of a single phase 2.5 KVA, 240V RMS controlled PV VSI (Photovoltaic Voltage Source Inverter) inverter using IGBTs (Insulated Gate Bipolar Transistor). The behavior of output voltage, output current, and the total harmonic distortion (THD), with the variation in input dc blocking capacitor (Cdc), for linear and non-linear load has been analyzed. The values of Cdc as suggested by the other authors in their papers are not clearly defined and it poses difficulty in selecting the proper value. As the dc power stored in Cdc, (generally placed parallel with battery) is used as input to the VSI inverter. The simulation results shows the variation in the output voltage and current with different values of Cdc for linear and non-linear load connected at the output side of PV VSI inverter and suggest the selection of suitable value of Cdc.

Keywords: DC Blocking capacitor, IGBTs, PV VSI, THD.

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Authors: Mahdi Ebrahimzadeh

Abstract:

In this paper we introduce an ultra low power CMOS LC oscillator and analyze a method to design a low power low phase noise complementary CMOS LC oscillator. A 1.8GHz oscillator is designed based on this analysis. The circuit has power supply equal to 1.1 V and dissipates 0.17 mW power. The oscillator is also optimized for low phase noise behavior. The oscillator phase noise is -126.2 dBc/Hz and -144.4 dBc/Hz at 1 MHz and 8 MHz offset respectively.

Keywords: LC oscillator, Low Power, Low Phase Noise

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Authors: Irtaza M. Syed, Kaamran Raahemifar

Abstract:

This paper presents a model predictive control (MPC) of a utility interactive (UI) single phase inverter (SPI) for a photovoltaic (PV) system at residential/distribution level. The proposed model uses single-phase phase locked loop (PLL) to synchronize SPI with the grid and performs MPC control in a dq reference frame. SPI model consists of boost converter (BC), maximum power point tracking (MPPT) control, and a full bridge (FB) voltage source inverter (VSI). No PI regulators to tune and carrier and modulating waves are required to produce switching sequence. Instead, the operational model of VSI is used to synthesize sinusoidal current and track the reference. Model is validated using a three kW PV system at the input of UI-SPI in Matlab/Simulink. Implementation and results demonstrate simplicity and accuracy, as well as reliability of the model.

Keywords: Matlab/Simulink, Model Predictive Control, Phase Locked Loop, Single Phase Inverter, Voltage Source Inverter.

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Authors: Gao Wei, Xu Minglu, Xu Yan, Zhang Xiaotong, Wang Xinghua

Abstract:

A 3.5-bit stage of the CMOS pipelined ADC is proposed. In this report, the main part of 3.5-bit stage ADC is introduced. How the MDAC, comparator and encoder worked and designed are shown in details. Besides, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with differential amplifier, this OTA achieve high-gain and high-speed. This design was using CMOS 0.18um process and simulation in Cadence. The result of the simulation shows that the OTA has a gain up to 80dB, the unity gain bandwidth of about 1.138GHz with 2pF load.

Keywords: pipelined ADC, MDAC, operational amplifier.

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Authors: Nasir Mehmood, Saad Rahman, Vinodh Ravinath, Mahesh Balaji

Abstract:

This paper describes the design of a programmable FSK-modulator based on VCO and its implementation in 0.35m CMOS process. The circuit is used to transmit digital data at 100Kbps rate in the frequency range of 400-600MHz. The design and operation of the modulator is discussed briefly. Further the characteristics of PLL, frequency synthesizer, VCO and the whole design are elaborated. The variation among the proposed and tested specifications is presented. Finally, the layout of sub-modules, pin configurations, final chip and test results are presented.

Keywords: FSK Modulator, CMOS, VCO, Phase Locked Loop, Frequency Synthesizer.

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Authors: Wai Pan Chan, Minkyu Je

Abstract:

A precision CMOS chopping amplifier is adopted in this work to improve a CMOS temperature sensor high sensitive enough for intracranial temperature monitoring. An amplified temperature sensitivity of 18.8 ± 3*0.2 mV/oC is attained over the temperature range from 20 oC to 80 oC from a given 10 samples of the same wafer. The analog frontend design outputs the temperature dependent and the temperature independent signals which can be directly interfaced to a 10 bit ADC to accomplish an accurate temperature instrumentation system.

Keywords: Chopping, analog frontend, CMOS temperature sensor, traumatic brain injury (TBI), intracranial temperature monitoring.

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Authors: M. Aleshams, A. Shahsavandi

Abstract:

This paper describes a CMOS four-quadrant multiplier intended for use in the front-end receiver by utilizing the square-law characteristic of the MOS transistor in the saturation region. The circuit is based on 0.35 um CMOS technology simulated using HSPICE software. The mixer has a third-order inter the power consumption is 271uW from a single 1.2V power supply. One of the features of the proposed design is using two MOS transistors limitation to reduce the supply voltage, which leads to reduce the power consumption. This technique provides a GHz bandwidth response and low power consumption.

Keywords: RF-Mixer, Multiplier, cut-off frequency, power consumption

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Authors: Irtaza M. Syed, Kaamran Raahemifar

Abstract:

This paper presents a model predictive control (MPC) of a utility interactive three phase inverter (TPI) for a photovoltaic (PV) system at commercial level. The proposed model uses phase locked loop (PLL) to synchronize the TPI with the power electric grid (PEG) and performs MPC control in a dq reference frame. TPI model consists of a boost converter (BC), maximum power point tracking (MPPT) control, and a three-leg voltage source inverter (VSI). The operational model of VSI is used to synthesize the sinusoidal current and track the reference. The model is validated using a 35.7 kW PV system in Matlab/Simulink. Implementation results show simplicity and accuracy, as well as reliability of the model.

Keywords: Model predictive control, three phase voltage source inverter, PV system, Matlab/Simulink.

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Authors: B. M. Manjunatha, D. V. Ashok Kumar, M. Vijay Kumar

Abstract:

This paper proposes five level diode clamped Z source Inverter. The existing PWM techniques used for ZSI are restricted for two level. The two level Z Source Inverter have high harmonic distortions which effects the performance of the grid connected PV system. To improve the performance of the system the number of voltage levels in the output waveform need to be increased. This paper presents comparative analysis of a five level diode clamped Z source Inverter with different carrier based Modified Pulse Width Modulation techniques. The parameters considered for comparison are output voltage, voltage gain, voltage stress across switch and total harmonic distortion when powered by same DC supply. Analytical results are verified using MATLAB.

Keywords: Diode Clamped, Pulse Width Modulation, total harmonic distortion, Z Source Inverter.

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Authors: Kelaiaia Mounia Samira, Labar Hocine, Bounaya Kamel, Kelaiaia Samia

Abstract:

With the rapid advanced of technology, the industrial processes become increasingly demanding, from the point of view, power quality and controllability. The advent of multi levels inverters responds partially to these requirements. But actually, the new generation of multi-cells inverters permits to reach more performances, since, it offers more voltage levels. The disadvantage in the increase of voltage levels by the number of cells in cascades is on account of series igbts synchronisation loss, from where, a limitation of cells in cascade to 4. Regarding to these constraints, a new topology is proposed in this paper, which increases the voltage levels of the three-cell inverter from 4 to 8; with the same number of igbts, and using less stored energy in the flaying capacitors. The details of operation and modelling of this new inverter structure are also presented, then tested thanks to a three phase induction motor. KeywordsFlaying capacitors, Multi-cells inverter, pwm, switchers, modelling.

Keywords: Flaying capacitors, Multi-cells inverter, pwm, switchers, modelling.

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Authors: J. S. Kim, N. P. Hong

Abstract:

In this paper, a CMOS vector modulator designed for wireless backhaul system based on 802.11ac is presented. A poly phase filter and sign select switches yield two orthogonal signal paths. Two variable gain amplifiers with strongly reduced phase shift of only ±5 ° are used to weight these paths. It has a phase control range of 360 ° and a gain range of -10 dB to 10 dB. The current drawn from a 1.2 V supply amounts 20.4 mA. Using a 0.13 mm technology, the chip die area amounts 1.47x0.75 mm².

Keywords: CMOS, vector modulator, backhaul, 802.11ac.

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Authors: Bachir Belmadani, Rachid Taleb, Zinelaabidine Boudjema, Adil Yahdou

Abstract:

Carrier-based methods have been used widely for switching of multilevel inverters due to their simplicity, flexibility and reduced computational requirements compared to space vector modulation (SVM). This paper focuses on Multicarrier Sinusoidal Pulse Width Modulation (MCSPWM) strategy for the three phase Five-Level Flying Capacitor Inverter (5LFCI). The inverter is simulated for Induction Motor (IM) load and Total Harmonic Distortion (THD) for output waveforms is observed for different controlling schemes.

Keywords: Flying capacitor inverter, multicarrier sinusoidal pulse width modulation, space vector modulation, total harmonic distortion, induction motor.

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Authors: Shashank Gautam

Abstract:

This paper proposes techniques like MT CMOS, POWER GATING, DUAL STACK, GALEOR and LECTOR to reduce the leakage power. A Full Adder has been designed using these techniques and power dissipation is calculated and is compared with general CMOS logic of Full Adder. Simulation results show the validity of the proposed techniques is effective to save power dissipation and to increase the speed of operation of the circuits to a large extent.

Keywords: Low Power, MT CMOS, Galeor, Lector, Power Gating, Dual Stack, Full Adder.

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Authors: Montree Kumngern, Kobchai Dejhan

Abstract:

Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and current mirrors are the basic building blocks in realization scheme. This technique provides; wide dynamic range, wide-bandwidth response and low power consumption. The major advantages of this approach are; its has single ended inputs; since its input is dual translinear loop operate in class-AB mode which make this multiplier configuration interesting for low-power applications; current multiplying, voltage multiplying, or current and voltage multiplying can be obtainable with balanced input. The simulation results of versatile analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth of about 19MHz, a maximum power consumption of 0.46mW, and temperature compensated. Operation of versatile analog multiplier was also confirmed through an experiment using CMOS transistor array.

Keywords: Class-AB, dual-mode CMOS analog multiplier, CMOS analog integrated circuit, CMOS translinear integrated circuit.

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Authors: Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Keivan Navi

Abstract:

In this paper we present two novel 1-bit full adder cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output structures are used to design the adder blocks. Characteristic of dynamic logic leads to higher speeds than the other standard static full adder cells. Using HSpice and 0.18┬Ám CMOS technology exhibits a significant decrease in the cell delay which can result in a considerable reduction in the power-delay product (PDP). The PDP of Multi-Output design at 1.8v power supply is around 0.15 femto joule that is 5% lower than conventional dynamic full adder cell and at least 21% lower than other static full adders.

Keywords: Bridge Style, Dynamic Logic, Full Adder, HighSpeed, Multi Output, NP-CMOS, Zipper.

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Authors: R. Kamalakannan, N. Ravi Kumar

Abstract:

The global energy consumption is increasing persistently and need for distributed power generation through renewable energy is essential. To meet the power requirements for consumers without any voltage fluctuations and losses, modeling and design of multilevel inverter with Flexible AC Transmission System (FACTS) capability is presented. The presented inverter is provided with 13-level cascaded H-bridge topology of Insulated Gate Bipolar Transistor (IGBTs) connected along with inbuilt Distributed Static Synchronous Compensators (DSTATCOM). The DSTATCOM device provides control of power factor stability at local feeder lines and the inverter eliminates Total Harmonic Distortion (THD). The 13-level inverter utilizes 52 switches of each H-bridge is fed with single DC sources separately and the Pulse Width Modulation (PWM) technique is used for switching IGBTs. The control strategy implemented for inverter transmits active power to grid as well as it maintains power factor to be stable with achievement of steady state power transmission. Significant outcome of this project is improvement of output voltage quality with steady state power transmission with low THD. Simulation of inverter with DSTATCOM is performed using MATLAB/Simulink environment. The scaled prototype model of proposed inverter is built and its results were validated with simulated results.

Keywords: FACTS devices, distributed-Static synchronous compensators, DSTATCOM, total harmonics elimination, modular multilevel converter.

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Authors: Rohana Musa, Yuzman Yusoff, Chia Chieu Yin, Hanif Che Lah

Abstract:

This paper presents the design and characterization of a low power Complementary Metal Oxide Semiconductor (CMOS) process sensor. The design is targeted for implementation using Silterra’s 180 nm CMOS process technology. The proposed process sensor employs a voltage threshold (V_th) extractor architecture for detection of variations in the fabrication process. The process sensor generates output voltages in the range of 401 mV (fast-fast corner) to 443 mV (slow-slow corner) at nominal condition. The power dissipation for this process sensor is 6.3 µW with a supply voltage of 1.8V with a silicon area of 190 µm X 60 µm. The preliminary result of this process sensor that was fabricated indicates a close resemblance between test and simulated results.

Keywords: CMOS Process sensor, Process, Voltage and Temperature (PVT) sensor, threshold extractor circuit, Vth extractor circuit.

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Authors: Apinan Aurasopon, Worawat Sa-ngiavibool

Abstract:

This paper proposes a feed-forward control in resonant dc link inverter. The feed-forward control configuration is based on synchronous sigma-delta modulation. The simulation results showing the proposed technique can reject non-ideal dc bus improving the total harmonic distortion.

Keywords: Feed-forward control, Resonant dc link inverter, Synchronous sigma-delta modulation.

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Authors: Tapan Trivedi, Pramod Agarwal, Rajendrasinh Jadeja, Pragnesh Bhatt

Abstract:

Space Vector Pulse Width Modulation is popular for variable frequency drives. The method has several advantages over carried based PWM and is computation intensive. The implementation of SVPWM for multilevel inverter requires special attention and at the same time consumes considerable resources. Due to faster processing power and reduced over all computational burden, FPGAs are being investigated as an alternative for other controllers. In this paper, a space vector PWM algorithm is implemented using FPGA which requires less computational area and is modular in structure. The algorithm is verified experimentally for Neutral Point Clamped inverter using FPGA development board xc3s5000-4fg900.

Keywords: Modular structure, Multilevel inverter, Space Vector PWM, Switching States.

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Authors: S. Chatterji, S. L. Shimi

Abstract:

As wind, solar and other clean and green energy sources gain popularity worldwide, engineers are seeking ways to make renewable energy systems more affordable and to integrate them with existing ac power grids. In the present paper an attempt has been made for integrating the PV arrays to the smart nano grid using an artificial intelligent (AI) based solar powered cascade multilevel inverter. The AI based controller switching scheme has been used for improving the power quality by reducing the Total Harmonic Distortion (THD) of the multi-level inverter output voltage.

Keywords: Artificial Intelligent (AI), Solar Powered Multi-level Inverter, Smart nano grid, Total Harmonic Distortion (THD).

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Authors: Abdelmonaem Ayachi, Belgacem Hamdi

Abstract:

This paper presents a fault-tolerant implementation for adder schemes using the dual duplication code. To prove the efficiency of the proposed method, the circuit is simulated in double pass transistor CMOS 32nm technology and some transient faults are voluntary injected in the Layout of the circuit. This fully differential implementation requires only 20 transistors which mean that the proposed design involves 28.57% saving in transistor count compared to standard CMOS technology.

Keywords: Semiconductors, digital electronics, double pass transistor technology, Full adder, fault tolerance.

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Authors: M.Yousefi, A.Vatanjou, F.Nazeri

Abstract:

A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here. With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to output. Designed circuit is simulated with HSPICE using level 49 parameters (BSIM 3v3) in 0.35mm standard CMOS technology. DC gain achieved is 56.7dB and Unity Gain Bandwidth (UGB) obtained is 1.15GHz. These results confirm that adding extra paths for signal can improve DC gain and UGB of folded-cascode significantly.

Keywords: OTA (Operational Transconductance Amplifier), DC gain, Unity Gain Bandwidth (UGBW)

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Authors: Najiya Omar, Hamed Aly, Timothy Little

Abstract:

The optimal size of a photovoltaic (PV) array is considered a critical factor in designing an efficient PV system due to the dependence of the PV cell performance on temperature. A high temperature can lead to voltage losses of solar panels, whereas a low temperature can cause voltage overproduction. There are two possible scenarios of the inverter’s operation in which they are associated with the erroneous calculations of the number of PV panels: 1) If the number of the panels is scant and the temperature is high, the minimum voltage required to operate the inverter will not be reached. As a result, the inverter will shut down. 2) Comparably, if the number of panels is excessive and the temperature is low, the produced voltage will be more than the maximum limit of the inverter which can cause the inverter to get disconnected or even damaged. This article aims to assess theoretical and practical methodologies to calculate size and determine the topology of a PV array. The results are validated by applying an experimental evaluation for a 100 kW Grid-connected PV system for a location in Halifax, Nova Scotia and achieving a satisfactory system performance compared to the previous work done.

Keywords: Sizing PV panels, grid-connected PV, topology of PV array, theoretical and practical methodologies.

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Authors: Nasir Mehmood, Jens Ogniewski, Vinodh Ravinath

Abstract:

This paper describes the design of a real-time audiorange digital oscilloscope and its implementation in 90nm CMOS FPGA platform. The design consists of sample and hold circuits, A/D conversion, audio and video processing, on-chip RAM, clock generation and control logic. The design of internal blocks and modules in 90nm devices in an FPGA is elaborated. Also the key features and their implementation algorithms are presented. Finally, the timing waveforms and simulation results are put forward.

Keywords: CMOS, VLSI, Oscilloscope, Field Programmable Gate Array (FPGA), VHDL, Video Graphics Array (VGA)

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Authors: R. Gunabalan, S. Immanuel Prabakaran, J. Reegan, S. Ganesh

Abstract:

This paper describes a software approach for modeling inverter fed induction motor drive using Laboratory Virtual Instrument Engineering Workbench (LabVIEW). The reason behind the selection of LabVIEW software is because of its strong graphical interface, flexibility of its programming language combined with built-in tools designed specifically for test, measurement and control. LabVIEW is generally used in most of the applications for data acquisition, test and control. In this paper, inverter and induction motor are modeled using LabVIEW toolkits. Simulation results are presented and are validated.

Keywords: Induction motor, LabVIEW, State model.

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Authors: A. Elnady

Abstract:

This paper presents an improved Direct Power Control (DPC) scheme applied to the multilevel inverter that forms a Distributed Generation Unit (DGU). This paper demonstrates the performance of active and reactive power injected by the DGU to the smart grid. The DPC is traditionally operated by the hysteresis controller with the Space Vector Modulation (SVM) which is applied on the 2-level inverters or 3-level inverters. In this paper, the DPC is operated by the PI controller with the Phase-Disposition Pulse Width Modulation (PD-PWM) applied to the 5-level diode clamped inverter. The new combination of the DPC, PI controller, PD-PWM and multilevel inverter proves that its performance is much better than the conventional hysteresis-SVM based DPC. Simulations results have been presented to validate the performance of the suggested control scheme in the grid-connected mode.

Keywords: Direct power control, PI controller, PD-PWM, and power control.

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