Search results for: circuits regimes

Authors: M.Hosseinghadiry, H. Mohammadi, M.Nadisenejani

Abstract:

with increasing circuits- complexity and demand to use portable devices, power consumption is one of the most important parameters these days. Full adders are the basic block of many circuits. Therefore reducing power consumption in full adders is very important in low power circuits. One of the most powerconsuming modules in full adders is XOR/XNOR circuit. This paper presents two new full adders based on two new logic approaches. The proposed logic approaches use one XOR or XNOR gate to implement a full adder cell. Therefore, delay and power will be decreased. Using two new approaches and two XOR and XNOR gates, two new full adders have been implemented in this paper. Simulations are carried out by HSPICE in 0.18μm bulk technology with 1.8V supply voltage. The results show that the ten-transistors proposed full adder has 12% less power consumption and is 5% faster in comparison to MB12T full adder. 9T is more efficient in area and is 24% better than similar 10T full adder in term of power consumption. The main drawback of the proposed circuits is output threshold loss problem.

Keywords: Full adder, XNOR, Low power, High performance, Very Large Scale Integrated Circuit.

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Authors: J. Hrabovský, M. Chabičovský, J. Horský

Abstract:

Water spray cooling is a technique typically used in heat treatment and other metallurgical processes where controlled temperature regimes are required. Water spray cooling is used in static (without movement) or dynamic (with movement of the steel plate) regimes. The static regime is notable for the fixed position of the hot steel plate and fixed spray nozzle. This regime is typical for quenching systems focused on heat treatment of the steel plate. The second application of spray cooling is the dynamic regime. The dynamic regime is notable for its static section cooling system and moving steel plate. This regime is used in rolling and finishing mills. The fixed position of cooling sections with nozzles and the movement of the steel plate produce nonhomogeneous water distribution on the steel plate. The length of cooling sections and placement of water nozzles in combination with the nonhomogeneity of water distribution lead to discontinued or interrupted cooling conditions. The impact of static and dynamic regimes on cooling intensity and the heat transfer coefficient during the cooling process of steel plates is an important issue. Heat treatment of steel is accompanied by oxide scale growth. The oxide scale layers can significantly modify the cooling properties and intensity during the cooling. The combination of static and dynamic (section) regimes with the variable thickness of the oxide scale layer on the steel surface impact the final cooling intensity. The study of the influence of the oxide scale layers with different cooling regimes was carried out using experimental measurements and numerical analysis. The experimental measurements compared both types of cooling regimes and the cooling of scale-free surfaces and oxidized surfaces. A numerical analysis was prepared to simulate the cooling process with different conditions of the section and samples with different oxide scale layers.

Keywords: Heat transfer coefficient, numerical analysis, oxide layer, spray cooling.

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Authors: S. Hosseini, M. Ahmadi Najafabadi, M. Akhlaghi

Abstract:

The health of the journal bearings is very important in preventing unforeseen breakdowns in rotary machines, and poor lubrication is one of the most important factors for producing the bearing failures. Hydrodynamic lubrication (HL), mixed lubrication (ML), and boundary lubrication (BL) are three regimes of a journal bearing lubrication. This paper uses acoustic emission (AE) measurement technique to correlate features of the AE signals to the three lubrication regimes. The transitions from HL to ML based on operating factors such as rotating speed, load, inlet oil pressure by time domain and time-frequency domain signal analysis techniques are detected, and then metal-to-metal contacts between sliding surfaces of the journal and bearing are identified. It is found that there is a significant difference between theoretical and experimental operating values that are obtained for defining the lubrication regions.

Keywords: Acoustic emission technique, pressure fed journal bearing, time and frequency signal analysis, metal-to-metal contact.

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Authors: A.Khaja Kamaluddin, B.Muhammed Yousoof

Abstract:

Routing places an important role in determining the quality of service in wireless networks. The routing methods adopted in wireless networks have many drawbacks. This paper aims to review the current routing methods used in wireless networks. This paper proposes an innovative solution to overcome the problems in routing. This solution is aimed at improving the Quality of Service. This solution is different from others as it involves the resuage of the part of the virtual circuits. This improvement in quality of service is important especially in propagation of multimedia applications like video, animations etc. So it is the dire need to propose a new solution to improve the quality of service in ATM wireless networks for multimedia applications especially during this era of multimedia based applications.

Keywords: Packet buffering, Routing Table, Virtual Circuits (VC)

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Authors: Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj

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Minimizations of power dissipation, chip area with higher circuit performance are the necessary and key parameters in deep submicron regime. The leakage current increases sharply in deep submicron regime and directly affected the power dissipation of the logic circuits. In deep submicron region the power dissipation as well as high performance is the crucial concern since increasing importance of portable systems. Number of leakage reduction techniques employed to reduce the leakage current in deep submicron region but they have some trade-off to control the leakage current. ONOFIC approach gives an excellent agreement between power dissipation and propagation delay for designing the efficient CMOS logic circuits. In this article ONOFIC approach is compared with LECTOR technique and output results show that ONOFIC approach significantly reduces the power dissipation and enhance the speed of the logic circuits. The lower power delay product is the big outcome of this approach and makes it an influential leakage reduction technique.

Keywords: Deep submicron, Leakage Current, LECTOR, ONOFIC, Power Delay Product

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Authors: Traian Chiulan, Brandusa Pantelimon

Abstract:

The paper analyzes the large power transformer unit regimes, indicating the criteria for the management of the voltage operating conditions, as well as the change in the operating conditions with the load connected to the secondary winding of the transformer unit. Further, the paper presents the software application for the evaluation of the transformer unit operation under different conditions. The software application was developed by means of virtual instrumentation.

Keywords: Operating regimes, power transformer, overload, lifetime, virtual instrumentation.

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand Tan Kong Yew

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This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), and ion sensor electronics.

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Authors: Yuzman Yusoff, Siti Noor Harun, Noor Shelida Sallehand, Tan Kong Yew

Abstract:

This paper presents the design and characterization of analog readout interface circuits for ion sensitive field effect transistor (ISFET) and ion selective electrode (ISE) based sensor. These interface circuits are implemented using MIMOS’s 0.35um CMOS technology and experimentally characterized under 24-leads QFN package. The characterization evaluates the circuit’s functionality, output sensitivity and output linearity. Commercial sensors for both ISFET and ISE are employed together with glass reference electrode during testing. The test result shows that the designed interface circuits manage to readout signals produced by both sensors with measured sensitivity of ISFET and ISE sensor are 54mV/pH and 62mV/decade, respectively. The characterized output linearity for both circuits achieves above 0.999 Rsquare. The readout also has demonstrated reliable operation by passing all qualifications in reliability test plan.

Keywords: Readout interface circuit (ROIC), analog interface circuit, ion sensitive field effect transistor (ISFET), ion selective electrode (ISE), ion sensor electronics.

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Authors: Yngvar Berg, Mehdi Azadmehr

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In this paper we present a linear autozeroing ultra lowvoltage amplifier. The autozeroing performed by all ULV circuits is important to reduce the impact of noise and especially avoid power supply noise in mixed signal low-voltage CMOS circuits. The simulated data presented is relevant for a 90nm TSMC CMOS process.

Keywords: Low-voltage, trans conductance amplifier, linearity, floating-gate.

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Authors: Artem Nuriev, Olga Zaitseva

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This paper is devoted to the study of a viscous incompressible flow around a circular cylinder performing harmonic oscillations, especially the steady streaming phenomenon. The research methodology is based on the asymptotic explanation method combined with the computational bifurcation analysis. The research approach develops Schlichting and Wang decomposition method. Present studies allow to identify several regimes of the secondary streaming with different flow structures. The results of the research are in good agreement with experimental and numerical simulation data.

Keywords: Oscillating cylinder, Secondary Streaming, Flow Regimes, Asymptotic and Bifurcation Analysis.

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Authors: E. Farshidi

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This paper presents a new general technique for analysis of noise in static log-domain translinear circuits. It is demonstrated that employing this technique, leads to a general, simple and routine method of the noise analysis. The circuit has been simulated by HSPICE. The simulation results are seen to conform to the theoretical analysis and shows benefits of the proposed circuit.

Keywords: Noise analysis, log-domain, static, dynamic, translinear loop, companding.

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Authors: Shashank Gautam, Pramod Sharma

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In present era, development of digital circuits, signal processors and other integrated circuits, magnitude comparators are challenged by large area and more power consumption. Comparator is most basic circuit that performs comparison. This paper presents a technique to design a two bit comparator which consumes less area and power. DSCH and MICROWIND version 3 are used to design the schematic and design the layout of the schematic, observe the performance parameters at different nanometer technologies respectively.

Keywords: Chip design, consumed power, layout area, two bit comparator.

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Authors: F. J. Sowiński, M. Dziubiński

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In the study the influence of the physical-chemical properties of a liquid, the width of a channel gap and the superficial liquid and gas velocities on the patterns formed during two phase flows in vertical, narrow mini-channels was investigated. The research was performed in the channels of rectangular cross-section and of dimensions: 15 x 0.65 mm and 7.5 x 0.73 mm. The experimental data were compared with the published criteria of the transitions between the patterns of two-phase flows.

Keywords: Two-phase flow, flow regimes, mini-channel, viscosity.

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Authors: Anna Romanova, Mojtaba Mahmoodian, Upul Chandrasekara, Morteza A. Alani

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Corrosion of concrete sewer pipes induced by sulphuric acid attack is a recognised problem worldwide, which is not only an attribute of countries with hot climate conditions as thought before. The significance of this problem is by far only realised when the pipe collapses causing surface flooding and other severe consequences. To change the existing post-reactive attitude of managing companies, easy to use and robust models are required to be developed which currently lack reliable data to be correctly calibrated. This paper focuses on laboratory experiments of establishing concrete pipe corrosion rate by submerging samples in to 0.5pH sulphuric acid solution for 56 days under 10ºC, 20ºC and 30ºC temperature regimes. The result showed that at very early stage of the corrosion process the samples gained overall mass, at 30ºC the corrosion progressed quicker than for other temperature regimes, however with time the corrosion level for 10ºC and 20ºC regimes tended towards those at 30ºC. Overall, at these conditions the corrosion rates of 10 mm/year, 13,5 mm/year and 17 mm/year were observed.

Keywords: Sewer pipes, concrete corrosion, sulphuric acid, concrete coupons, corrosion rate.

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Authors: G.Ramana Murthy, C.Senthilpari, P.Velrajkumar, Lim Tien Sze

Abstract:

The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other existing six adder circuits in terms of power, propagation delay and PDP. The proposed adder circuit is further analyzed for interconnect analysis, which gives better performance than other adder circuits in terms of layout thickness, width and height.

Keywords: Full Adder, Interconnect Analysis, Low-Power, Multiplexer, Propagation Delay, Parametric Analysis.

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Authors: Atefeh Bagherianziarat, Dana Hamplova

Abstract:

The inverse social gradient in life satisfaction (LS) is a well-established research finding. Although objective aspects of inequality or individuals’ socioeconomic status are among the approved predictors of life satisfaction; however, less is known about the effect of subjective inequality and the interplay of these two aspects of inequality on life satisfaction. It is suggested that individuals’ perception of their socioeconomic status in society can moderate the link between their absolute socioeconomic status and life satisfaction. Nevertheless, this moderating link has not been affirmed to work likewise in societies with different welfare regimes associating with different levels of social inequality. In this study, we compared the moderative influence of subjective inequality on the link between objective inequality and LS. In particular, we focus on differences across welfare state regimes based on Esping-Andersen's theory. Also, we explored the moderative role of believing in the value of equality on the link between objective and subjective inequality on LS, in the given societies. Since our studied variables were measured at both individual and country levels, we applied a multilevel analysis to the European Social Survey data (round 9). The results showed that people in different regimes reported statistically meaningful different levels of LS that is explained to different extends by their household income and their perception of their income inequality. The findings of the study supported the previous findings of the moderator influence of perceived inequality on the link between objective inequality and LS. However, this link is different in various welfare state regimes. The results of the multilevel modeling showed that country-level subjective equality is a positive predictor for individuals’ LS, while the Gini coefficient that was considered as the indicator of absolute inequality has a smaller effect on LS. Also, country-level subjective equality moderates the confirmed link between individuals’ income and their LS. It can be concluded that both individual and country-level subjective inequality slightly moderate the effect of individuals’ income on their LS.

Keywords: individual values, life satisfaction, multi-level analysis, objective inequality, subjective inequality, welfare regimes status

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Authors: Oluseun S. Oyelakin, Olalekan W. Olaniyi

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A field experiment was conducted at Ido town in Ido Local Government Area of Oyo state, Nigeria to determine the effects of intercropping maize (Zea mays L.) with Jack bean (Canavalia ensiformis L.) at different spacing and weeding regimes on crops productivity. The treatments were 2 x 2 x 3 factorial arrangement involving two spatial crop arrangements. Spacing of 75 cm x 50 cm and 90 cm x 42 cm (41.667 cm) with two plants per stand resulted in plant population of approximately 53,000 plants/hectare. Also, Randomized Complete Block Design (RCBD) with two cropping patterns (sole and intercrop), three weeding regimes (weedy check, weeds once, and weed twice) with three replicates was used. Data were analyzed with SAS (Statistical Analysis System) and statistical means separated using Least Significant Difference (LSD) (P ≤ 0.05). Intercropping and crop spacing did not have significant influence on the growth parameters and yield parameters. The maize grain yield of 1.11 t/ha obtained under sole maize was comparable to 1.05 t/ha from maize/jack beans. Weeding regime significantly influenced growth and yields of maize in intercropping with Jack beans. Weeding twice resulted in significantly higher growth than that of the other weeding regimes. Plant height at 6 Weeks After Sowing (WAS) under weeding twice regime (3 and 6 WAS) was 83.9 cm which was significantly different from 67.75 cm and 53.47 cm for weeding once (3 WAS) and no weeding regimes respectively. Moreover, maize grain yield of 1.3 t/ha obtained from plots weeded twice was comparable to that of 1.23 t/ha from single weeding and both were significantly higher than 0.71 t/ha maize grain yield obtained from the no weeding control. The dry matter production of Jack beans reduced at some growth stages due to intercropping of maize with Jack beans though with no significance effect on the other growth parameters of the crop. There was no effect on the growth parameters of Jack beans in maize/jack beans intercrop based on cropping spacing while comparable growth and dry matter production in Jack beans were produced in maize/Jack beans mixture with single weeding.

Keywords: Crop spacing, intercropping, growth parameter, weeding regime, sole cropping, week after sowing.

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Authors: Yang Luo, Beibei Wang

Abstract:

In this paper, we present a design methodology of lightweight register transfer level (RTL) hardware threat implemented based on a MAX II FPGA platform. The dynamic power consumed by the toggling of the various bit of registers as well as the dynamic power consumed per unit of logic circuits were analyzed. The hardware threat was designed taking advantage of the differences in dynamic power consumed per unit of logic circuits to hide the transfer information. The experiment result shows that the register hardware threat was successfully implemented by using different dynamic power consumed per unit of logic circuits to hide the key information of DES encryption module. It needs more than 100000 sample curves to reduce the background noise by comparing the sample space when it completely meets the time alignment requirement. In additional, an external trigger signal is playing a very important role to detect the hardware threat in this experiment.

Keywords: Side-channel analysis, hardware threat, register transfer level, dynamic power.

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Authors: Ivan Lovrinović, Gordana Kordić, Martina Nakić

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There are little subjects in macroeconomics that are so widely discussed, but at the same time controversial and without a clear solution such as the choice of exchange rate regime. National authorities need to take into consideration numerous fundamentals, trying to fulfil goals of economic growth, low and stable inflation and international stability. This paper focuses on the countries of ex- Yugoslavia and their exchange rate history as independent states. We follow the development of the regimes in 6 countries during the transition through the financial crisis of the second part of the 2000s to the prospects of their final goal: full membership in the European Union. Main question is to what extent has the exchange regime contributed to their economic success, considering other objective factors.

Keywords: European Union, exchange rate regime, ex- Yugoslavia countries

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Authors: Majid Reza Naseh, Mohammad Haeri

Abstract:

This paper introduces an adaptive control scheme to synchronize two identical Chua's systems. Introductory part of the paper is presented in the first part of the paper and then in the second part, a new theorem is proposed based on which an adaptive control scheme is developed to synchronize two identical modified Chua's circuit. Finally, numerical simulations are included to verify the effectiveness of the proposed control method.

Keywords: Chaos synchronization, adaptive control, Chua's circuits.

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Authors: Wenji Zhu, Yigang He

Abstract:

This paper presents a new method of analog fault diagnosis based on back-propagation neural networks (BPNNs) using wavelet decomposition and fractal dimension as preprocessors. The proposed method has the capability to detect and identify faulty components in an analog electronic circuit with tolerance by analyzing its impulse response. Using wavelet decomposition to preprocess the impulse response drastically de-noises the inputs to the neural network. The second preprocessing by fractal dimension can extract unique features, which are the fed to a neural network as inputs for further classification. A comparison of our work with [1] and [6], which also employs back-propagation (BP) neural networks, reveals that our system requires a much smaller network and performs significantly better in fault diagnosis of analog circuits due to our proposed preprocessing techniques.

Keywords: Analog circuits, fault diagnosis, tolerance, wavelettransform, fractal dimension, box dimension.

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Authors: Alexandr A. Penin

Abstract:

Application of projective geometry to the theory of two-ports and cascade circuits with a load change is considered. The equations linking the input and output of a two-port are interpreted as projective transformations which have the invariant as a cross-ratio of four points. This invariant has place for all regime parameters in all parts of a cascade circuit. This approach allows justifying the definition of a regime and its change, to calculate a circuit without explicitly finding the aparameters, to transmit accurately an analogue signal through the unstable two-port.

Keywords: Circuit regime, geometric circuit theory, projective geometry, two-port.

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Authors: Paulo S. Caparelli, Eduardo Costa, Alexsandro S. Soares, Hipolito Barbosa

Abstract:

This paper presents an evolutionary method for designing electronic circuits and numerical methods associated with monitoring systems. The instruments described here have been used in studies of weather and climate changes due to global warming, and also in medical patient supervision. Genetic Programming systems have been used both for designing circuits and sensors, and also for determining sensor parameters. The authors advance the thesis that the software side of such a system should be written in computer languages with a strong mathematical and logic background in order to prevent software obsolescence, and achieve program correctness.

Keywords: Pattern recognition, evolutionary computation, biological signal, functional programming.

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Authors: Pradeep Bhagawath, K.N. Prabhu, Satyanarayan

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Wetting characteristics of reactive (Sn–0.7Cu solder) and non– reactive (castor oil) wetting of liquids on Cu and Ag plated Al substrates have been investigated. Solder spreading exhibited capillary, gravity and viscous regimes. Oils did not exhibit noticeable spreading regimes. Solder alloy showed better wettability on Ag coated Al substrate compared to Cu plating. In the case of castor oil, Cu coated Al substrate exhibited good wettability as compared to Ag coated Al substrates. The difference in wettability during reactive wetting of solder and non–reactive wetting of oils is attributed to the change in the surface energies of Al substrates brought about by the formation of intermetallic compounds (IMCs).

Keywords: Wettability, contact angle, solder, castor oil, IMCs.

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Authors: Emanuele Stomeo, Tatiana Kalganova, Cyrille Lambert

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Evolvable hardware (EHW) refers to a selfreconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). A lot of research has been done in this area several different EA have been introduced. Every time a specific EA is chosen for solving a particular problem, all its components, such as population size, initialization, selection mechanism, mutation rate, and genetic operators, should be selected in order to achieve the best results. In the last three decade a lot of research has been carried out in order to identify the best parameters for the EA-s components for different “test-problems". However different researchers propose different solutions. In this paper the behaviour of mutation rate on (1+λ) evolution strategy (ES) for designing logic circuits, which has not been done before, has been deeply analyzed. The mutation rate for an EHW system modifies values of the logic cell inputs, the cell type (for example from AND to NOR) and the circuit output. The behaviour of the mutation has been analyzed based on the number of generations, genotype redundancy and number of logic gates used for the evolved circuits. The experimental results found provide the behaviour of the mutation rate to be used during evolution for the design and optimization of logic circuits. The researches on the best mutation rate during the last 40 years are also summarized.

Keywords: Evolvable hardware, mutation rate, evolutionarycomputation, design of logic circuit.

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Authors: Zdeňka Dostálová, David Matoušek, Bohumil Brtnik

Abstract:

As there are also graph methods of circuit analysis in addition to algebraic methods, it is, in theory, clearly possible to carry out an analysis of a whole switched circuit in two-phase switching exclusively by the graph method as well. This article deals with two methods of full-graph solving of switched circuits: by transformation graphs and by two-graphs. It deals with the circuit switched capacitors and the switched current, too. All methods are presented in an equally detailed steps to be able to compare.

Keywords: Switched capacitors of two phases, switched currents of two phases, transformation graph, two-graph, Mason's formula, voltage transfer, summary graph.

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Authors: Jianping Hu, Xiaolei Sheng

Abstract:

This paper introduces an adiabatic register file based on two-phase CPAL (Complementary Pass-Transistor Adiabatic Logic circuits) with power-gating scheme, which can operate on a single-phase power clock. A 32×32 single-phase adiabatic register file with power-gating scheme has been implemented with TSMC 0.18μm CMOS technology. All the circuits except for the storage cells employ two-phase CPAL circuits, and the storage cell is based on the conventional memory one. The two-phase non-overlap power-clock generator with power-gating scheme is used to supply the proposed adiabatic register file. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. Compared with the traditional static CMOS register file, HSPICE simulations show that the proposed adiabatic register file can work very well, and it attains about 73% energy savings at 100 MHz.

Keywords: Low power, Register file, Complementarypass-transistor logic, Adiabatic logic, Single-phase power clock.

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Authors: Gilberto Gonzalez-A, Dunia Nuñez-P

Abstract:

Bond graph models of an electrical transformer including the nonlinear saturation are presented. The transformer using electrical and magnetic circuits are modelled. These models determine the relation between self and mutual inductances, and the leakage and magnetizing inductances of power transformers with two windings using the properties of a bond graph. The equivalence between electrical and magnetic variables is given. The modelling and analysis using this methodology to three phase power transformers can be extended.

Keywords: Bond graph, electrical transformer, magnetic circuits, nonlinear saturation.

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Authors: Ebrahim Farshidi

Abstract:

This paper presents a new circuit arrangement for a current-mode Wheatstone bridge that is suitable for low-voltage integrated circuits implementation. Compared to the other proposed circuits, this circuit features severe reduction of the elements number, low supply voltage (1V) and low power consumption (<350uW). In addition, the circuit has favorable nonlinearity error (<0.35%), operate with multiple sensors and works by single supply voltage. The circuit employs MOSFET transistors, so it can be used for standard CMOS fabrication. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

Keywords: Wheatstone bridge, current-mode, low-voltage, MOS.

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Authors: D. Krishnaveni, M. Geetha Priya

Abstract:

Application of reversible logic in integrated circuits results in the improved optimization of power consumption. This technology can be put into use in a variety of low power applications such as quantum computing, optical computing, nano-technology, and Complementary Metal Oxide Semiconductor (CMOS) Very Large Scale Integrated (VLSI) design etc. Logic gates are the basic building blocks in the design of any logic network and thus integrated circuits. In this paper, reversible Dual Key Gate (DKG) and Dual key Gate Pair (DKGP) gates that work singly as full adder/full subtractor are used to realize the basic building blocks of logic circuits. Reversible full adder/subtractor and parallel adder/ subtractor are designed using other reversible gates available in the literature and compared with that of DKG & DKGP gates. Efficient performance of reversible logic circuits relies on the optimization of the key parameters viz number of constant inputs, garbage outputs and number of reversible gates. The full adder/subtractor and parallel adder/subtractor design with reversible DKGP and DKG gates results in least number of constant inputs, garbage outputs, and number of reversible gates compared to the other designs. Thus, this paper provides a threshold to build more complex arithmetic systems using these reversible logic gates, leading to the enhanced performance of computing systems.

Keywords: Low power CMOS, quantum computing, reversible logic gates, full adder, full subtractor, parallel adder/subtractor, basic gates, universal gates.

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