Search results for: SPICE Model.

Authors: A. Braeken, L. Sterckx, A. Touhafi, Y. Verbelen

Abstract:

When studying electronics, hands-on experience is considered to be very valuable for a better understanding of the concepts of electricity and electronics. Students lacking sufficient time in the lab are often put at disadvantage. A way to overcome this, is by using interactive multimedia in a virtual environment. Instead of proposing another new ad-hoc simulator for e-learning, we propose in this paper an e-learning platform integrating the SPICE simulator as a web service. This enables to make use of all the functions of the de-facto standard simulator SPICE inelectronics when developing new simulations.

Keywords: E-learning, SPICE, virtual experiments, web service.

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Authors: É. Kónya, E. Szabó, I. Bata-Vidács, T. Deák, M. Ottucsák, N. Adányi, A. Székács

Abstract:

Spice paprika is a major spice commodity in the European Union (EU), produced locally and imported from non-EU countries, reported not only for chemical and microbiological contamination, but also for fraud. The effective interaction between producers’ quality management practices and government and EU activities is described on the example of spice paprika production and control in Hungary, a country of leading spice paprika producer and per capita consumer in Europe. To demonstrate the importance of various contamination factors in the Hungarian production and EU trade of spice paprika, several aspects concerning food safety of this commodity are presented. Alerts in the Rapid Alert System for Food and Feed (RASFF) of the EU between 2005 and 2013, as well as Hungarian state inspection results on spice paprika in 2004 are discussed, and quality non-compliance claims regarding spice paprika among EU member states are summarized in by means of network analysis. Quality assurance measures established along the spice paprika production technology chain at the leading Hungarian spice paprika manufacturer, Kalocsai Fűszerpaprika Zrt. are surveyed with main critical control points identified. The structure and operation of the Hungarian state food safety inspection system is described. Concerted performance of the latter two quality management systems illustrates the effective interaction between internal (manufacturer) and external (state) quality control measures.

Keywords: Spice paprika, quality control, reporting mechanisms, RASFF, vulnerable points, HACCP, BRC Global Standard.

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Authors: A. Lakrim, D. Tahri

Abstract:

This paper sets out a behavioral macro-model of a Merged PiN and Schottky (MPS) diode based on silicon carbide (SiC). This model holds good for both static and dynamic electrothermal simulations for industrial applications. Its parameters have been worked out from datasheets curves by drawing on the optimization method: Simulated Annealing (SA) for the SiC MPS diodes made available in the industry. The model also adopts the Analog Behavioral Model (ABM) of PSPICE in which it has been implemented. The thermal behavior of the devices was also taken into consideration by making use of Foster’ canonical network as figured out from electro-thermal measurement provided by the manufacturer of the device.

Keywords: SiC MPS Diode, electro-thermal, SPICE Model.

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Authors: Sz. Klátyik, B. Darvas, M. Mörtl, M. Ottucsák, E. Takács, H. Bánáti, L. Simon, G. Gyurcsó, A. Székács

Abstract:

Environmental and health safety of condiments used for spicing food products in food processing or by culinary means receive relatively low attention, even though possible contamination of spices may affect food quality and safety. Contamination surveys mostly focus on microbial contaminants or their secondary metabolites, mycotoxins. Chemical contaminants, particularly pesticide residues, however, are clearly substantial factors in the case of given condiments in the Capsicum family including spice paprika and chilli. To assess food safety and support the quality of the Hungaricum product spice paprika, the pesticide residue status of spice paprika and chilli is assessed on the basis of reported pesticide contamination cases and non-compliances in the Rapid Alert System for Food and Feed of the European Union since 1998.

Keywords: Spice paprika, Capsicum, pesticide residues, RASFF.

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Authors: Dipankar Dhabak, Soumya Pandit

Abstract:

This paper presents an adaptive technique for generation of data required for construction of artificial neural network-based performance model of nano-scale CMOS inverter circuit. The training data are generated from the samples through SPICE simulation. The proposed algorithm has been compared to standard progressive sampling algorithms like arithmetic sampling and geometric sampling. The advantages of the present approach over the others have been demonstrated. The ANN predicted results have been compared with actual SPICE results. A very good accuracy has been obtained.

Keywords: CMOS Inverter, Nano-scale, Adaptive Sampling, ArtificialNeural Network

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Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

Abstract:

Fast delay estimation methods, as opposed to simulation techniques, are needed for incremental performance driven layout synthesis. On-chip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed and circuit complexity. Inductance causes noise in signal waveforms, which can adversely affect the performance of the circuit and signal integrity. Several approaches have been put forward which consider the inductance for on-chip interconnect modelling. But for even much higher frequency, of the order of few GHz, the shunt dielectric lossy component has become comparable to that of other electrical parameters for high speed VLSI design. In order to cope up with this effect, on-chip interconnect has to be modelled as distributed RLCG line. Elmore delay based methods, although efficient, cannot accurately estimate the delay for RLCG interconnect line. In this paper, an accurate analytical delay model has been derived, based on first and second moments of RLCG interconnection lines. The proposed model considers both the effect of inductance and conductance matrices. We have performed the simulation in 0.18μm technology node and an error of as low as less as 5% has been achieved with the proposed model when compared to SPICE. The importance of the conductance matrices in interconnect modelling has also been discussed and it is shown that if G is neglected for interconnect line modelling, then it will result an delay error of as high as 6% when compared to SPICE.

Keywords: Delay Modelling; On-Chip Interconnect; RLCGInterconnect; Ramp Input; Damping; VLSI

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Authors: M.J. Sharifi

Abstract:

Several models have been introduced so far for single electron box, SEB, which all of them were restricted to DC response and or low temperature limit. In this paper we introduce a new time dependent, high temperature analytical model for SEB for the first time. DC behavior of the introduced model will be verified against SIMON software and its time behavior will be verified against a newly published paper regarding step response of SEB.

Keywords: Single electron box, SPICE, SIMON, Timedependent, Circuit model.

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Authors: Rishikesh Pandey, Maneesha Gupta

Abstract:

A new low-voltage floating gate MOSFET (FGMOS) based squarer using square law characteristic of the FGMOS is proposed in this paper. The major advantages of the squarer are simplicity, rail-to-rail input dynamic range, low total harmonic distortion, and low power consumption. The proposed circuit is biased without body effect. The circuit is designed and simulated using SPICE in 0.25μm CMOS technology. The squarer is operated at the supply voltages of ±0.75V . The total harmonic distortion (THD) for the input signal 0.75Vpp at 25 KHz, and maximum power consumption were found to be less than 1% and 319μW respectively.

Keywords: Analog signal processing, floating gate MOSFETs, low-voltage, Spice, squarer.

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Authors: Hassan Jassim Motlak

Abstract:

A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to the symmetrical input stage. P-Spice simulation results are obtained using 0.18μm MIETEC CMOS process parameters and supply voltage of ±1.2V, 50μA biasing current. The p-spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, openloop gain bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/μS, THD of -63dB and DC consumption power (PC) of 2mW.

Keywords: Pseudo-OTA used CMOS CFOA, low power CFOA, high-performance CFOA, novel CFOA.

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Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

Abstract:

The resistive-inductive-capacitive behavior of long interconnects which are driven by CMOS gates are presented in this paper. The analysis is based on the ¤Ç-model of a RLC load and is developed for submicron devices. Accurate and analytical expressions for the output load voltage, the propagation delay and the short circuit power dissipation have been proposed after solving a system of differential equations which accurately describe the behavior of the circuit. The effect of coupling capacitance between input and output and the short circuit current on these performance parameters are also incorporated in the proposed model. The estimated proposed delay and short circuit power dissipation are in very good agreement with the SPICE simulation with average relative error less than 6%.

Keywords: Delay, Inverter, Short Circuit Power, ¤Ç-Model, RLCInterconnect, VLSI

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Authors: Z. Feng, V. Viswanathan, D. Navarro, I. O'Connor

Abstract:

This paper presents a new high speed simulation methodology to solve the long simulation time problem of CMOS image sensor matrix. Generally, for integrating the pixel matrix in SOC and simulating the system performance, designers try to model the pixel in various modeling languages such as VHDL-AMS, SystemC or Matlab. We introduce a new alternative method based on spice model in cadence design platform to achieve accuracy and reduce simulation time. The simulation results indicate that the pixel output voltage maximum error is at 0.7812% and time consumption reduces from 2.2 days to 13 minutes achieving about 240X speed-up for the 256x256 pixel matrix.

Keywords: CMOS image sensor, high speed simulation, image sensor matrix simulation.

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Authors: Abdelghafour Galadi

Abstract:

In this paper, accurate power MOSFET models including quasi-saturation effect are presented. These models have no internal node voltages determined by the circuit simulator and use one JFET or one depletion mode MOSFET transistors controlled by an “effective” gate voltage taking into account the quasi-saturation effect. The proposed models achieve accurate simulation results with an average error percentage less than 9%, which is an improvement of 21 percentage points compared to the commonly used standard power MOSFET model. In addition, the models can be integrated in any available commercial circuit simulators by using their analytical equations. A description of the models will be provided along with the parameter extraction procedure.

Keywords: Power MOSFET, drift layer, quasi-saturation effect, SPICE model, circuit simulation.

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Authors: V. T. S. Dao, T. G. Etoh, C. Vo Le, H. D. Nguyen, K. Takehara, T. Akino, K. Nishi

Abstract:

We present an explicit expression to estimate driving voltage attenuation through RC networks representation of an ultrahigh- speed image sensor. Elmore delay metric for a fundamental RC chain is employed as the first-order approximation. By application of dimensional analysis to SPICE simulation data, we found a simple expression that significantly improves the accuracy of the approximation. Estimation error of the resultant expression for uniform RC networks is less than 2%. Similarly, another simple closed-form model to estimate 50 % delay through fundamental RC networks is also derived with sufficient accuracy. The framework of this analysis can be extended to address delay or attenuation issues of other VLSI structures.

Keywords: Dimensional Analysis, Elmore model, RC network, Signal Attenuation, Ultra-High-Speed Image Sensor.

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Authors: Andrés Gomez-Casseres, Rubén Contreras

Abstract:

In this paper, a bidirectional boost converter operated in Discontinuous Conduction Mode (DCM) is presented as a suitable power conditioning circuit for tuning of kinetic energy harvesters without the need of a battery. A nonlinear control scheme, composed by two linear controllers, is used to control the average value of the input current, enabling the synthesization of complex loads. The converter, along with the control system, is validated through SPICE simulations using the LTspice tool. The converter model and the controller transfer functions are derived. From the simulation results, it was found that the input current distortion increases with the introduced phase shift and that, such distortion, is almost entirely present at the zero-crossing point of the input voltage.

Keywords: Average current control, boost converter, electrical tuning, energy harvesting.

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Authors: A.R. Aswatha, T. Basavaraju, S. Sandeep Kumar

Abstract:

Timing driven physical design, synthesis, and optimization tools need efficient closed-form delay models for estimating the delay associated with each net in an integrated circuit (IC) design. The total number of nets in a modern IC design has increased dramatically and exceeded millions. Therefore efficient modeling of interconnection is needed for high speed IC-s. This paper presents closed–form expressions for RC and RLC interconnection trees in current mode signaling, which can be implemented in VLSI design tool. These analytical model expressions can be used for accurate calculation of delay after the design clock tree has been laid out and the design is fully routed. Evaluation of these analytical models is several orders of magnitude faster than simulation using SPICE.

Keywords: IC design, RC/RLC Interconnection, VLSI Systems.

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Authors: Jasdeep Kaur, Nupur Prakash, S. S. Rajput

Abstract:

A current mirror (CM) based on self cascode MOSFETs low voltage analog and mixed mode structures has been proposed. The proposed CM has high output impedance and can operate at 0.5 V. P-Spice simulations confirm the high performance of this CM with a bandwidth of 6.0 GHz at input current of 100 μA.

Keywords: Current Mirrors, Composite Cascode Structure, Current Source/Sink

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Authors: Dalibor Biolek, Viera Biolková, Zden─øk Kolka

Abstract:

A universal current-mode biquad is described which represents an economical variant of well-known KHN (Kerwin, Huelsman, Newcomb) voltage-mode filter. The circuit consists of two multiple-output OTAs and of two grounded capacitors. Utilizing simple splitter of the input current and a pair of jumpers, all the basic 2nd-order transfer functions can be implemented. The principle is verified by Spice simulation on the level of a CMOS structure of OTAs.

Keywords: Biquad, current mode, OTA.

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Authors: Saad Mutashar Abbas, M. A. Hannan, S. A. Samad, A. Hussain

Abstract:

This paper presented a proposed design for transcutaneous inductive powering links. The design used to transfer power and data to the implanted devices such as implanted Microsystems to stimulate and monitoring the nerves and muscles. The system operated with low band frequency 13.56 MHZ according to industrial- scientific – medical (ISM) band to avoid the tissue heating. For external part, the modulation index is 13 % and the modulation rate 7.3% with data rate 1 Mbit/s assuming Tbit=1us. The system has been designed using 0.35-μm fabricated CMOS technology. The mathematical model is given and the design is simulated using OrCAD P Spice 16.2 software tool and for real-time simulation the electronic workbench MULISIM 11 has been used. The novel circular plane (pancake) coils was simulated using ANSOFT- HFss software.

Keywords: Implanted devices, ASK techniques, Class-E power amplifier, Inductive powering and low-frequency ISM band.

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Authors: S. M. Abbas, M. A. Hannan, S. A. Samad, A. Hussain

Abstract:

This paper presented a modified efficient inductive powering link based on ASK modulator and proposed efficient class- E power amplifier. The design presents the external part which is located outside the body to transfer power and data to the implanted devices such as implanted Microsystems to stimulate and monitoring the nerves and muscles. The system operated with low band frequency 10MHZ according to industrial- scientific – medical (ISM) band to avoid the tissue heating. For external part, the modulation index is 11.1% and the modulation rate 7.2% with data rate 1 Mbit/s assuming Tbit = 1us. The system has been designed using 0.35-μm fabricated CMOS technology. The mathematical model is given and the design is simulated using OrCAD P Spice 16.2 software tool and for real-time simulation, the electronic workbench MULISIM 11 has been used.

Keywords: Implanted devices, ASK techniques, Class-E power amplifier, Inductive powering and low-frequency ISM band.

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Authors: V. T. S. Dao, T. G. Etoh, C. Vo Le, H. D. Nguyen, K. Takehara, T. Akino, K. Nishi

Abstract:

Since 2004, we have been developing an in-situ storage image sensor (ISIS) that captures more than 100 consecutive images at a frame rate of 10 Mfps with ultra-high sensitivity as well as the video camera for use with this ISIS. Currently, basic research is continuing in an attempt to increase the frame rate up to 100 Mfps and above. In order to suppress electro-magnetic noise at such high frequency, a digital-noiseless imaging transfer scheme has been developed utilizing solely sinusoidal driving voltages. This paper presents highly efficient-yet-accurate expressions to estimate attenuation as well as phase delay of driving voltages through RC networks of an ultra-high-speed image sensor. Elmore metric for a fundamental RC chain is employed as the first-order approximation. By application of dimensional analysis to SPICE data, we found a simple expression that significantly improves the accuracy of the approximation. Similarly, another simple closed-form model to estimate phase delay through fundamental RC networks is also obtained. Estimation error of both expressions is much less than previous works, only less 2% for most of the cases . The framework of this analysis can be extended to address similar issues of other VLSI structures.

Keywords: Dimensional Analysis, ISIS, Digital-noiseless, RC network, Attenuation, Phase Delay, Elmore model

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Authors: Susmita Sahoo, Madhumanti Datta, Rajib Kar

Abstract:

This work proposes an accurate crosstalk noise estimation method in the presence of multiple RLC lines for the use in design automation tools. This method correctly models the loading effects of non switching aggressors and aggressor tree branches using resistive shielding effect and realistic exponential input waveforms. Noise peak and width expressions have been derived. The results obtained are at good agreement with SPICE results. Results show that average error for noise peak is 4.7% and for the width is 6.15% while allowing a very fast analysis.

Keywords: Crosstalk, distributed RLC segments, On-Chip interconnect, output response, VLSI, noise peak, noise width.

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Authors: Young Wook Lee, Sun-Jae Kim, Soo-Yeon Lee, Moon-Kyu Song, Woo-Geun Lee Min-Koo Han

Abstract:

We have fabricated a-IGZO TFT and investigated the stability under positive DC and AC bias stress. The threshold voltage of a-IGZO TFT shifts positively under those biases, and that reduces on-current. For this reason, conventional shift-register circuit employing TFTs which stressed by positive bias will be unstable, may do not work properly. We have designed a new 6-transistor shift-register, which has less transistors than prior circuits. The TFTs of the proposed shift-register are not suffering from positive DC or AC stress, mainly kept unbiased. Despite the compact design, the stable output signal was verified through the SPICE simulation even under RC delay of clock signal.

Keywords: Indium Gallium Zinc Oxide (IGZO), Thin FilmTransistor (TFT), shift-register

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Authors: Azza M. Anis, M. M. Abutaleb, Hani F. Ragai, M. I. Eladawy

Abstract:

This paper presents the characterization and design of a capacitive pressure sensor with LC-based 0.35 µm CMOS readout circuit. SPICE is employed to evaluate the characteristics of the readout circuit and COMSOL multiphysics structural analysis is used to simulate the behavior of the pressure sensor. The readout circuit converts the capacitance variation of the pressure sensor into the frequency output. Simulation results show that the proposed pressure sensor has output frequency from 2.50 to 2.28 GHz in a pressure range from 0.1 to 2 MPa almost linearly. The sensitivity of the frequency shift with respect to the applied pressure load is 0.11 GHz/MPa.

Keywords: CMOS LC-based oscillator, micro pressure sensor, silicon carbide

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Authors: Kollarama Subramanyam, Nisha Kuruvilla, J. P. Raina

Abstract:

Novel compact expressions for propagation constant (γ) of SWCNT and bundled SWCNTs interconnect, in terms of physical parameters such as length, operating frequency and diameter of CNTs is proposed in this work. These simplified expressions enable physical insight and accurate estimation of signal attenuation level and its phase change at any length for a particular frequency. The proposed expressions are validated against SPICE simulated results of lumped as well as distributed equivalent electrical RLC nets of CNT interconnect. These expressions also help us to evaluate the cut off frequencies of SWCNTs for different interconnect lengths.

Keywords: Attenuation constant, Bundled SWCNT, CNT interconnects, Propagation Constant.

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Authors: Jan Doutreloigne

Abstract:

This paper describes two methods for the reduction of the peak input current during the boosting of Dickson charge pumps. Both methods are implemented in the fully integrated Dickson charge pumps of a high-voltage display driver chip for smart-card applications. Experimental results reveal good correspondence with Spice simulations and show a reduction of the peak input current by a factor of 6 during boosting.

Keywords: Bi-stable display driver, Dickson charge pump, highvoltage generator, peak current reduction, sub-pump boosting, variable frequency boosting.

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Authors: Junaid Rashid, Waqar Mehmood, Muhammad Wasif Nisar

Abstract:

This survey paper shows the recent state of model comparison as it’s applies to Model Driven engineering. In Model Driven Engineering to calculate the difference between the models is a very important and challenging task. There are number of tasks involved in model differencing that firstly starts with identifying and matching the elements of the model. In this paper, we discuss how model matching is accomplished, the strategies, techniques and the types of the model. We also discuss the future direction. We found out that many of the latest model comparison strategies are geared near enabling Meta model and similarity based matching. Therefore model versioning is the most dominant application of the model comparison. Recently to work on comparison for versioning has begun to deteriorate, giving way to different applications. Ultimately there is wide change among the tools in the measure of client exertion needed to perform model comparisons, as some require more push to encourage more sweeping statement and expressive force.

Keywords: Model comparison, model clone detection, model versioning, EMF Model, model diff.

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Authors: Şebnem Ertaş

Abstract:

“Architecture” is one component of sustainable cultural tourism. The sustainability of architecture is possible through preservation and restoration activities. In Turkey, which has an important place in the world’s cultural heritage, several studies focused on the sustainability of the cultural heritage were done in terms of the principles of “preserve-use-sustain”. Within the scope of this study, a methodology will be proposed in order to obtain the development of different scenarios supporting sustainable tourism. Sille is an ancient village located on the Spice Road and Silk Road dating back to the Ottoman and Seljuk eras. However, in recent years it is protected as an archeological site. In the “Alternative Project Phase”, the streets and buildings which bring dynamism to trade are determined; among these, 10 major buildings in Hacı Ali Ağa Street are studied.

Keywords: Tourism, cultural tourism, sustainability of architecture, interior design, Sille.

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Authors: Bala Dhandayuthapani Veerasamy

Abstract:

Parallel programming models exist as an abstraction of hardware and memory architectures. There are several parallel programming models in commonly use; they are shared memory model, thread model, message passing model, data parallel model, hybrid model, Flynn-s models, embarrassingly parallel computations model, pipelined computations model. These models are not specific to a particular type of machine or memory architecture. This paper expresses the model program for concurrent approach to data parallel model through java programming.

Keywords: Concurrent, Data Parallel, JDK, Parallel, Thread

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Authors: Georgia Garani

Abstract:

A generalised relational data model is formalised for the representation of data with nested structure of arbitrary depth. A recursive algebra for the proposed model is presented. All the operations are formally defined. The proposed model is proved to be a superset of the conventional relational model (CRM). The functionality and validity of the model is shown by a prototype implementation that has been undertaken in the functional programming language Miranda.

Keywords: nested relations, recursive algebra, recursive nested operations, relational data model.

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Authors: Mohammed Abdalla Osman Mukhtar, Azween Abdullah, Alan Giffin Downe

Abstract:

Model mapping and transformation are important processes in high level system abstractions, and form the cornerstone of model-driven architecture (MDA) techniques. Considerable research in this field has devoted attention to static system abstraction, despite the fact that most systems are dynamic with high frequency changes in behavior. In this paper we provide an overview of work that has been done with regard to behavior model mapping and transformation, based on: (1) the completeness of the platform independent model (PIM); (2) semantics of behavioral models; (3) languages supporting behavior model transformation processes; and (4) an evaluation of model composition to effect the best approach to describing large systems with high complexity.

Keywords: MDA; PIM, PSM, QVT, Model Transformation

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