**Commenced**in January 2007

**Frequency:**Monthly

**Edition:**International

**Paper Count:**32845

##### Estimation of Attenuation and Phase Delay in Driving Voltage Waveform of a Digital-Noiseless, Ultra-High-Speed Image Sensor

**Authors:**
V. T. S. Dao,
T. G. Etoh,
C. Vo Le,
H. D. Nguyen,
K. Takehara,
T. Akino,
K. Nishi

**Abstract:**

Since 2004, we have been developing an in-situ storage image sensor (ISIS) that captures more than 100 consecutive images at a frame rate of 10 Mfps with ultra-high sensitivity as well as the video camera for use with this ISIS. Currently, basic research is continuing in an attempt to increase the frame rate up to 100 Mfps and above. In order to suppress electro-magnetic noise at such high frequency, a digital-noiseless imaging transfer scheme has been developed utilizing solely sinusoidal driving voltages. This paper presents highly efficient-yet-accurate expressions to estimate attenuation as well as phase delay of driving voltages through RC networks of an ultra-high-speed image sensor. Elmore metric for a fundamental RC chain is employed as the first-order approximation. By application of dimensional analysis to SPICE data, we found a simple expression that significantly improves the accuracy of the approximation. Similarly, another simple closed-form model to estimate phase delay through fundamental RC networks is also obtained. Estimation error of both expressions is much less than previous works, only less 2% for most of the cases . The framework of this analysis can be extended to address similar issues of other VLSI structures.

**Keywords:**
Dimensional Analysis,
ISIS,
Digital-noiseless,
RC network,
Attenuation,
Phase Delay,
Elmore model

**Digital Object Identifier (DOI):**
doi.org/10.5281/zenodo.1078197

**References:**

[1] T. G. Etoh, D. Poggermann, A. Ruckelshausen, A. J. P. Theuwissen, G. Kreider, H. O. Folkerts, H. Mutoh, Y. Kondo, H. Maruno, K. Takubo, H. Soya, K. Takehara, T. Okinaka, Y. Takano, T. Reisinger, and C. Lohman, "A CCD image sensor of 1Mframes/s for continuous image capturing of 103 frames", Digest of Technical Papers, IEEE Int. Solid-State Circuits Conf., San Francisco, CA, pp. 46-47, 2002.

[2] T. G. Etoh, D. Poggermann, G. Kreider, H. Mutoh, A. J. P. Theuwissen, A. Ruckelshausen, Y. Kondo, H. Maruno, K. Takubo, H. Soya, K. Takehara, T. Okinaka, and Y. Takano, "An image sensor which captures 100 consecutive frames at 1,000,000 frame/s", IEEE Trans.Electron Dev., vol. 50, no. 1, Jan. 2003, pp. 144-151.

[3] T. G. Etoh, C. Vo Le, Y. Hashishin, N. Otsuka, K. Takehara, H. Ohtake, T. Hayashida, and H. Maruyama, "Evolution of ultra-high-speed CCD imagers", Plasma and Fusion Research, 2, S1021, 2007.

[4] T. G. Etoh, L. C. Vo, H. Kawano, I. Ishikawa, A. Miyawaki, V. T. S. Dao, H. D. Nguyen, S. Yokoi, S. Yoshida, H. Nakano, K. Takehara, Y. Saito, "Ultra-high-speed bionanoscope for cell and microbe imaging", in Proc. International. Congress on High Speed Imaging and Photonics, Canberra, Vol. 7126, 2008, pp. 712605-712605-11.

[5] C. Vo Le, H.D. Nguyen, V. T. S. Dao, K. Takehara, T. G. Etoh, T. Akino, K. Kitamura, T. Arai, H. Maruyama, "Technologies to develop a video camera with the frame rate higher than 100 Mfps", in Proc. International. Congress on High Speed Imaging and Photonics, Canberra, Vol. 7126, 2008, pp. 712606-712606-9.

[6] V. T. S. Dao, L. C. Vo, H. D. Nguyen, T. G. Etoh, K. Takehara, T. Akino, K. Nishi, "Estimation of driving voltage attenuation of an ultrahigh- speed image sensor by dimensional analysis", World Academy of Science, Engineering and Technology, Intl. Journal of Elect., Circuits Syst., vol. 4, 2008, pp. 200-204. URL: http://www.waset.org/ijecs/v2/v2- 4-36.pdf

[7] W.C. Elmore, "The transient response of damped linear networks with particular regard to wide-band amplifiers," J. Appl. Phys., vol. 19, no. 1, Jan. 1948, pp. 55-63.

[8] S. Y. Kim and S. S. Wong, "Closed-form RC and RLC delay models considering input rise time," IEEE Trans.Circuits Syst.-I, Regular Papers, vol. 54, no. 9, Sep. 2007, pp. 2001-2010.

[9] L.T. Pillage and R.A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Comput-Aided Des.Integr.Circuits Syst., vol. 9, no. 4, Apr. 1990, pp. 352-366.

[10] C. L. Ratzlaff, N. Gopal, and L. T. Pillage, "RICE: Rapid interconnect circuit evaluator," in Proc. IEEE/ACM Design Automation Conf., 1991, pp. 555-560.

[11] Y. I. Ismail and C. Amin, "Computation of Signal Threshold Crossing Times Directly from Higher Order Moments", IEEE Trans. Comput- Aided Des.Integr. Circuits Syst.,vol. 23, no. 8, Aug. 2004, pp. 1264-1276.

[12] D. E. Khalil, Y. Ismail, M. Khellah, T. Karnik, and V. De, "Analytical Model for the Propagation Delay of Through Silicon Vias", in Proc. 9th Int. Symp. Quality Electronic Design, 2008, pp. 553-556.

[13] J. Vlach, J. A. Barby, A. Vannelli, T. Talkhan, and C. J. Shi, "Group delay as an estimate of delay in logic," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol.10, no. 7, July 1991, pp. 949-953.

[14] M. Celik and L. T. Pillegi., "Metrics and bound for phase delay and signal attenuation in RC(L) clock trees," IEEE Trans.Comput.-Aided Des. Integr. Circuits Syst., vol.18, no. 3, Mar. 1999, pp. 293-300.