Search results for: third harmonic resistive leakage current

Authors: Ki-Young Kim, Jae-Ho Lim, Deok-Min Kim, Seok-Yoon Kim

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Average current analysis checking the impact of current flow is very important to guarantee the reliability of semiconductor systems. As semiconductor process technologies improve, the coupling capacitance often become bigger than self capacitances. In this paper, we propose an analytic technique for analyzing average current on interconnects in multi-conductor structures. The proposed technique has shown to yield the acceptable errors compared to HSPICE results while providing computational efficiency.

Keywords: current moment, interconnect modeling, reliability analysis, worst-case switching

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Authors: V. Suresh Babu, Haseena P. S., Varun P. Gopi, M. R. Baiju

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In this paper a scheme is proposed for generating a programmable current reference which can be implemented in the CMOS technology. The current can be varied over a wide range by changing an external voltage applied to one of the control gates of FGMOS (Floating Gate MOSFET). For a range of supply voltages and temperature, CMOS current reference is found to be dependent, this dependence is compensated by subtracting two current outputs with the same dependencies on the supply voltage and temperature. The system performance is found to improve with the use of FGMOS. Mathematical analysis of the proposed circuit is done to establish supply voltage and temperature independence. Simulation and performance evaluation of the proposed current reference circuit is done using TANNER EDA Tools. The current reference shows the supply and temperature dependencies of 520 ppm/V and 312 ppm/oC, respectively. The proposed current reference can operate down to 0.9 V supply.

Keywords: Floating Gate MOSFET, current reference, self bias scheme, temperature independency, supply voltage independency.

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Authors: Fatemeh Karimi, Morteza Fathipour, Hamdam Ghanatian, Vala Fathipour

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In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility in tensile strained silicon, the n-type FETs with strained silicon channel have better drain current compare with the pure Si one. In this structure gate dielectric divided in two parts, we have used high-κ dielectric near the source and low-κ dielectric near the drain to reduce the short channel effects. By this structure short channel effects such as FIBL will be reduced indeed by increasing the RSiGe, ID-VD characteristics will be improved. The leakage current and transfer characteristics, the threshold-voltage (Vt), the drain induced barrier height lowering (DIBL), are estimated with respect to, gate bias (VG), RSiGe and different gate dielectrics. For short channel effects, such as DIBL, gate all around strained silicon nanowire FET have similar characteristics with the pure Si one while dual dielectrics can improve short channel effects in this structure.

Keywords: SNWT (silicon nanowire transistor), Tensile Strain, high-κ dielectric, Field Induced Barrier Lowering (FIBL), cylindricalnano wire (CW), drain induced barrier lowering (DIBL).

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Authors: Khalil Monfaredi, Hassan Faraji Baghtash, Majid Abbasi

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In this paper a novel high output impedance, low input impedance, wide bandwidth, very simple current mirror with input and output voltage requirements less than that of a simple current mirror is presented. These features are achieved with very simple structure avoiding extra large node impedances to ensure high bandwidth operation. The circuit's principle of operation is discussed and compared to simple and low voltage cascode (LVC) current mirrors. Such outstanding features of this current mirror as high output impedance ~384K, low input impedance~6.4, wide bandwidth~178MHz, low input voltage ~ 362mV, low output voltage ~ 38mV and low current transfer error ~4% (all at 50μA) makes it an outstanding choice for high performance applications. Simulation results in BSIM 0.35μm CMOS technology with HSPICE are given in comparison with simple, and LVC current mirrors to verify and validate the performance of the proposed current mirror.

Keywords: Analog circuits, Current mirror, high frequency, Low power, Low voltage.

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Authors: Dalibor Biolek, Viera Biolková, Zden─øk Kolka

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A universal current-mode biquad is described which represents an economical variant of well-known KHN (Kerwin, Huelsman, Newcomb) voltage-mode filter. The circuit consists of two multiple-output OTAs and of two grounded capacitors. Utilizing simple splitter of the input current and a pair of jumpers, all the basic 2nd-order transfer functions can be implemented. The principle is verified by Spice simulation on the level of a CMOS structure of OTAs.

Keywords: Biquad, current mode, OTA.

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Authors: Lina Wu, Jia Liu, Ye Li

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The goal of this project is to investigate constant properties (called the Liouville-type Problem) for a p-stable map as a local or global minimum of a p-energy functional where the domain is a Euclidean space and the target space is a closed half-ellipsoid. The First and Second Variation Formulas for a p-energy functional has been applied in the Calculus Variation Method as computation techniques. Stokes’ Theorem, Cauchy-Schwarz Inequality, Hardy-Sobolev type Inequalities, and the Bochner Formula as estimation techniques have been used to estimate the lower bound and the upper bound of the derived p-Harmonic Stability Inequality. One challenging point in this project is to construct a family of variation maps such that the images of variation maps must be guaranteed in a closed half-ellipsoid. The other challenging point is to find a contradiction between the lower bound and the upper bound in an analysis of p-Harmonic Stability Inequality when a p-energy minimizing map is not constant. Therefore, the possibility of a non-constant p-energy minimizing map has been ruled out and the constant property for a p-energy minimizing map has been obtained. Our research finding is to explore the constant property for a p-stable map from a Euclidean space into a closed half-ellipsoid in a certain range of p. The certain range of p is determined by the dimension values of a Euclidean space (the domain) and an ellipsoid (the target space). The certain range of p is also bounded by the curvature values on an ellipsoid (that is, the ratio of the longest axis to the shortest axis). Regarding Liouville-type results for a p-stable map, our research finding on an ellipsoid is a generalization of mathematicians’ results on a sphere. Our result is also an extension of mathematicians’ Liouville-type results from a special ellipsoid with only one parameter to any ellipsoid with (n+1) parameters in the general setting.

Keywords: Bochner Formula, Stokes’ Theorem, Cauchy-Schwarz Inequality, first and second variation formulas, Hardy-Sobolev type inequalities, Liouville-type problem, p-harmonic map.

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Authors: Kimberly Jane S. Uy, Patricia Angela Reyes-Abu, Wen Yaw Chung

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A high precision temperature insensitive current and voltage reference generator is presented. It is specifically developed for temperature compensated oscillator. The circuit, designed using MXIC 0.5um CMOS technology, has an operating voltage that ranges from 2.6V to 5V and generates a voltage of 1.21V and a current of 6.38 ӴA. It exhibits a variation of ±0.3nA for the current reference and a stable output for voltage reference as the temperature is varied from 0°C to 70°C. The power supply rejection ratio obtained without any filtering capacitor at 100Hz and 10MHz is -30dB and -12dB respectively.

Keywords: Current reference, voltage reference, threshold voltage, temperature compensation, mobility.

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Authors: Néjib Hassen, Thouraya Ettaghzouti, Kamel Besbes

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In this paper, a modified CCCII is presented. We have used a current mirror with low supply voltage. This circuit is operated at low supply voltage of ±1V. Tspice simulations for TSMC 0.18μm CMOS Technology has shown that the current and voltage bandwidth are respectively 3.34GHz and 4.37GHz, and parasitic resistance at port X has a value of 169.320 for a control current of 120μA. In order to realize this circuit, we have implemented in this first step a universal current mode filter where the frequency can reach the 134.58MHz. In the second step, we have implemented two simulated inductors: one floating and the other grounded. These two inductors are operated in high frequency and variable depending on bias current I0. Finally, we have used the two last inductors respectively to implement two sinusoidal oscillators domains of frequencies respectively: [470MHz, 692MHz], and [358MHz, 572MHz] for bias currents I0 [80μA, 350μA].

Keywords: Current controlled current conveyor CCCII, floating inductor, grounded inductor, oscillator, universal filter.

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Authors: M. S. Sivagamasundari, P. Melba Mary

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Multilevel inverter is a promising inverter topology for high voltage and high power applications. This inverter synthesizes several different levels of DC voltages to produce a stepped AC output that approaches the pure sine waveform. The three different topologies, diode-clamped inverter, capacitor-clamped inverter and cascaded h-bridge multilevel inverter are widely used in these multilevel inverters. Among the three topologies, cascaded h-bridge multilevel inverter is more suitable for photovoltaic applications since each PV array can act as a separate dc source for each h-bridge module. This research especially focus on photovoltaic power source as input to the system and shows the potential of a Single Phase Cascaded H-bridge Eleven level inverter governed by the fuzzy logic controller to improve the power quality by reducing the total harmonic distortion at the output voltage. Hence the efficiency of the system will be improved. Simulation using MATLAB/SIMULINK has been done to verify the performance of cascaded h-bridge eleven level inverter using sinusoidal pulse width modulation technique. The simulated output shows very favorable result.

Keywords: Multilevel inverter, Cascaded H-Bridge multilevel inverter, Total Harmonic Distortion, Photovoltaic cell, Sinusoidal pulse width modulation.

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Authors: Karama M. AL-Tamimi, Munir A. Al-Absi

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A new OTA-based logarithmic-control variable gain current amplifier (LCCA) is presented. It consists of two Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The circuit operates from 0.6V DC power supply and consumes 0.6 μW. The linear-dB controllable output range is 43 dB with maximum error less than 0.5dB. The functionality of the proposed design was confirmed using HSPICE in 0.35μm CMOS process technology.

Keywords: LCCA, OTA, Logarithmic, VGA, Weak inversion, Current-mode

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Authors: Krzysztof Wawryn, Robert Suszyński, Bogdan Strzeszewski

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This paper presents two prototypes of low power low voltage current mode 9 bit pipelined a/d converters. The first and the second converters are configured of 1.5 bit and 2.5 bit stages, respectively. The a/d converter structures are composed of current mode building blocks and final comparator block which converts the analog current signal into digital voltage signal. All building blocks have been designed in CMOS AMS 0.35μm technology, then simulated to verify proposed concept. The performances of both converters are compared to performances of known current mode and voltage mode switched capacitance converter structures. Low power consumption and small chip area are advantages of the proposed converters.

Keywords: Pipelined converter, a/d converter, low power, lowvoltage, current mode.

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Authors: S.Srinivas

Abstract:

Multi-level voltage source inverters offer several advantages such as; derivation of a refined output voltage with reduced total harmonic distortion (THD), reduction of voltage ratings of the power semiconductor switching devices and also the reduced electro-magnetic-interference problems etc. In this paper, new carrier-overlapped phase-disposition or sub-harmonic sinusoidal pulse width modulation (CO-PD-SPWM) and also the carrieroverlapped phase-disposition space vector modulation (CO-PDSVPWM) schemes for a six-level diode-clamped inverter topology are proposed. The principle of the proposed PWM schemes is similar to the conventional PD-PWM with a little deviation from it in the sense that the triangular carriers are all overlapped. The overlapping of the triangular carriers on one hand results in an increased number of switchings, on the other hand this facilitates an improved spectral performance of the output voltage. It is demonstrated through simulation studies that the six-level diode-clamped inverter with the use of CO-PD-SPWM and CO-PD-SVPWM proposed in this paper is capable of generating multiple levels in its output voltage. The advantages of the proposed PWM schemes can be derived to benefit, especially at lower modulation indices of the inverter and hence this aspect of the proposed PWM schemes can be well exploited in high power applications requiring low speeds of operation of the drive.

Keywords: Diode clamped inverter, Pulse width modulation, Six level inverter, carrier based PWM.

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Authors: E. Selçuk, Z. Karaçor, P. Yardımcı

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Trade liberalization and its effects on the economies of developing countries have been investigated by many different studies, and some of them have focused on its impact on the current account balance. Turkey, as being one of the countries, which has liberalized its foreign trade in the 1980s, also needs to be studied in terms of the impact of liberalization on current account deficits. Therefore, the aim of this study is to find out whether trade liberalization has affected Turkey’s trade and current account balances. In order to determine this, yearly data of Turkey from 1980 to 2013 is used. As liberalization dummy, the year 1989, which was set for Turkey, is selected. Structural break test and model estimation results show that trade liberalization has a negative impact on trade balance but do not have a significant impact on the current account balance.

Keywords: Budget deficit, current account, liberalization, Turkish economy.

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Authors: Labar Hocine, Dgeghader Yacine, Kelaiaia Mounia Samira, Bounaya Kamel

Abstract:

To maximise furnace production it-s necessary to optimise furnace control, with the objectives of achieving maximum power input into the melting process, minimum network distortion and power-off time, without compromise on quality and safety. This can be achieved with on the one hand by an appropriate electrode control and on the other hand by a minimum of AC transformer switching. Electrical arc is a stochastic process; witch is the principal cause of power quality problems, including voltages dips, harmonic distortion, unbalance loads and flicker. So it is difficult to make an appropriate model for an Electrical Arc Furnace (EAF). The factors that effect EAF operation are the melting or refining materials, melting stage, electrode position (arc length), electrode arm control and short circuit power of the feeder. So arc voltages, current and power are defined as a nonlinear function of the arc length. In this article we propose our own empirical function of the EAF and model, for the mean stages of the melting process, thanks to the measurements in the steel factory.

Keywords: Modelling, electrical arc, melting, power, EAF, steel.

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Authors: J. Chelladurai, G. Saravana Ilango, C. Nagamani, S. Senthil Kumar

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Pulse width modulation (PWM) techniques have been the subject of intensive research for different industrial and power sector applications. A large variety of methods, different in concept and performance, have been newly developed and described. This paper analyzes the comparative merits of Sinusoidal Pulse Width Modulation (SPWM) and Space Vector Pulse Width Modulation (SVPWM) techniques and the suitability of these techniques in a Shunt Active Filter (SAF). The objective is to select the scheme that offers effective utilization of DC bus voltage and also harmonic reduction at the input side. The effectiveness of the PWM techniques is tested in the SAF configuration with a non linear load. The performance of the SAF with the SPWM and (SVPWM) techniques are compared with respect to the THD in source current. The study reveals that in the context of closed loop SAF control with the SVPWM technique there is only a minor improvement in THD. The utilization of the DC bus with SVPWM is also not significant compared to that with SPWM because of the non sinusoidal modulating signal from the controller in SAF configuration.

Keywords: Voltage source inverter, Shunt active filter, SPWM, SVPWM, Matlab/SIMULINK.

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Authors: Adrian T. Plesca

Abstract:

This paper describes a three-dimensional thermal model of the current path included in the low voltage power circuit breakers. The model can be used to analyse the thermal behaviour of the current path during both steady-state and transient conditions. The current path lengthwise temperature distribution and timecurrent characteristic of the terminal connections of the power circuit breaker have been obtained. The influence of the electric current and voltage drop on main electric contact of the circuit breaker has been investigated. To validate the three-dimensional thermal model, some experimental tests have been done. There is a good correlation between experimental and simulation results.

Keywords: Current path, power circuit breakers, temperature distribution, thermal analysis.

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Authors: Z. X. Chen, Z. Fang, X. P. Wang, G. -Q. Lo, D. -L. Kwong, Y. H. Wu

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This paper presents a study of Ni-silicides as the bottom electrode of HfO₂-based RRAM. Various silicidation conditions were used to obtain different Ni concentrations within the Ni-silicide bottom electrode, namely Ni₂Si, NiSi, and NiSi₂. A 10nm HfO₂ switching material and 50nm TiN top electrode was then deposited and etched into 500nm by 500nm square RRAM cells. Cell performance of the Ni₂Si and NiSi cells were good, while the NiSi₂ cell could not switch reliably, indicating that the presence of Ni in the bottom electrode is important for good switching.

Keywords: HfO2-based, Ni-silicide, NiSi, resistive RAM (RRAM).

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Authors: Hassan Faraji Baghtash

Abstract:

In this paper, a low voltage high performance current mirror is presented. Its most important specifications, which are improved in this work, are analyzed and formulated proving that it has such outstanding merits as: Very low input resistance of 26mΩ, very wide current dynamic range of 8 decades from 10pA to 1mA (160dB) together with an extremely low current copy error of less than 0.6ppm, and very low input and output voltages. Furthermore, the proposed current mirror bandwidth is 944MHz utilizing very low power consumption (267μW) and transistors count. HSPICE simulation results are performed using TSMC 0.18μm CMOS technology utilizing 1.8V single power supply, confirming the theoretically proved outstanding performance of the proposed current mirror. Monte Carlo simulation of its most important parameter is also examined showing its sufficiently resistance against technology process variations.

Keywords: Current mirror/source, high accuracy, low voltage, wide dynamic range.

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Authors: Lv Xiaopeng, Bian Qiang, Yue Suge

Abstract:

A fully on-chip low drop-out (LDO) voltage regulator with 100pF output load capacitor is presented. A novel frequency compensation scheme using current buffer is adopted to realize single dominant pole within the unit gain frequency of the regulation loop, the phase margin (PM) is at least 50 degree under the full range of the load current, and the power supply rejection (PSR) character is improved compared with conventional Miller compensation. Besides, the differentiator provides a high speed path during the load current transient. Implemented in 0.18μm CMOS technology, the LDO voltage regulator provides 100mA load current with a stable 1.8V output voltage consuming 80μA quiescent current.

Keywords: capacitor-less LDO, frequency compensation, transient response, power supply rejection

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Authors: JeongJu Kim, Heeyoon Chung, DongHo Rhee, HyungHee Cho

Abstract:

There is a gap at combustor-turbine interface where leakage flow comes out to prevent hot gas ingestion into the gas turbine nozzle platform. The leakage flow protects the nozzle endwall surface from the hot gas coming from combustor exit. For controlling flow’s stream, the gap’s geometry is transformed by changing fillet radius size. During the operation, step configuration is occurred that was unintended between combustor-turbine platform interface caused by thermal expansion or mismatched assembly. In this study, CFD simulations were performed to investigate the effect of the fillet and step on heat transfer and film cooling effectiveness on the nozzle platform. The Reynolds-averaged Navier-stokes equation was solved with turbulence model, SST k-omega. With the fillet configuration, predicted film cooling effectiveness results indicated that fillet radius size influences to enhance film cooling effectiveness. Predicted film cooling effectiveness results at forward facing step configuration indicated that step height influences to enhance film cooling effectiveness. We suggested that designer change a combustor-turbine interface configuration which was varied by fillet radius size near endwall gap when there was a step at combustor-turbine interface. Gap shape was modified by increasing fillet radius size near nozzle endwall. Also, fillet radius and step height were interacted with the film cooling effectiveness and heat transfer on endwall surface.

Keywords: Gas turbine, film cooling effectiveness, endwall, fillet.

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Authors: Jae Hyung Noh, Hang Geun Jeong

Abstract:

The charge-pump circuit is an important component in a phase-locked loop (PLL). The charge-pump converts Up and Down signals from the phase/frequency detector (PFD) into current. A conventional CMOS charge-pump circuit consists of two switched current sources that pump charge into or out of the loop filter according to two logical inputs. The mismatch between the charging current and the discharging current causes phase offset and reference spurs in a PLL. We propose a new charge-pump circuit to reduce the current mismatch by using a regulated cascode circuit. The proposed charge-pump circuit is designed and simulated by spectre with TSMC 0.18-μm 1.8-V CMOS technology.

Keywords: Phase-locked loop (PLL), charge-pump, phase/frequency detector (PFD), regulated cascode.

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Authors: J. Schmidt, O. Kornadt

Abstract:

The major part of light weight timber constructions consists of insulation. Mineral wool is the most commonly used insulation due to its cost efficiency and easy handling. The fiber orientation and porosity of this insulation material enables flowthrough. The air flow resistance is low. If leakage occurs in the insulated bay section, the convective flow may cause energy losses and infiltration of the exterior wall with moisture and particles. In particular the infiltrated moisture may lead to thermal bridges and growth of health endangering mould and mildew. In order to prevent this problem, different numerical calculation models have been developed. All models developed so far have a potential for completion. The implementation of the flow-through properties of mineral wool insulation may help to improve the existing models. Assuming that the real pressure difference between interior and exterior surface is larger than the prescribed pressure difference in the standard test procedure for mineral wool ISO 9053 / EN 29053, measurements were performed using the measurement setup for research on convective moisture transfer “MSRCMT". These measurements show, that structural inhomogeneities of mineral wool effect the permeability only at higher pressure differences, as applied in MSRCMT. Additional microscopic investigations show, that the location of a leak within the construction has a crucial influence on the air flow-through and the infiltration rate. The results clearly indicate that the empirical values for the acoustic resistance of mineral wool should not be used for the calculation of convective transfer mechanisms.

Keywords: convection, convective transfer, infiltration, mineralwool, permeability, resistance, leakage

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Authors: Jun Yu, Yat-Hei Lam, Boris Grinberg, Kevin Chai Tshun Chuan

Abstract:

This paper presents a 5-V to 30-V current-mode boost converter for powering the drive circuit of a micro-electro-mechanical sensor. The design of a transconductance amplifier and an integrated current sensing circuit are presented. In addition, essential building blocks for power-on protection such as a soft-start and clamp block and supply and clock ready block are discussed in details. The chip is fabricated in a 0.18-μm CMOS process. Measurement results show that the soft-start and clamp block can effectively limit the inrush current during startup and protect the boost converter from startup failure.

Keywords: Boost Converter, Current Sensing, Power-on protection, Step-up Converter, Soft-start.

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Authors: Zia Abbas, Giuseppe Scotti, Mauro Olivieri

Abstract:

Current mode circuits like current conveyors are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption and less chip area. The second generation current controlled conveyor (CCCII) has the advantage of electronic adjustability over the CCII i.e. in CCCII; adjustment of the X-terminal intrinsic resistance via a bias current is possible. The presented approach is based on the CMOS implementation of second generation positive (CCCII+), negative (CCCII-) and dual Output Current Controlled Conveyor (DOCCCII) and its application as Universal filter. All the circuits have been designed and simulated using 65nm CMOS technology model parameters on Cadence Virtuoso / Spectre using 1V supply voltage. Various simulations have been carried out to verify the linearity between output and input ports, range of operation frequency, etc. The outcomes show good agreement between expected and experimental results.

Keywords: CCCII+, CCCII-, DOCCCII, Electronic tunability, Universal filter

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Authors: Jie Zhang, Qianyu Guo, Tieyi Zhang, Zhiyong Feng, Xiaohong Li

Abstract:

The widespread popularity of mobile devices and the development of artificial intelligence (AI) have led to the widespread adoption of deep learning (DL) in Android apps. Compared with traditional Android apps (traditional apps), deep learning based Android apps (DL-based apps) need to use more third-party application programming interfaces (APIs) to complete complex DL inference tasks. However, existing methods (e.g., FlowDroid) for detecting sensitive information leakage in Android apps cannot be directly used to detect DL-based apps as they are difficult to detect third-party APIs. To solve this problem, we design DLtrace, a new static information flow analysis tool that can effectively recognize third-party APIs. With our proposed trace and detection algorithms, DLtrace can also efficiently detect privacy leaks caused by sensitive APIs in DL-based apps. Additionally, we propose two formal definitions to deal with the common polymorphism and anonymous inner-class problems in the Android static analyzer. Using DLtrace, we summarize the non-sequential characteristics of DL inference tasks in DL-based apps and the specific functionalities provided by DL models for such apps. We conduct an empirical assessment with DLtrace on 208 popular DL-based apps in the wild and found that 26.0% of the apps suffered from sensitive information leakage. Furthermore, DLtrace outperformed FlowDroid in detecting and identifying third-party APIs. The experimental results demonstrate that DLtrace expands FlowDroid in understanding DL-based apps and detecting security issues therein.

Keywords: Mobile computing, deep learning apps, sensitive information, static analysis.

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Authors: F. Salehuddin, I. Ahmad, F. A. Hamid, A. Zaharim, H. A. Elgomati, B. Y. Majlis, P. R. Apte

Abstract:

In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant variations on threshold voltage (VTH) and leakage current (ILeak) in 45nm p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) device. Besides halo implant dose, the other process parameters which used were Source/Drain (S/D) implant dose, oxide growth temperature and silicide anneal temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to VTH and ILeak are halo implant dose (40%) and S/D implant dose (52%) respectively. Whereas the second ranking factor affecting VTH and ILeak are oxide growth temperature (32%) and halo implant dose (34%) respectively. The results show that after optimizations approaches is -0.157V at ILeak=0.195mA/μm.

Keywords: Optimization, p-type MOSFETs device, HALO Structure, Taguchi Method.

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Authors: M. Sajjadnejad, H. Karimi Abadeh

Abstract:

In this research, zinc coatings were fabricated by electroplating process in a sulfate solution under direct and pulse current conditions. In direct and pulse current conditions, effect of maximum current was investigated on the coating properties. Also a comparison was made between the obtained coatings under direct and pulse current. Morphology of the coatings was investigated by scanning electron microscopy (SEM). Corrosion behavior of the coatings was investigated by potentiodynamic polarization test. In pulse current conditions, the effect of pulse frequency and duty cycle was also studied. The effect of these conditions and parameters were also investigated on morphology and corrosion behavior. All of DC plated coatings are showing a distinct passivation area in -1 to -0.4 V range. Pulsed current coatings possessed a higher corrosion resistance. The results showed that current density is the most important factor regarding the fabrication process. Furthermore, a rise in duty cycle deteriorated corrosion resistance of coatings. Pulsed plated coatings performed almost 10 times better than DC plated coatings.

Keywords: Corrosion, duty cycle, pulsed current, zinc.

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Authors: Min-ju Kwon, Chae-won Kim, Jeong-yun Seo, Hee-guk Chae, Yong-seo Koo

Abstract:

In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.

Keywords: LDO regulator, noise sensing circuit, current reference, pass transistor.

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Authors: D. Subedi, S. Pradhan

Abstract:

Current transformers are an integral part of power system because it provides a proportional safe amount of current for protection and measurement applications. However, when the power system experiences an abnormal situation leading to huge current flow, then this huge current is proportionally injected to the protection and metering circuit. Since the protection and metering equipment’s are designed to withstand only certain amount of current with respect to time, these high currents pose a risk to man and equipment. Therefore, during such instances, the CT saturation characteristics have a huge influence on the safety of both man and equipment and on the reliability of the protection and metering system. This paper shows the effect of burden on the Accuracy Limiting factor/ Instrument security factor of current transformers and the change in saturation characteristics of the CT’s. The response of the CT to varying levels of overcurrent at different connected burden will be captured using the data acquisition software LabVIEW. Analysis is done on the real time data gathered using LabVIEW. Variation of current transformer saturation characteristics with changes in burden will be discussed.

Keywords: Accuracy limiting factor, burden, current transformer, instrument security factor, saturation characteristics.

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Authors: Ahmed Helal, Sherif Zain Elabideen, Ahmed Lotfy

Abstract:

In this paper the modeling and analysis of Space Vector Pulse Width Modulation (SVPWM) based Dynamic Voltage Restorer (DVR) using PSCAD/EMTDC software will be presented in details. The simulation includes full modeling of the SVPWM technique used to control the DVR inverter. A test power system composed of three phase voltage source, sag generator, DVR and three phase resistive load is used to demonstrate restoration capability of the DVR. The simulation results of the presented DVR proved excellent voltage sag mitigation to protect sensitive loads.

Keywords: Dynamic voltage restorer, power quality, simulationand modeling, voltage sag.

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