Search results for: Circuit breaker
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 564

Search results for: Circuit breaker

264 A SAW-less Dual-Band CDMA Diversity and Simultaneous-GPS Zero-IF Receiver

Authors: Bassem Fahs, Philippe Barré, Patrick Ozenne, Eric Chartier, Guillaume Hérault, Sébastien Jacquet, Sébastien Clamagirand

Abstract:

We present a dual-band (Cellular & PCS) dual-path zero-IF receiver for CDMA2000 diversity, monitoring and simultaneous-GPS. The secondary path is a SAW-less diversity CDMA receiver which can be also used for advanced features like monitoring when supported with an additional external VCO. A GPS receiver is integrated with its dedicated VCO allowing simultaneous positioning during a cellular call. The circuit is implemented in a 0.25μm 40GHz-fT BiCMOS process and uses a HVQFN 56-pin package. It consumes a maximum 300mW from a 2.8V supply in dual-modes. The chip area is 12.8mm2.

Keywords: CDMA, diversity, GPS, zero-IF, SAW-less

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263 Design and Control of DC-DC Converter for the Military Application Fuel Cell

Authors: Tae-Yeong Lee, Eun-Ju Yoo, Won-Yeong Choi, Young-Woo Park

Abstract:

This paper presents a 24 watts SEPIC converter design and control using microprocessor. SEPIC converter has advantages of a wide input range and miniaturization caused by the low stress at elements. There is also an advantage that the input and output are isolated in MOSFET-off state. This paper presents the PID control through the SEPIC converter transfer function using a DSP and the protective circuit for fuel cell from the over-current and inverse-voltage by using the characteristic of SEPIC converter. Then it derives them through the experiments.

Keywords: DC-DC Converter, Fuel-Cell, Microprocessor Control, Military Converter, SEPIC Converter

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262 2D Image Processing for DSO Astrophotography

Authors: R. Suszynski, K. Wawryn, R. Wirski

Abstract:

The new concept of two–dimensional (2D) image processing implementation for auto-guiding system is shown in this paper. It is dedicated to astrophotography and operates with astronomy CCD guide cameras or with self-guided dual-detector CCD cameras and ST4 compatible equatorial mounts. This idea was verified by MATLAB model, which was used to test all procedures and data conversions. Next the circuit prototype was implemented at Altera MAX II CPLD device and tested for real astronomical object images. The digital processing speed of CPLD prototype board was sufficient for correct equatorial mount guiding in real-time system.

Keywords: DSO astrophotography, image processing, twodimensionalconvolution method, two-dimensional filtering.

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261 Low Power Approach for Decimation Filter Hardware Realization

Authors: Kar Foo Chong, Pradeep K. Gopalakrishnan, T. Hui Teo

Abstract:

There are multiple ways to implement a decimator filter. This paper addresses usage of CIC (cascaded-integrator-comb) filter and HB (half band) filter as the decimator filter to reduce the frequency sample rate by factor of 64 and detail of the implementation step to realize this design in hardware. Low power design approach for CIC filter and half band filter will be discussed. The filter design is implemented through MATLAB system modeling, ASIC (application specific integrated circuit) design flow and verified using a FPGA (field programmable gate array) board and MATLAB analysis.

Keywords: CIC filter, decimation filter, half-band filter, lowpower.

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260 A Current-mode Continuous-time Sigma-delta Modulator based on Translinear Loop Principle

Authors: P. Jelodarian , E. Farshidi

Abstract:

In this paper, a new approach for design of a fully differential second order current mode continuous-time sigma-delta modulator is presented. For circuit implementation, square root domain (SRD) translinear loop based on floating-gate MOS transistors that operate in saturation region is employed. The modulator features, low supply voltage, low power consumption (8mW) and high dynamic range (55dB). Simulation results confirm that this design is suitable for data converters.

Keywords: Sigma-delta, current-mode, translinear loop, geometric mean, squarer/divider.

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259 Performance Monitoring of the Refrigeration System with Minimum Set of Sensors

Authors: Radek Fisera, Petr Stluka

Abstract:

This paper describes a methodology for remote performance monitoring of retail refrigeration systems. The proposed framework starts with monitoring of the whole refrigeration circuit which allows detecting deviations from expected behavior caused by various faults and degradations. The subsequent diagnostics methods drill down deeper in the equipment hierarchy to more specifically determine root causes. An important feature of the proposed concept is that it does not require any additional sensors, and thus, the performance monitoring solution can be deployed at a low installation cost. Moreover only a minimum of contextual information is required, which also substantially reduces time and cost of the deployment process.

Keywords: Condition monitoring, energy baselining, fault detection and diagnostics, commercial refrigeration.

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258 Optimal Assessment of Faulted Area around an Industrial Customer for Critical Sag Magnitudes

Authors: Marios N. Moschakis

Abstract:

This paper deals with the assessment of faulted area around an industrial customer connected to a particular electric grid that will cause a certain sag magnitude on this customer. The faulted (critical or exposed) area’s length is calculated by adding all line lengths in the neighborhood of the critical node (customer). The applied method is the so-called Method of Critical Distances. By using advanced short-circuit analysis, the Critical Area can be accurately calculated for radial and meshed power networks due to all symmetrical and asymmetrical faults. For the demonstration of the effectiveness of the proposed methodology, a study case is used.

Keywords: Critical area, fault-induced voltage sags, industrial customers, power quality.

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257 Sediment Transport Monitoring in the Port of Veracruz Expansion Project

Authors: Francisco Liaño-Carrera, José Isaac Ramírez-Macías, David Salas-Monreal, Mayra Lorena Riveron-Enzastiga, Marcos Rangel-Avalos, Adriana Andrea Roldán-Ubando

Abstract:

The construction of most coastal infrastructure developments around the world are usually made considering wave height, current velocities and river discharges; however, little effort has been paid to surveying sediment transport during dredging or the modification to currents outside the ports or marinas during and after the construction. This study shows a complete survey during the construction of one of the largest ports of the Gulf of Mexico. An anchored Acoustic Doppler Current Velocity profiler (ADCP), a towed ADCP and a combination of model outputs were used at the Veracruz port construction in order to describe the hourly sediment transport and current modifications in and out of the new port. Owing to the stability of the system the new port was construction inside Vergara Bay, a low wave energy system with a tidal range of up to 0.40 m. The results show a two-current system pattern within the bay. The north side of the bay has an anticyclonic gyre, while the southern part of the bay shows a cyclonic gyre. Sediment transport trajectories were made every hour using the anchored ADCP, a numerical model and the weekly data obtained from the towed ADCP within the entire bay. The sediment transport trajectories were carefully tracked since the bay is surrounded by coral reef structures which are sensitive to sedimentation rate and water turbidity. The survey shows that during dredging and rock input used to build the wave breaker sediments were locally added (< 2500 m2) and local currents disperse it in less than 4 h. While the river input located in the middle of the bay and the sewer system plant may add more than 10 times this amount during a rainy day or during the tourist season. Finally, the coastal line obtained seasonally with a drone suggests that the southern part of the bay has not been modified by the construction of the new port located in the northern part of the bay, owing to the two subsystem division of the bay.

Keywords: Acoustic Doppler current profiler, time series, port construction, construction around coral reefs, sediment transport monitoring.

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256 An Experimental Investigation of Heating in Induction Motors

Authors: R. Khaldi, N. Benamrouche, M. Bouheraoua

Abstract:

The ability to predict an accurate temperature distribution requires the knowledge of the losses, the thermal characteristics of the materials, and the cooling conditions, all of which are very difficult to quantify. In this paper, the impact of the effects of iron and copper losses are investigated separately and their effects on the heating in various points of the stator of an induction motor, is highlighted by using two simple tests. In addition, the effect of a defect, such as an open circuit in a phase of the stator, on the heating is also obtained by a no-load test. The squirrel cage induction motor is rated at 2.2 kW; 380 V; 5.2 A; Δ connected; 50 Hz; 1420 rpm and the class of insulation F, has been thermally tested under several load conditions. Several thermocouples were placed in strategic points of the stator.

Keywords: induction motor, temperature, heating, losses

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255 Comparative Performance Analysis of Nonlinearity Cancellation Techniques for MOS-C Realization in Integrator Circuits

Authors: Hasan Çiçekli, Ahmet Gökçen, Uğur Çam

Abstract:

In this paper, a comparative performance analysis of mostly used four nonlinearity cancellation techniques used to realize the passive resistor by MOS transistors, is presented. The comparison is done by using an integrator circuit which is employing sequentially Op-amp, OTRA and ICCII as active element. All of the circuits are implemented by MOS-C realization and simulated by PSPICE program using 0.35μm process TSMC MOSIS model parameters. With MOS-C realization, the circuits became electronically tunable and fully integrable which is very important in IC design. The output waveforms, frequency responses, THD analysis results and features of the nonlinearity cancellation techniques are also given.

Keywords: Integrator circuits, MOS-C realization, nonlinearity cancellation, tunable resistors.

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254 Measurement Fractional Order Sallen-Key Filters

Authors: Ahmed Soltan, Ahmed G. Radwan, Ahmed M. Soliman

Abstract:

This work aims to generalize the integer order Sallen-Key filters into the fractional-order domain. The analysis in the case of two different fractional-order elements introduced where the general transfer function becomes four terms which is unusual in the conventional case. In addition, the effect of the transfer function parameters on the filter poles and hence the stability is introduced and closed forms for the filter critical frequencies are driven. Finally, different examples for the fractional order Sallen-Key filter design are presented with circuit simulations using ADS where a great matching between the numerical and simulation results is obtained.

Keywords: Analog Filter, Low-Pass Filter, Fractance, Sallen-Key, Stability.

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253 High-Speed High-Gain CMOS OTA for SC Applications

Authors: M.Yousefi, A.Vatanjou, F.Nazeri

Abstract:

A fast settling multipath CMOS OTA for high speed switched capacitor applications is presented here. With the basic topology similar to folded-cascode, bandwidth and DC gain of the OTA are enhanced by adding extra paths for signal from input to output. Designed circuit is simulated with HSPICE using level 49 parameters (BSIM 3v3) in 0.35mm standard CMOS technology. DC gain achieved is 56.7dB and Unity Gain Bandwidth (UGB) obtained is 1.15GHz. These results confirm that adding extra paths for signal can improve DC gain and UGB of folded-cascode significantly.

Keywords: OTA (Operational Transconductance Amplifier), DC gain, Unity Gain Bandwidth (UGBW)

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252 New Design Methodologies for High Speed Low Power XOR-XNOR Circuits

Authors: Shiv Shankar Mishra, S. Wairya, R. K. Nagaria, S. Tiwari

Abstract:

New methodologies for XOR-XNOR circuits are proposed to improve the speed and power as these circuits are basic building blocks of many arithmetic circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. The performance of the XOR-XNOR circuits based on TSMC 0.18μm process models at all range of the supply voltage starting from 0.6V to 3.3V is evaluated by the comparison of the simulation results obtained from HSPICE. Simulation results reveal that the proposed circuit exhibit lower PDP and EDP, more power efficient and faster when compared with best available XOR-XNOR circuits in the literature.

Keywords: Exclusive-OR (XOR), Exclusive-NOR (XNOR), High speed, Low power, Arithmetic Circuits.

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251 Design and Layout of a X-Band MMIC Power Amplifier in a Phemt Technology

Authors: Renbin Dai, Rana Arslan Ali Khan

Abstract:

The design of Class A and Class AB 2-stage X band Power Amplifier is described in this report. This power amplifier is part of a transceiver used in radar for monitoring iron characteristics in a blast furnace. The circuit was designed using foundry WIN Semiconductors. The specification requires 15dB gain in the linear region, VSWR nearly 1 at input as well as at the output, an output power of 10 dBm and good stable performance in the band 10.9-12.2 GHz. The design was implemented by using inter-stage configuration, the Class A amplifier was chosen for driver stage i.e. the first amplifier focusing on the gain and the output amplifier conducted at Class AB with more emphasis on output power.

Keywords: Power amplifier, Class AB, Class A, MMIC, 2-stage, X band.

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250 Industrial Waste Monitoring

Authors: Khairuddin Bin Osman, Ngo Boon Kiat, A. Hamid Bin hamidon, Khairul Azha Bin A. Aziz, Hazli Rafis Bin Abdul Rahman, Mazran Bin Esro

Abstract:

Conventional industrial monitoring systems are tedious, inefficient and the at times integrity of the data is unreliable. The objective of this system is to monitor industrial processes specifically the fluid level which will measure the instantaneous fluid level parameter and respond by text messaging the exact value of the parameter to the user when being enquired by a privileged access user. The development of the embedded program code and the circuit for fluid level measuring are discussed as well. Suggestions for future implementations and efficient remote monitoring works are included.

Keywords: Industrial monitoring system, text messaging, embedded programming.

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249 Ribbon Beam Antenna for RFID Technology

Authors: T. Zalabsky, P. Bezousek, T. Shejbal

Abstract:

The paper describes new concept of the ribbon beam antenna for RFID technology. Antenna is located near to railway lines to monitor tags situated on trains. Antenna works at 2.45 GHz and it is fabricated by microstrip technology. Antenna contains two same mirrored parts having the same radiation patterns. Each part consists of three dielectric layers. The first layer has on one side radiation elements. The second layer is only for mechanical construction and it sets optimal electromagnetic field for each radiating elements. The third layer has on its top side a ground plane and on the bottom side a microstrip circuit used for individual radiation elements feeding.

Keywords: RFID, cosecant radiation pattern, ribbon beam, patch antenna, microstrip.

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248 An 8-Bit, 100-MSPS Fully Dynamic SAR ADC for Ultra-High Speed Image Sensor

Authors: F. Rarbi, D. Dzahini, W. Uhring

Abstract:

In this paper, a dynamic and power efficient 8-bit and 100-MSPS Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is presented. The circuit uses a non-differential capacitive Digital-to-Analog (DAC) architecture segmented by 2. The prototype is produced in a commercial 65-nm 1P7M CMOS technology with 1.2-V supply voltage. The size of the core ADC is 208.6 x 103.6 µm2. The post-layout noise simulation results feature a SNR of 46.9 dB at Nyquist frequency, which means an effective number of bit (ENOB) of 7.5-b. The total power consumption of this SAR ADC is only 1.55 mW at 100-MSPS. It achieves then a figure of merit of 85.6 fJ/step.

Keywords: CMOS analog to digital converter, dynamic comparator, image sensor application, successive approximation register.

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247 Design and Layout of Two Stage High Band Width Operational Amplifier

Authors: Yasir Mahmood Qureshi

Abstract:

This paper presents the design and layout of a two stage, high speed operational amplifiers using standard 0.35um CMOS technology. The design procedure involves designing the bias circuit, the differential input pair, and the gain stage using CAD tools. Both schematic and layout of the operational amplifier along with the comparison in the results of the two has been presented. The operational amplifier designed, has a gain of 93.51db at low frequencies. It has a gain bandwidth product of 55.07MHz, phase margin of 51.9º and a slew rate of 22v/us for a load of capacitor of 10pF.

Keywords: Gain bandwidth product, Operational Amplifier, phase margin, slew rate.

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246 Bias Stability of a-IGZO TFT and a new Shift-Register Design Suitable for a-IGZO TFT

Authors: Young Wook Lee, Sun-Jae Kim, Soo-Yeon Lee, Moon-Kyu Song, Woo-Geun Lee Min-Koo Han

Abstract:

We have fabricated a-IGZO TFT and investigated the stability under positive DC and AC bias stress. The threshold voltage of a-IGZO TFT shifts positively under those biases, and that reduces on-current. For this reason, conventional shift-register circuit employing TFTs which stressed by positive bias will be unstable, may do not work properly. We have designed a new 6-transistor shift-register, which has less transistors than prior circuits. The TFTs of the proposed shift-register are not suffering from positive DC or AC stress, mainly kept unbiased. Despite the compact design, the stable output signal was verified through the SPICE simulation even under RC delay of clock signal.

Keywords: Indium Gallium Zinc Oxide (IGZO), Thin FilmTransistor (TFT), shift-register

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245 Design Considerations of Scheduling Systems Suitable for PCB Manufacturing

Authors: Oscar Fernandez-Flores, Tony Speer, Rodney Day

Abstract:

This paper identifies five key design characteristics of production scheduling software systems in printed circuit board (PCB) manufacturing. The authors consider that, in addition to an effective scheduling engine, a scheduling system should be able to process a preventative maintenance calendar, to give the user the flexibility to handle data using a variety of electronic sources, to run simulations to support decision-making, and to have simple and customisable graphical user interfaces. These design considerations were the result of a review of academic literature, the evaluation of commercial applications and a compilation of requirements of a PCB manufacturer. It was found that, from those systems that were evaluated, those that effectively addressed all five characteristics outlined in this paper were the most robust of all and could be used in PCB manufacturing.

Keywords: Decision-making, ERP, PCB, scheduling.

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244 Novel Sinusoidal Pulse Width Modulation with Least Correlated Noise

Authors: Shiang-Hwua Yu, Han-Sheng Tseng

Abstract:

This paper presents a novel sinusoidal modulation scheme that features least correlated noise and high linearity. The modulation circuit, which is composed of a quantizer, a resonator, and a comparator, is capable of eliminating correlated modulation noise while doing modulation. The proposed modulation scheme combined with the linear quadratic optimal control is applied to a single-phase voltage source inverter and validated with the experiment results. The experiments show that the inverter supplies stable 60Hz 110V AC power with a total harmonic distortion of less than 1%, under the DC input variation from 190 V to 300 V and the output power variation from 0 to 600 W.

Keywords: Pulse width modulation, feedback dithering, linear quadratic control, inverter.

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243 Effect of Electric Field Amplitude on Electrical Fatigue Behavior of Lead Zirconate Titanate Ceramic

Authors: S. Kampoosiri, S. Pojprapai, R. Yimnirunand, B. Marungsri

Abstract:

Fatigue behaviors of Lead Zirconate Titanate (PZT) ceramics under different amplitude of bipolar electrical loads have been investigated. Fatigue behavior is represented by the change of hysteresis loops and remnant polarization. Three levels of electrical load amplitudes (1.00, 1.25 and 1.50 kV /mm) were applied in this experimental. It was found that the remnant polarization decreased significantly with the number of loading cycles. The degree of fatigue degradation depends on the amplitude of electric field. The higher amplitude exhibits the greater fatigue degradation.

Keywords: Lead Zirconate Titanate (PZT), hysteresis loop, Sawyer-Tower circuit, fatigue, polarization.

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242 Adaptive Sampling Algorithm for ANN-based Performance Modeling of Nano-scale CMOS Inverter

Authors: Dipankar Dhabak, Soumya Pandit

Abstract:

This paper presents an adaptive technique for generation of data required for construction of artificial neural network-based performance model of nano-scale CMOS inverter circuit. The training data are generated from the samples through SPICE simulation. The proposed algorithm has been compared to standard progressive sampling algorithms like arithmetic sampling and geometric sampling. The advantages of the present approach over the others have been demonstrated. The ANN predicted results have been compared with actual SPICE results. A very good accuracy has been obtained.

Keywords: CMOS Inverter, Nano-scale, Adaptive Sampling, ArtificialNeural Network

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241 Algorithmic Method for Efficient Cruise Program

Authors: Pelaez Verdet, Antonio, Loscertales Sanchez, Pilar

Abstract:

One of the mayor problems of programming a cruise circuit is to decide which destinations to include and which don-t. Thus a decision problem emerges, that might be solved using a linear and goal programming approach. The problem becomes more complex if several boats in the fleet must be programmed in a limited schedule, trying their capacity matches best a seasonal demand and also attempting to minimize the operation costs. Moreover, the programmer of the company should consider the time of the passenger as a limited asset, and would like to maximize its usage. The aim of this work is to design a method in which, using linear and goal programming techniques, a model to design circuits for the cruise company decision maker can achieve an optimal solution within the fleet schedule.

Keywords: Itinerary design, cruise programming, goalprogramming, linear programming

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240 Analysis and Experimentation of Interleaved Boost Converter with Ripple Steering for Power Factor Correction

Authors: A. Inba Rexy, R. Seyezhai

Abstract:

Through the fast growing technologies, design of power factor correction (PFC) circuit is facing several challenges. In this paper, a two-phase interleaved boost converter with ripple steering technique is proposed. Among the various topologies, Interleaved Boost converter (IBC) is considered as superior due to enriched performance, lower ripple content, compact weight and size. A thorough investigation is presented here for the proposed topology. Simulation study for the IBC has been carried out using MATLAB/SIMULINK. Theoretical analysis and hardware prototype has been performed to validate the results.

Keywords: Interleaved Boost Converter (IBC), Power Factor Correction (PFC), Ripple Steering Technique, Ripple, and Simulation.

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239 A Low Noise Microwave Filter with Minimum Distortion

Authors: Cheng Yuan Hung, Min Hang Weng, Siang Wen Lan, Wei Yu Chen, Hung Wei Wu, Chun Yueh Huang

Abstract:

In this paper, a low noise microwave bandpass filter (BPF) is presented. This filter is fabricated by modifying the conventional cross-coupled structure. The spurious response is improved by using the end open coupled lines, and the influence of the noise is minimized. Impedance matrix of the open end coupled circuit clarifies the characteristic of the suppression of the spurious response. The rejection of spurious suppression region of the proposed filter is greater than 20 dB from 3-13 GHz. The measured results of the fabricated filter confirm the concepts of the proposed design and exhibits high performance.

Keywords: Low noise, signal transmission, bandpass filter, end open coupled line, communication system.

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238 A Low-Area Fully-Reconfigurable Hardware Design of Fast Fourier Transform System for 3GPP-LTE Standard

Authors: Xin-Yu Shih, Yue-Qu Liu, Hong-Ru Chou

Abstract:

This paper presents a low-area and fully-reconfigurable Fast Fourier Transform (FFT) hardware design for 3GPP-LTE communication standard. It can fully support 32 different FFT sizes, up to 2048 FFT points. Besides, a special processing element is developed for making reconfigurable computing characteristics possible, while first-in first-out (FIFO) scheduling scheme design technique is proposed for hardware-friendly FIFO resource arranging. In a synthesis chip realization via TSMC 40 nm CMOS technology, the hardware circuit only occupies core area of 0.2325 mm2 and dissipates 233.5 mW at maximal operating frequency of 250 MHz.

Keywords: Reconfigurable, fast Fourier transform, single-path delay feedback, 3GPP-LTE.

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237 Realization of Electronically Tunable Current- Mode Multiphase Sinusoidal Oscillators Using CFTAs

Authors: Prungsak Uttaphut

Abstract:

An implementation of current-mode multiphase sinusoidal oscillators is presented. Using CFTA-based lossy integrators, odd and odd/even phase systems can be realized with following advantages. The condition of oscillation and frequency of oscillation can be orthogonally tuned. The high output impedances facilitate easy driving an external load without additional current buffers. The proposed MSOs provide odd or even phase signals that are equally spaced in phase and equal amplitude. The circuit requires one CFTA, one resistor and one grounded capacitor per phase without additional current amplifier. The results of PSPICE simulations using CMOS CFTA are included to verify theory.

Keywords: multiphase sinusoidal oscillator, current-mode, CFTA, lossy integrator

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236 Estimating the Technological Deviation Impact on the Value of the Output Parameter of the Induction Converter

Authors: Marinka K. Baghdasaryan, Siranush M. Muradyan, Avgen A. Gasparyan

Abstract:

Based on the experimental data, the impact of resistance and reactance of the winding, as well as the magnetic permeability of the magnetic circuit steel material on the value of the electromotive force of the induction converter is investigated. The obtained results allow estimating the main technological spreads and determining the maximum level of the electromotive force change. By the method of experiment planning, the expression of a polynomial for the electromotive force which can be used to estimate the adequacy of mathematical models to be used at the investigation and design of induction converters is obtained.

Keywords: Induction converter, electromotive force, expectation, technological spread, deviation, planning an experiment, polynomial, confidence level.

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235 14-Bit 1MS/s Cyclic-Pipelined ADC

Authors: S. Saisundar, Shan Jiang, Kevin T. C. Chai, David Nuttman, Minkyu Je

Abstract:

This paper presents a 14-bit cyclic-pipelined Analog to digital converter (ADC) running at 1 MS/s. The architecture is based on a 1.5-bit per stage structure utilizing digital correction for each stage. The ADC consists of two 1.5-bit stages, one shift register delay line, and digital error correction logic. Inside each 1.5-bit stage, there is one gain-boosting op-amp and two comparators. The ADC was implemented in 0.18µm CMOS process and the design has an area of approximately 0.2 mm2. The ADC has a differential input range of 1.2 Vpp. The circuit has an average power consumption of 3.5mA with 10MHz sampling clocks. The post-layout simulations of the design satisfy 12-bit SNDR with a full-scale sinusoid input.


Keywords: Analog to digital converter, cyclic, gain-boosting, pipelined.

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