14-Bit 1MS/s Cyclic-Pipelined ADC

Authors: S. Saisundar, Shan Jiang, Kevin T. C. Chai, David Nuttman, Minkyu Je

Abstract:

This paper presents a 14-bit cyclic-pipelined Analog to digital converter (ADC) running at 1 MS/s. The architecture is based on a 1.5-bit per stage structure utilizing digital correction for each stage. The ADC consists of two 1.5-bit stages, one shift register delay line, and digital error correction logic. Inside each 1.5-bit stage, there is one gain-boosting op-amp and two comparators. The ADC was implemented in 0.18µm CMOS process and the design has an area of approximately 0.2 mm². The ADC has a differential input range of 1.2 Vpp. The circuit has an average power consumption of 3.5mA with 10MHz sampling clocks. The post-layout simulations of the design satisfy 12-bit SNDR with a full-scale sinusoid input.

Keywords: Analog to digital converter, cyclic, gain-boosting, pipelined.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1335642

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