@article{(Open Science Index):https://publications.waset.org/pdf/16677, title = {14-Bit 1MS/s Cyclic-Pipelined ADC }, author = {S. Saisundar and Shan Jiang and Kevin T. C. Chai and David Nuttman and Minkyu Je }, country = {}, institution = {}, abstract = {This paper presents a 14-bit cyclic-pipelined Analog to digital converter (ADC) running at 1 MS/s. The architecture is based on a 1.5-bit per stage structure utilizing digital correction for each stage. The ADC consists of two 1.5-bit stages, one shift register delay line, and digital error correction logic. Inside each 1.5-bit stage, there is one gain-boosting op-amp and two comparators. The ADC was implemented in 0.18µm CMOS process and the design has an area of approximately 0.2 mm2. The ADC has a differential input range of 1.2 Vpp. The circuit has an average power consumption of 3.5mA with 10MHz sampling clocks. The post-layout simulations of the design satisfy 12-bit SNDR with a full-scale sinusoid input. }, journal = {International Journal of Electronics and Communication Engineering}, volume = {7}, number = {9}, year = {2013}, pages = {1190 - 1193}, ee = {https://publications.waset.org/pdf/16677}, url = {https://publications.waset.org/vol/81}, bibsource = {https://publications.waset.org/}, issn = {eISSN: 1307-6892}, publisher = {World Academy of Science, Engineering and Technology}, index = {Open Science Index 81, 2013}, }