Search results for: field-effect transistors

Authors: Pejman Hosseinioun, Ali Safari, Hamed Sarbazi

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Graphene is a one-atom-thick sheet of carbon with numerous impressive properties. It is a promising material for future high-speed nanoelectronics due to its intrinsic superior carrier mobility and very high saturation velocity. These exceptional carrier transport properties suggest that graphene field effect transistors (G-FETs) can potentially outperform other FET technologies. In this paper, detailed discussions are introduced for Graphene Transistors Based Microwave Amplifiers.

Keywords: graphene, microwave FETs, microwave amplifiers, transistors

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Authors: Robert Setekera, Ramses van der Toorn

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We present an extensive analysis of the temperature dependence of the local avalanche model used in most of the modern compact models for bipolar transistors. This local avalanche model uses the Chynoweth's empirical law for ionization coefficient to define the generation of the avalanche current in terms of the local electric field. We carry out the model analysis using DC-measurements taken on both Si and advanced SiGe bipolar transistors. For the advanced industrial SiGe-HBTs, we consider both high-speed and high-power devices (both NPN and PNP transistors). The limitations of the local avalanche model in modeling the temperature dependence of the avalanche current mostly in the weak avalanche region are demonstrated. In addition, the model avalanche parameters are analyzed to see if they are in agreement with semiconductor device physics.

Keywords: avalanche multiplication, avalanche current, bipolar transistors, compact modeling, electric field, impact ionization, local avalanche

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Authors: Yanan Zhu

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Based on the previous work about the influence mechanism of the mobility difference of phenyl and thienyl substituent semiconductors, we have made further exploration towards to design high-performance organic thin-film transistors. The substituent groups effect plays a significant role in materials properties and device performance as well. For the theoretical study, simulation of materials property and crystal packing can supply scientific guidance for materials synthesis in experiments. This time, we have taken the computational methods to design a new material substituent with furan groups, which are the potential to be used in organic thin-film transistors and organic single-crystal transistors. The reorganization energy has been calculated and much lower than 2,6-diphenyl anthracene (DPAnt), which performs large mobility as more than 30 cm²V⁻¹s⁻¹. Moreover, the other important parameter, charge transfer integral is larger than DPAnt, which suggested the furan substituent material may get a much better charge transport data. On the whole, the mechanism investigation based on phenyl and thienyl assisted in designing novel materials with furan substituent, which is predicted to be an outperformed organic field-effect transistors.

Keywords: theoretical calculation, mechanism, mobility, organic transistors

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Authors: Peihao Huang, Chun Zhao

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Thin-film transistors(TFTs) have the advantages of low power consumption, short reaction time, and have high research value in the field of semiconductors, based on this reason, people have focused on gallium oxide-indium oxide thin-film transistors, a relatively common thin-film transistor, elaborated and analyzed his production process, "aqueous solution method", explained the purpose of each step of operation, and finally explored the influence of potassium ions doped in the channel layer on the electrical properties of the device, as well as the effect of oxygen vacancies on its switching ratio and memory, and summarized the conclusions.

Keywords: aqueous solution, oxygen vacancies, switch ratio, thin-film transistor(TFT)

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Authors: S. Boorboor, S. A. H. Feghhi, H. Jafari

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The ionizing radiations cause different kinds of damages in electronic components. MOSFETs, most common transistors in today’s digital and analog circuits, are severely sensitive to TID damage. In this work, the threshold voltage shift of CD4007 device, which is an integrated circuit including P-channel and N-channel MOS transistors, was investigated for low dose gamma irradiation under different gate bias voltages. We used linear extrapolation method to extract threshold voltage from I_D-V_G characteristic curve. The results showed that the threshold voltage shift was approximately 27.5 mV/Gy for N-channel and 3.5 mV/Gy for P-channel transistors at the gate bias of |9 V| after irradiation by Co-60 gamma ray source. Although the sensitivity of the devices under test were strongly dependent to biasing condition and transistor type, the threshold voltage shifted linearly versus accumulated dose in all cases. The overall results show that the application of CD4007 as an electronic buffer in a radiation therapy system is limited by TID damage. However, this integrated circuit can be used as a cheap and sensitive radiation dosimeter for accumulated dose measurement in radiation therapy systems.

Keywords: threshold voltage shift, MOS transistor, linear extrapolation, gamma irradiation

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Authors: Petr Vaculik

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The newest semiconductor devices on the market are MOSFET transistors based on the silicon carbide – SiC. This material has exclusive features thanks to which it becomes a better switch than Si – silicon semiconductor switch. There are some special features that need to be understood to enable the device’s use to its full potential. The advantages and differences of SiC MOSFETs in comparison with Si IGBT transistors have been described in first part of this article. Second part describes driver for SiC MOSFET transistor and last part of article represents SiC MOSFET in the application of buck converter (step-down) and design of simple RC snubber.

Keywords: SiC, Si, MOSFET, IGBT, SBD, RC snubber

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Authors: Jingqi Li

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A new vertical carbon nanotube field effect transistor (CNTFET) has been developed. The source, drain and gate are vertically stacked in this structure. The carbon nanotubes are put on the side wall of the vertical stack. Unique transfer characteristics which depend on both silicon type and the sign of drain voltage have been observed in silicon integrated CNTFETs. The significant advantage of this CNTFET is that the short channel of the transistor can be fabricated without using complicate lithography technique.

Keywords: carbon nanotubes, field-effect transistors, electrical property, short channel fabrication

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Authors: Patikineti Sreenivasulu, K. srinivasa Rao, A. Vinaya Babu

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The demand for portability, performance and high functional integration density of digital devices leads to the scaling of complementary metal oxide semiconductor (CMOS) devices inevitable. The increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. MTCMOS technology provides low leakage and high performance operation by utilizing high speed, low Vt (LVT) transistors for logic cells and low leakage, high Vt (HVT) devices as sleep transistors. Sleep transistors disconnect logic cells from the supply and/or ground to reduce the leakage in the sleep mode. In this technology, energy consumption while doing the mode transition and minimum time required to turn ON the circuit upon receiving the wake up signal are issues to be considered because these can adversely impact the performance of VLSI circuit. In this paper we are introducing an enhancing method of MTCMOS technology to optimize the power in MTCMOS sequential circuits.

Keywords: power consumption, ultra-low power, leakage, sub threshold, MTCMOS

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Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza

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Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect.

Keywords: SOI technology, PDSOI MOSFET, FDSOI MOSFET, kink effect

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Authors: Mehdi Saeidmanesh, Razali Ismail

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Recently, Graphene Nanoribbon Field Effect Transistors (GNR FETs) attract a great deal of attention due to their better performance in comparison with conventional devices. In this paper, channel length Modulation (CLM) effect on the electrical characteristics of GNR FETs is analytically studied and modeled. To this end, the special distribution of the electric potential along the channel and current-voltage characteristic of the device is modeled. The obtained results of analytical model are compared to the experimental data of published works. As a result, it is observable that considering the effect of CLM, the current-voltage response of GNR FET is more realistic.

Keywords: graphene nanoribbon, field effect transistors, short channel effects, channel length modulation

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Authors: L. Boyaci

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Two basic equipment of electrical power subsystem of space satellites are Power Conditioning Unit (PCU) and Power Distribution Unit (PDU). Today, the main switching element used in power equipment in satellites is silicon (Si) based radiation-hardened MOSFET. GaNFETs have superior performances over MOSFETs in terms of their conduction and switching characteristics. GaNFET has started to take MOSFET’s place in many applications in industry especially by virtue of its switching performances. If GaNFET can also be used in equipment for space applications, this would be great revolution for future space power subsystem designs. In this study, the effect of proton irradiation on Gallium Nitride based power transistors was investigated. Four commercial enhancement mode GaN power transistors from Efficient Power Conversion Corporation (EPC) are irradiated with 30MeV protons while devices are switching. Flux of 8.2x10⁹ protons/cm²/s is applied for 12.5 seconds to reach ultimate fluence of 10¹¹ protons/cm². Vgs-Ids characteristics are measured and recorded for each device before, during and after irradiation. It was observed that if there would be destructive events. Proton induced permanent damage on devices is not observed. All the devices remained healthy and continued to operate. For two of these devices, further irradiation is applied with same flux for 30 minutes up to a total fluence level of 1.476x10¹³ protons/cm². We observed that GaNFETs are fully functional under this high level of radiation and no destructive events and irreversible failures took place for transistors. Results reveal that irradiated GaNFET in this experiment has radiation tolerance under proton testing and very important candidate for being one of the future power switching element in space.

Keywords: enhancement mode GaN power transistors, proton irradiation effects, radiation tolerance

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Authors: Davit Mirzoyan, Ararat Khachatryan

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A process corner monitoring circuit (PCMC) is presented in this work. The circuit generates a signal, the logical value of which depends on the process corner only. The signal can be used in both digital and analog circuits for testing and compensation of process variations (PV). The presented circuit uses only metal-oxide-semiconductor (MOS) transistors, which allow increasing its detection accuracy, decrease power consumption and area. Due to its simplicity the presented circuit can be easily modified to monitor parametrical variations of only n-type and p-type MOS (NMOS and PMOS, respectively) transistors, resistors, as well as their combinations. Post-layout simulation results prove correct functionality of the proposed circuit, i.e. ability to monitor the process corner (equivalently die-to-die variations) even in the presence of within-die variations.

Keywords: detection, monitoring, process corner, process variation

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Authors: MeiBo, ZhaoXing, LuoLei, YuQingkui, TangMin, HanZhengsheng

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The Single Event Transients (SETs) were investigated on 0.18μm PDSOI transistors and 100 series CMOS inverter chain using pulse laser. The effect of different laser energy and device bias for waveform on SET was characterized experimentally, as well as the generation and propagation of SET in inverter chain. In this paper, the effects of struck transistors type and struck locations on SETs were investigated. The results showed that when irradiate NMOSFETs from 100th to 2nd stages, the SET pulse width measured at the output terminal increased from 287.4 ps to 472.9 ps; and when irradiate PMOSFETs from 99th to 1st stages, the SET pulse width increased from 287.4 ps to 472.9 ps. When struck locations were close to the output of the chain, the SET pulse was narrow; however, when struck nodes were close to the input, the SET pulse was broadening. SET pulses were progressively broadened up when propagating along inverter chains. The SET pulse broadening is independent of the type of struck transistors. Through analysis, history effect induced threshold voltage hysteresis in PDSOI is the reason of pulse broadening. The positive pulse observed by oscilloscope, contrary to the expected results, is because of charging and discharging of capacitor.

Keywords: single event transients, pulse laser, partially-depleted silicon-on-insulator, propagation-induced pulse broadening effect

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Authors: Hefzollah Mohammadiyan, Mohammad Bagher Heidari, Ensiyeh Hajeb

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In this paper investigates and analyses the structure of nano sensors will be discussed. The structure can be classified based of nano sensors: quantum points, carbon nanotubes and nano tools, which details into each other and in turn are analyzed. Then will be fully examined to the Carbon nanotubes as chemical and mechanical sensors. The following discussion, be examined compares the advantages and disadvantages as different types of sensors and also it has feature and a wide range of applications in various industries. Finally, the structure and application of Chemical sensor transistors and the sensors will be discussed in air pollution control.

Keywords: carbon nanotubes, quantum points, chemical sensors, mechanical sensors, chemical sensor transistors, single walled nanotube (SWNT), atomic force microscope (AFM)

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Authors: Tomas Vincze, Michal Micjan, Milan Pavuk, Martin Weis

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In recent years, alternative materials are gaining attention to replace polycrystalline and amorphous silicon, which are a standard for low requirement devices, where silicon is unnecessarily and high cost. For that reason, metal oxides are envisioned as the new materials for these low-requirement applications such as sensors, solar cells, energy storage devices, or field-effect transistors. Their most common way of layer growth is sputtering; however, this is a high-cost fabrication method, and a more industry-suitable alternative is the sol-gel method. In this group of materials, many oxides exhibit a semiconductor-like behavior with sufficiently high mobility to be applied as transistors. The sol-gel method is a cost-effective deposition technique for semiconductor-based devices. Copper oxides, as p-type semiconductors with free charge mobility up to 1 cm2/Vs., are suitable replacements for poly-Si or a-Si:H devices. However, to reach the potential of silicon devices, a fine-tuning of material properties is needed. Here we focus on the optimization of the electrical parameters of copper oxide-based field-effect transistors by modification of precursor solvent (usually 2-methoxy ethanol). However, to achieve solubility and high-quality films, a better solvent is required. Since almost no solvents have both high dielectric constant and high boiling point, an alternative approach was proposed with blend solvents. By mixing isopropyl alcohol (IPA) and 2-methoxy ethanol (2ME) the precursor reached better solubility. The quality of the layers fabricated using mixed solutions was evaluated in accordance with the surface morphology and electrical properties. The IPA:2ME solution mixture reached optimum results for the weight ratio of 1:3. The cupric oxide layers for optimal mixture had the highest crystallinity and highest effective charge mobility.

Keywords: copper oxide, field-effect transistor, semiconductor, sol-gel method

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Authors: Daniel Bülz, Franziska Lüttich, Sreetama Banerjee, Georgeta Salvan, Dietrich R. T. Zahn

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For the development of electronics, organic semiconductors are of great interest due to their adjustable optical and electrical properties. Especially for spintronic applications they are interesting because of their weak spin scattering, which leads to longer spin life times compared to inorganic semiconductors. It was shown that some organic materials change their resistance if an external magnetic field is applied. Pentacene is one of the materials which exhibit the so called photoinduced magnetoresistance which results in a modulation of photocurrent when varying the external magnetic field. Also the soluble derivate of pentacene, the 6,13-bis (triisopropylsilylethynyl)-pentacene (TIPS-pentacene) exhibits the same negative magnetoresistance. Aiming for simpler fabrication processes, in this work, we compare TIPS-pentacene organic field effect transistors (OFETs) made from solution with those fabricated by thermal evaporation. Because of the different processing, the TIPS-pentacene thin films exhibit different morphologies in terms of crystal size and homogeneity of the substrate coverage. On the other hand, the interface treatment is known to have a high influence on the threshold voltage, eliminating trap states of silicon oxide at the gate electrode and thereby changing the electrical switching response of the transistors. Therefore, we investigate the influence of interface treatment using octadecyltrichlorosilane (OTS) or using a simple cleaning procedure with acetone, ethanol, and deionized water. The transistors consist of a prestructured OFET substrates including gate, source, and drain electrodes, on top of which TIPS-pentacene dissolved in a mixture of tetralin and toluene is deposited by drop-, spray-, and spin-coating. Thereafter we keep the sample for one hour at a temperature of 60 °C. For the transistor fabrication by thermal evaporation the prestructured OFET substrates are also kept at a temperature of 60 °C during deposition with a rate of 0.3 nm/min and at a pressure below 10-6 mbar. The OFETs are characterized by means of optical microscopy in order to determine the overall quality of the sample, i.e. crystal size and coverage of the channel region. The output and transfer characteristics are measured in the dark and under illumination provided by a white light LED in the spectral range from 450 nm to 650 nm with a power density of (8±2) mW/cm2.

Keywords: organic field effect transistors, solution processed, surface treatment, TIPS-pentacene

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Authors: Mahdiar Hosseighadiry, Farnaz Fotovatikhah, Razali Ismail, Mohsen Khaledian, Mehdi Saeidemanesh

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In this paper, a new low-power high-performance full adder is presented based on a new design method. The proposed method relies on pass gate design and provides full-swing circuits with minimum number of transistors. The method has been applied on SUM, COUT and XOR-XNOR modules resulting on rail-to-rail intermediate and output signals with no feedback transistors. The presented full adder cell has been simulated in 45 and 32 nm CMOS technologies using HSPICE considering parasitic capacitance and compared to several well-known designs from literature. In addition, the proposed cell has been extensively evaluated with different output loads, supply voltages, temperatures, threshold voltages, and operating frequencies. Results show that it functions properly under all mentioned conditions and exhibits less PDP compared to other design styles.

Keywords: full adders, low-power, high-performance, VLSI design

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Authors: Yu-Hsien Lin, Yu-Ru Lin, Yung-Chun Wu

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This work demonstrates the ultra-thin poly-Si (polycrystalline Silicon) nanowire junctionless thin film transistors (NWs JL-TFT) with nickel silicide contact. For nickel silicide film, this work designs to use two-step annealing to form ultra-thin, uniform and low sheet resistance (Rs) Ni silicide film. The NWs JL-TFT with nickel silicide contact exhibits the good electrical properties, including high driving current (>10⁷ Å), subthreshold slope (186 mV/dec.), and low parasitic resistance. In addition, this work also compares the electrical characteristics of NWs JL-TFT with nickel silicide and non-silicide contact. Nickel silicide techniques are widely used for high-performance devices as the device scaling due to the source/drain sheet resistance issue. Therefore, the self-aligned silicide (salicide) technique is presented to reduce the series resistance of the device. Nickel silicide has several advantages including low-temperature process, low silicon consumption, no bridging failure property, smaller mechanical stress, and smaller contact resistance. The junctionless thin-film transistor (JL-TFT) is fabricated simply by heavily doping the channel and source/drain (S/D) regions simultaneously. Owing to the special doping profile, JL-TFT has some advantages such as lower thermal the budget which can integrate with high-k/metal-gate easier than conventional MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), longer effective channel length than conventional MOSFETs, and avoidance of complicated source/drain engineering. To solve JL-TFT has turn-off problem, JL-TFT needs ultra-thin body (UTB) structure to reach fully depleted channel region in off-state. On the other hand, the drive current (Iᴅ) is declined as transistor features are scaled. Therefore, this work demonstrates ultra thin poly-Si nanowire junctionless thin film transistors with nickel silicide contact. This work investigates the low-temperature formation of nickel silicide layer by physical-chemical deposition (PVD) of a 15nm Ni layer on the poly-Si substrate. Notably, this work designs to use two-step annealing to form ultrathin, uniform and low sheet resistance (Rs) Ni silicide film. The first step was promoted Ni diffusion through a thin interfacial amorphous layer. Then, the unreacted metal was lifted off after the first step. The second step was annealing for lower sheet resistance and firmly merged the phase.The ultra-thin poly-Si nanowire junctionless thin film transistors NWs JL-TFT with nickel silicide contact is demonstrated, which reveals high driving current (>10⁷ Å), subthreshold slope (186 mV/dec.), and low parasitic resistance. In silicide film analysis, the second step of annealing was applied to form lower sheet resistance and firmly merge the phase silicide film. In short, the NWs JL-TFT with nickel silicide contact has exhibited a competitive short-channel behavior and improved drive current.

Keywords: poly-Si, nanowire, junctionless, thin-film transistors, nickel silicide

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Authors: Nikhil Jain, Yang Xu, Bin Yu

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Hexagonal boron nitride (h-BN) has been used as a substrate and gate dielectric for graphene field effect transistors (GFETs). Using a graphene/h-BN/TiN (channel/dielectric/gate) stack, key material properties of h-BN were investigated i.e. dielectric strength and tunneling behavior. Work function difference between graphene and TiN results in spontaneous p-doping of graphene through a multi-layer h-BN flake. However, at high levels of current stress, n-doping of graphene is observed, possibly due to the charge transfer across the thin h-BN multi layer. Neither Direct Tunneling (DT) nor Fowler-Nordheim Tunneling (FNT) was observed in TiN/h-BN/Au hetero structures with h-BN showing two distinct volatile conduction states before breakdown. Hexagonal boron nitride emerges as a material of choice for gate dielectrics in GFETs because of robust dielectric properties and high tunneling barrier.

Keywords: graphene, transistors, conduction, hexagonal boron nitride, dielectric strength, tunneling

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Authors: Antonis Constantinides, Christos Yiallouras, Christakis Damianou

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The application of today's semiconductor transistors in high power UHF DVB-T linear amplifiers has evolved significantly by utilizing LDMOS technology. This fact provides engineers with the option to design a single transistor signal amplifier which enables output power and linearity that was unobtainable previously using bipolar junction transistors or later type first generation MOSFETS. The quiescent current stability in terms of thermal variations of the LDMOS guarantees a robust operation in any topology of DVB-T signal amplifiers. Otherwise, progressively uncontrolled heat dissipation enhancement on the LDMOS case can degrade the amplifier’s crucial parameters in regards to the gain, linearity, and RF stability, resulting in dysfunctional operation or a total destruction of the unit. This paper presents one more sophisticated approach from the traditional biasing circuits used so far in LDMOS DVB-T amplifiers. It utilizes a microprocessor control technology, providing stability in topologies where IDQ must be perfectly accurate.

Keywords: LDMOS, amplifier, back-off, bias circuit

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Authors: Debabrata Bhadra, B. K. Chaudhuri

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The operation of organic thin film transistors (OFETs) with low voltage is currently a prevailing issue. We have fabricated anthracene thin-film transistor (TFT) with an ultrathin layer (~450nm) of Poly-vinylidene fluoride (PVDF)/CuO nanocomposites as a gate insulator. We obtained a device with excellent electrical characteristics at low operating voltages (<1V). Different layers of the film were also prepared to achieve the best optimization of ideal gate insulator with various static dielectric constant (εr ). Capacitance density, leakage current at 1V gate voltage and electrical characteristics of OFETs with a single and multi layer films were investigated. This device was found to have highest field effect mobility of 2.27 cm2/Vs, a threshold voltage of 0.34V, an exceptionally low sub threshold slope of 380 mV/decade and an on/off ratio of 106. Such favorable combination of properties means that these OFETs can be utilized successfully as voltages below 1V. A very simple fabrication process has been used along with step wise poling process for enhancing the pyroelectric effects on the device performance. The output characteristic of OFET after poling were changed and exhibited linear current-voltage relationship showing the evidence of large polarization. The temperature dependent response of the device was also investigated. The stable performance of the OFET after poling operation makes it reliable in temperature sensor applications. Such High-ε CuO/PVDF gate dielectric appears to be highly promising candidates for organic non-volatile memory and sensor field-effect transistors (FETs).

Keywords: organic field effect transistors, thin film transistor, gate dielectric, organic semiconductor

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Authors: Hamdi Belgacem, Fradi Aymen

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In this paper we present a low power, low cost differential logic unit (LU). The proposed LU receives dual-rail inputs and generates dual-rail outputs. The proposed circuit can be used in Arithmetic and Logic Units (ALU) of processor. It can be also dedicated for self-checking applications based on dual duplication code. Four logic functions as well as their inverses are implemented within a single Logic Unit. The hardware overhead for the implementation of the proposed LU is lower than the hardware overhead required for standard LU implemented with standard CMOS logic style. This new implementation is attractive as fewer transistors are required to implement important logic functions. The proposed differential logic unit can perform 8 Boolean logical operations by using only 16 transistors. Spice simulations using a 32 nm technology was utilized to evaluate the performance of the proposed circuit and to prove its acceptable electrical behaviour.

Keywords: differential logic unit, double pass transistor logic, low power CMOS design, low cost CMOS design

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Authors: Kittipong Tripetch, Nobuhiko Nakano

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Two types of floating active resistors based on a complementary regulated cascode topology with cross-coupled regulated transistors are presented in this paper. The first topology is a high swing complementary regulated cascode active resistor. The second topology is a complementary common gate with a regulated cross coupled transistor. The small-signal input resistances of the floating resistors are derived. Three graphs of the input current versus the input voltage for different aspect ratios are designed and plotted using the Cadence Spectre 0.18-µm Rohm Semiconductor process. The total harmonic distortion graphs are plotted for three different aspect ratios with different input-voltage amplitudes and different input frequencies. From the simulation results, it is observed that a resistance of approximately 8.52 MΩ can be obtained from supply voltage at  ±0.9 V.

Keywords: floating active resistor, complementary common gate, complementary regulated cascode, current mirror

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Authors: Nikhil Jain, Bin Yu

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We explore the potential of using ultra-thin hexagonal boron nitride (h-BN) as both supporting substrate and gate dielectric for graphene-channel field effect transistors (GFETs). Different from commonly used oxide-based dielectric materials which are typically amorphous, very rough in surface, and rich with surface traps, h-BN is layered insulator free of dangling bonds and surface states, featuring atomically smooth surface. In a graphene-channel-last device structure with local buried metal gate electrode (TiN), thin h-BN multilayer is employed as both supporting “substrate” and gate dielectric for graphene active channel. We observed superior carrier mobility and electrical conduction, significantly improved from that in GFETs with SiO2 as substrate/gate insulator. In addition, we report excellent dielectric behavior of layered h-BN, including ultra-low leakage current and high critical electric field for breakdown.

Keywords: graphene, field-effect transistors, hexagonal boron nitride, dielectric strength, tunneling

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Authors: Samson Mil'shtein, Dhawal Asthana, Benjamin Sullivan

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The wide energy gap of GaN is the major parameter justifying the design and fabrication of high-power electronic components made of this material. However, the existence of a piezo-electrics in nature sheet charge at the AlGaN/GaN interface complicates the control of carrier injection into the intrinsic channel of GaN HEMTs (High Electron Mobility Transistors). As a result, most of the transistors created as R&D prototypes and all of the designs used for mass production are D-mode devices which introduce challenges in the design of integrated circuits. This research presents the design and modeling of an E-mode GaN HEMT with a very low turn-on voltage. The proposed device includes two critical elements allowing the transistor to achieve zero conductance across the channel when Vg = 0V. This is accomplished through the inclusion of an extremely thin, 2.5nm intrinsic Ga₀.₇₄Al₀.₂₆N spacer layer. The added spacer layer does not create piezoelectric strain but rather elastically follows the variations of the crystal structure of the adjacent GaN channel. The second important factor is the design of a gate metal with a high work function. The use of a metal gate with a work function (Ni in this research) greater than 5.3eV positioned on top of n-type doped (Nd=10¹⁷cm⁻³) Ga₀.₇₄Al₀.₂₆N creates the necessary built-in potential, which controls the injection of electrons into the intrinsic channel as the gate voltage is increased. The 5µm long transistor with a 0.18µm long gate and a channel width of 30µm operate at Vd=10V. At Vg =1V, the device reaches the maximum drain current of 0.6mA, which indicates a high current density. The presented device is operational at frequencies greater than 10GHz and exhibits a stable transconductance over the full range of operational gate voltages.

Keywords: compound semiconductors, device modeling, enhancement mode HEMT, gallium nitride

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Authors: Abdelmadjid Mammeri, Fatima Zohra Mahi, Luca Varani, H. Marinchoi

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We propose an analytical model for the admittance and the noise calculations of the InGaAs transistor and diode. The development of the small-signal admittance takes into account the longitudinal and transverse electric fields through a pseudo two-dimensional approximation of the Poisson equation. The frequency-dependent of the small-signal admittance response is determined by the total currents and the potentials matrix relation between the gate and the drain terminals. The noise is evaluated by using the real part of the transistor/diode admittance under a small-signal perturbation. The analytical results show that the admittance spectrum exhibits a series of resonant peaks corresponding to the excitation of plasma waves. The appearance of the resonance is discussed and analyzed as functions of the channel length and the temperature. The model can be used, on one hand; to control the appearance of the plasma resonances, and on other hand; can give significant information about the noise frequency dependence in the InGaAs transistor and diode.

Keywords: InGaAs transistors, InGaAs diode, admittance, resonant peaks, plasma waves, analytical model

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Authors: Lin Gong, Holger Göbel

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In the present study, we have investigated the influence of UV/ozone treatment on pentacene-based organic field effect transistors (OFETs) with a bilayer gate dielectric. The OFETs for this study were fabricated on heavily n-doped Si substrates with a thermally deposited SiO2 dielectric layer (300nm). On the SiO2 dielectric a very thin (≈ 15nm) buffer layer of polystyrene (PS) was first spin-coated and then treated by UV/ozone to modify the surface prior to the deposition of pentacene. We found out that by extending the UV/ozone treatment time the threshold voltage of the OFETs was monotonically shifted towards positive values, whereas the field effect mobility first decreased but eventually reached a stable value after a treatment time of approximately thirty seconds. Since the field effect mobility of the UV/ozone treated bilayer OFETs was found to be higher than the value of a comparable transistor with a single layer dielectric, we propose that the bilayer (SiO2/PS) structure can be used to shift the threshold voltage to a desired value without sacrificing field effect mobility.

Keywords: buffer layer, organic field effect transistors, threshold voltage, UV/ozone treatment

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Authors: Sibani Bisoyi, Ute Zschieschang, Alexander Hoyer, Hagen Klauk

Abstract:

Abstract— Organic thin-film transistors (TFTs) have great potential to be used for various applications such as flexible displays or sensors. For some of these applications, the TFTs must be able to withstand temperatures in excess of 100 °C, for example to permit the integration with devices or components that require high process temperatures, or to make it possible that the devices can be subjected to the standard sterilization protocols required for biomedical applications. In this work, we have investigated how the thermal stability of low-voltage small-molecule semiconductor dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]thiophene (DNTT) TFTs is affected by the encapsulation of the TFTs and by the ambient in which the thermal stress is performed. We also studied to which extent the thermal stability of the TFTs depends on the channel length. Some of the TFTs were encapsulated with a layer of vacuum-deposited Teflon, while others were left without encapsulation, and the thermal stress was performed either in nitrogen or in air. We found that the encapsulation with Teflon has virtually no effect on the thermal stability of our TFTs. In contrast, the ambient in which the thermal stress is conducted was found to have a measurable effect, but in a surprising way: When the thermal stress is carried out in nitrogen, the mobility drops to 70% of its initial value at a temperature of 160 °C and to close to zero at 170 °C, whereas when the stress is performed in air, the mobility remains at 75% of its initial value up to a temperature of 160 °C and at 60% up to 180 °C. To understand this behavior, we studied the effect of the thermal stress on the semiconductor thin-film morphology by scanning electron microscopy. While the DNTT films remain continuous and conducting when the heating is carried out in air, the semiconductor morphology undergoes a dramatic change, including the formation of large, thick crystals of DNTT and a complete loss of percolation, when the heating is conducted in nitrogen. We also found that when the TFTs are heated to a temperature of 200 °C in air, all TFTs with a channel length greater than 50 µm are destroyed, while TFTs with a channel length of less than 50 µm survive, whereas when the TFTs are heated to the same temperature (200 °C) in nitrogen, only the TFTs with a channel smaller than 8 µm survive. This result is also linked to the thermally induced changes in the semiconductor morphology.

Keywords: organic thin-film transistors, encapsulation, thermal stability, thin-film morphology

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Authors: Chhavi Saxena

Abstract:

FinFETs can be a replacement for bulk-CMOS transistors in many different designs. Its low leakage/standby power property makes FinFETs a desirable option for memory sub-systems. Memory modules are widely used in most digital and computer systems. Leakage power is very important in memory cells since most memory applications access only one or very few memory rows at a given time. As technology scales down, the importance of leakage current and power analysis for memory design is increasing. In this paper, we discover an option for low power interconnect synthesis at the 32nm node and beyond, using Fin-type Field-Effect Transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a mechanism for improving FinFETs efficiency, called variable supply voltage schemes. In this paper, we’ve illustrated the design and implementation of FinFET based 4x4 SRAM cell array by means of one bit 7T SRAM. FinFET based 7T SRAM has been designed and analysis have been carried out for leakage current, dynamic power and delay. For the validation of our design approach, the output of FinFET SRAM array have been compared with standard CMOS SRAM and significant improvements are obtained in proposed model.

Keywords: FinFET, 7T SRAM cell, leakage current, delay

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Authors: Y. Lu, L. Liu, J. Guo

Abstract:

Monolayer graphene and dichaclogenide semiconductor materials attract extensive research interest for potential nanoelectronics applications. The ultimate scaling limit of double gate MoS2 Field-Effect-Transistors (FETs) with a monolayer thin body is examined and compared with ultra-thin-body Si FETs by using self-consistent quantum transport simulation in the presence of phonon scattering. Modelling of phonon scattering, quantum mechanical effects, and self-consistent electrostatics allows us to accurately assess the performance potential of monolayer MoS2 FETs. The results revealed that monolayer MoS2 FETs show 52% smaller Drain Induced Barrier Lowering (DIBL) and 13% Smaller Sub-Threshold Swing (SS) than 3 nm-thick-body Si FETs at a channel length of 10 nm with the same gating. With a requirement of SS<100mV/dec, the scaling limit of monolayer MoS2 FETs is assessed to be 5 nm, comparing with 8nm of the ultra-thin-body Si counterparts due to the monolayer thin body and higher effective mass which reduces direct source-to-drain tunnelling. By comparing with the ITRS target for high performance logic devices of 2023; double gate monolayer MoS2 FETs can fulfil the ITRS requirements.

Keywords: nanotransistors, monolayer 2D materials, quantum transport, scaling limit

Procedia PDF Downloads 234