Search results for: threshold voltage

Authors: S. Boorboor, S. A. H. Feghhi, H. Jafari

Abstract:

The ionizing radiations cause different kinds of damages in electronic components. MOSFETs, most common transistors in today’s digital and analog circuits, are severely sensitive to TID damage. In this work, the threshold voltage shift of CD4007 device, which is an integrated circuit including P-channel and N-channel MOS transistors, was investigated for low dose gamma irradiation under different gate bias voltages. We used linear extrapolation method to extract threshold voltage from I_D-V_G characteristic curve. The results showed that the threshold voltage shift was approximately 27.5 mV/Gy for N-channel and 3.5 mV/Gy for P-channel transistors at the gate bias of |9 V| after irradiation by Co-60 gamma ray source. Although the sensitivity of the devices under test were strongly dependent to biasing condition and transistor type, the threshold voltage shifted linearly versus accumulated dose in all cases. The overall results show that the application of CD4007 as an electronic buffer in a radiation therapy system is limited by TID damage. However, this integrated circuit can be used as a cheap and sensitive radiation dosimeter for accumulated dose measurement in radiation therapy systems.

Keywords: threshold voltage shift, MOS transistor, linear extrapolation, gamma irradiation

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Authors: Deepika Sharma, Bal Krishan

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In this paper, the structure of N-channel VDMOS was designed and analyzed using Silvaco TCAD tools by varying N+ source doping concentration, P-Body doping concentration, gate oxide thickness and the diffuse time. VDMOS is considered to be ideal power switches due to its high input impedance and fast switching speed. The performance of the device was analyzed from the Ids vs Vgs curve. The electrical characteristics such as threshold voltage, gate oxide thickness and breakdown voltage for the proposed device structures were extarcted. Effect of epitaxial layer on various parameters is also observed.

Keywords: on-resistance, threshold voltage, epitaxial layer, breakdown voltage

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Authors: Jae-Chang Kwak, Yong-Seo Koo

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The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.

Keywords: DT-CMOS, PMIC, PFM, DC-DC converter

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Authors: Hafez Fouad

Abstract:

Telemedicine applications have very low voltage which required High Precision Rectifier Design with high Sensitivity to operate at minimum input Voltage. In this work, we targeted 0.2V input voltage using 65 nm CMOS rectifier for Energy Harvesting Telemedicine application. The proposed rectifier which designed at 2.4GHz using two-stage structure found to perform in a better case where minimum operation voltage is lower than previous published paper and the rectifier can work at a wide range of low input voltage amplitude. The Performance Summary of Full-wave fully gate cross-coupled rectifiers (FWFR) CMOS Rectifier at F = 2.4 GHz: The minimum and maximum output voltages generated using an input voltage amplitude of 2 V are 490.9 mV and 1.997 V, maximum VCE = 99.85 % and maximum PCE = 46.86 %. The Performance Summary of Differential drive CMOS rectifier with external bootstrapping circuit rectifier at F = 2.4 GHz: The minimum and maximum output voltages generated using an input voltage amplitude of 2V are 265.5 mV (0.265V) and 1.467 V respectively, maximum VCE = 93.9 % and maximum PCE= 15.8 %.

Keywords: energy harvesting, embedded system, IoT telemedicine system, threshold voltage minimization, differential drive cmos rectifier, full-wave fully gate cross-coupled rectifiers CMOS rectifier

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Authors: Liqian Li, Yu Liu, Karen Colins

Abstract:

The dose rate present in a seriously contaminated area can be indirectly determined by monitoring radiation damage to inexpensive commercial electronics, instead of deploying expensive radiation hardened sensors. EEPROMs (Electrically Erasable Read Only Memories) are a good candidate for this purpose because they are inexpensive and are sensitive to radiation exposure. When the total ionizing dose threshold is reached, an EEPROM chip will show signs of damage that can be monitored and transmitted by less susceptible electronics. The dose rate can then be determined from the known threshold dose and the exposure time, assuming the radiation field remains constant with time. Therefore, the threshold dose needs to be well understood before this method can be used. There are many factors affecting the threshold dose, such as the gamma ray energy spectrum, the operating voltage, etc. The purpose of this study was to experimentally determine how the threshold dose depends on dose rate, temperature, voltage, and duty factor. It was found that the duty factor has the strongest effect on the total ionizing dose threshold, while the effect of the other three factors that were investigated is less significant. The effect of temperature was found to be opposite to that expected to result from annealing and is yet to be understood.

Keywords: EEPROM, ionizing radiation, radiation effects on electronics, total ionizing dose, wireless sensor networks

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Authors: Lin Gong, Holger Göbel

Abstract:

In the present study, we have investigated the influence of UV/ozone treatment on pentacene-based organic field effect transistors (OFETs) with a bilayer gate dielectric. The OFETs for this study were fabricated on heavily n-doped Si substrates with a thermally deposited SiO2 dielectric layer (300nm). On the SiO2 dielectric a very thin (≈ 15nm) buffer layer of polystyrene (PS) was first spin-coated and then treated by UV/ozone to modify the surface prior to the deposition of pentacene. We found out that by extending the UV/ozone treatment time the threshold voltage of the OFETs was monotonically shifted towards positive values, whereas the field effect mobility first decreased but eventually reached a stable value after a treatment time of approximately thirty seconds. Since the field effect mobility of the UV/ozone treated bilayer OFETs was found to be higher than the value of a comparable transistor with a single layer dielectric, we propose that the bilayer (SiO2/PS) structure can be used to shift the threshold voltage to a desired value without sacrificing field effect mobility.

Keywords: buffer layer, organic field effect transistors, threshold voltage, UV/ozone treatment

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Authors: Rajesh Agarwal

Abstract:

Carrier mobility at the organic/insulator interface is essential to the performance of organic thin film transistors (OTFT). The present work describes estimation of field dependent mobility (FDM) parameters and the threshold voltage of an OTFT using a simple, easy to fabricate two terminal asymmetric capacitive test structure using admittance measurements. Conventionally, transfer characteristics are used to estimate the threshold voltage in an OTFT with field independent mobility (FIDM). Yet, this technique breaks down to give accurate results for devices with high contact resistance and having field dependent mobility. In this work, a new technique is presented for characterization of long channel organic capacitor (LCOC). The proposed technique helps in the accurate estimation of mobility enhancement factor (γ), the threshold voltage (V_th) and band mobility (µ₀) using capacitance-voltage (C-V) measurement in OTFT. This technique also helps to get rid of making short channel OTFT or metal-insulator-metal (MIM) structures for making C-V measurements. To understand the behavior of devices and ease of analysis, transmission line compact model is developed. The 2-D numerical simulation was carried out to illustrate the correctness of the model. Results show that proposed technique estimates device parameters accurately even in the presence of contact resistance and field dependent mobility. Pentacene/Poly (4-vinyl phenol) based top contact bottom-gate OTFT’s are fabricated to illustrate the operation and advantages of the proposed technique. Small signal of frequency varying from 1 kHz to 5 kHz and gate potential ranging from +40 V to -40 V have been applied to the devices for measurement.

Keywords: capacitance, mobility, organic, thin film transistor

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Authors: Ajay Kumar, Neha Gupta

Abstract:

This work presents the sensitivity assessment of Gallium Nitride (GaN) material-based FinFET by dielectric modulation in the nanocavity gap for label-free biosensing applications. The significant deflection is observed in the electrical characteristics such as drain current (ID), transconductance (gm), surface potential, energy band profile, electric field, sub-threshold slope (SS), and threshold voltage (Vth) in the presence of biomolecules owing to GaN material. Further, the device sensitivity is evaluated to identify the effectiveness of the proposed biosensor and its capability to detect the biomolecules with high precision or accuracy. Higher sensitivity is observed for Gelatin (k=12) in terms of on-current (SION), threshold voltage (SVth), and switching ratio (SSR) by 104.88%, 82.12%, and 119.73%, respectively. This work is performed using a powerful tool 3D Sentaurus TCAD using a well-calibrated structure. All the results pave the way for GaN-FinFET as a viable candidate for label-free dielectric modulated biosensor applications.

Keywords: biosensor, biomolecules, FinFET, sensitivity

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Authors: Hani Baek, Gwang Min Sun, Chansun Shin, Sung Ho Ahn

Abstract:

Fast neutron irradiation using nuclear reactors is an effective method to improve switching loss and short circuit durability of power semiconductor (insulated gate bipolar transistors (IGBT) and insulated gate transistors (IGT), etc.). However, not only fast neutrons but also thermal neutrons, epithermal neutrons and gamma exist in the nuclear reactor. And the electrical properties of the IGBT may be deteriorated by the irradiation of gamma. Gamma irradiation damages are known to be caused by Total Ionizing Dose (TID) effect and Single Event Effect (SEE), Displacement Damage. Especially, the TID effect deteriorated the electrical properties such as leakage current and threshold voltage of a power semiconductor. This work can confirm the effect of the gamma irradiation on the electrical properties of 600 V NPT-IGBT. Irradiation of gamma forms lattice defects in the gate oxide and Si-SiO₂ interface of the IGBT. It was confirmed that this lattice defect acts on the center of the trap and affects the threshold voltage, thereby negatively shifted the threshold voltage according to TID. In addition to the change in the carrier mobility, the conductivity modulation decreases in the n-drift region, indicating a negative influence that the forward voltage drop decreases. The turn-off delay time of the device before irradiation was 212 ns. Those of 2.5, 10, 30, 70 and 100 kRad(Si) were 225, 258, 311, 328, and 350 ns, respectively. The gamma irradiation increased the turn-off delay time of the IGBT by approximately 65%, and the switching characteristics deteriorated.

Keywords: NPT-IGBT, gamma irradiation, switching, turn-off delay time, recombination, trap center

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Authors: M. Fadlallah, G. Ghibaudo, C. G. Theodorou

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The dynamic variation in memory devices such as the Static Random Access Memory can give errors in read or write operations. In this paper, the effect of low-frequency and random telegraph noise on the dynamic variation of one SRAM cell is detailed. The effect on circuit noise, speed, and length of time of processing is examined, using the Supply Read Retention Voltage and the Read Static Noise Margin. New test run methods are also developed. The obtained results simulation shows the importance of noise caused by dynamic variation, and the impact of Random Telegraph noise on SRAM variability is examined by evaluating the statistical distributions of Random Telegraph noise amplitude in the pull-up, pull-down. The threshold voltage mismatch between neighboring cell transistors due to intrinsic fluctuations typically contributes to larger reductions in static noise margin. Also the contribution of each of the SRAM transistor to total dynamic variation has been identified.

Keywords: low-frequency noise, random telegraph noise, dynamic variation, SRRV

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Authors: Rohana Musa, Yuzman Yusoff, Chia Chieu Yin, Hanif Che Lah

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This paper presents the design and characterization of a low power Complementary Metal Oxide Semiconductor (CMOS) process sensor. The design is targeted for implementation using Silterra’s 180 nm CMOS process technology. The proposed process sensor employs a voltage threshold (V_th) extractor architecture for detection of variations in the fabrication process. The process sensor generates output voltages in the range of 401 mV (fast-fast corner) to 443 mV (slow-slow corner) at nominal condition. The power dissipation for this process sensor is 6.3 µW with a supply voltage of 1.8V with a silicon area of 190 µm X 60 µm. The preliminary result of this process sensor that was fabricated indicates a close resemblance between test and simulated results.

Keywords: CMOS process sensor, PVT sensor, threshold extractor circuit, Vth extractor circuit

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Authors: B. Manoj Kumar, C. Malavika, E. S. Kannan

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The objective of this study is to investigate the switching behavior of two vertically aligned memristors connected by a shared top electrode, a configuration that significantly deviates from the conventional single oxide layer sandwiched between two electrodes. The device is fabricated by bridging copper electrodes with mechanically exfoliated van der Waals metal (specifically tantalum disulfide and tantalum diselenide). The device demonstrates threshold-switching behavior in its I-V characteristics. When the input voltage signal is ramped with voltages below the threshold, the output current shows spiking behavior, resembling integrated and firing actions without extra circuitry. We also investigated the self-reset behavior of the device. Using a continuous constant voltage bias, we activated the device to the firing state. After removing the bias and reapplying it shortly afterward, the current returned to its initial state. This indicates that the device can spontaneously return to its resting state. The outcome of this investigation offers a fresh perspective on memristor-based device design and an efficient method to construct hardware for neuromorphic computing systems.

Keywords: integrated and firing, memristor, spiking behavior, threshold switching

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Authors: Seyed Ahmad Mojallal

Abstract:

Let G be a connected threshold graph of order n with m edges and trace T. In this talk we give a lower bound on Laplacian energy in terms of n, m, and T of G. From this we determine the threshold graphs with the first four minimal Laplacian energies. We also list the first 20 minimal Laplacian energies among threshold graphs. Let σ=σ(G) be the number of Laplacian eigenvalues greater than or equal to average degree of graph G. Using this concept, we obtain the threshold graphs with the largest and the second largest Laplacian energies.

Keywords: Laplacian eigenvalues, Laplacian energy, threshold graphs, extremal graphs

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Authors: Young-San Shin, Seongsoo Lee

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Hall sensor is widely used to measure rotation angle. When the Hall voltage is measured for linear displacement, it is converted to angular displacement using arctangent function, which requires a large lookup table. In this paper, a lookup table reduction technique is presented for angle measurement. When the input of the lookup table is small within a certain threshold, the change of the outputs with respect to the change of the inputs is relatively small. Thus, several inputs can share same output, which significantly reduce the lookup table size. Its error analysis was also performed, and the threshold was determined so as to maintain the error less than 1°. When the Hall voltage has 11-bit resolution, the lookup table size is reduced from 1,024 samples to 279 samples.

Keywords: hall sensor, angle measurement, lookup table, arctangent

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Authors: Bo Bae Song, Byung Seok Lee, Hyun young Kim, Chung Kwang Lee, Yong Seo Koo

Abstract:

This paper proposed a silicon controller rectifier (SCR) based ESD protection device to protect low voltage ESD for integrated circuit. The proposed ESD protection device has low trigger voltage and high holding voltage compared with conventional SCR-based ESD protection devices. The proposed ESD protection circuit is verified and compared by TCAD simulation. This paper verified effective low voltage ESD characteristics with low trigger voltage of 5.79V and high holding voltage of 3.5V through optimization depending on design variables (D1, D2, D3, and D4).

Keywords: ESD, SCR, holding voltage, latch-up

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Authors: Atabak Faramarzpour, Mohsen Mohammadian

Abstract:

In this article, we introduce the stability of power system voltage and state DG power plants placement and its effect on improving voltage security margin in radial distribution networks. For this purpose, first, important definitions in voltage stability area such as small and big voltage disturbances, instability, and voltage collapse, and voltage security definitions are stated. Then, according to voltage collapse time, voltage stability is classified and each one's characteristics are stated.

Keywords: DG power plants, evaluation, voltage security, radial distribution networks

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Authors: Debabrata Bhadra, B. K. Chaudhuri

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The operation of organic thin film transistors (OFETs) with low voltage is currently a prevailing issue. We have fabricated anthracene thin-film transistor (TFT) with an ultrathin layer (~450nm) of Poly-vinylidene fluoride (PVDF)/CuO nanocomposites as a gate insulator. We obtained a device with excellent electrical characteristics at low operating voltages (<1V). Different layers of the film were also prepared to achieve the best optimization of ideal gate insulator with various static dielectric constant (εr ). Capacitance density, leakage current at 1V gate voltage and electrical characteristics of OFETs with a single and multi layer films were investigated. This device was found to have highest field effect mobility of 2.27 cm2/Vs, a threshold voltage of 0.34V, an exceptionally low sub threshold slope of 380 mV/decade and an on/off ratio of 106. Such favorable combination of properties means that these OFETs can be utilized successfully as voltages below 1V. A very simple fabrication process has been used along with step wise poling process for enhancing the pyroelectric effects on the device performance. The output characteristic of OFET after poling were changed and exhibited linear current-voltage relationship showing the evidence of large polarization. The temperature dependent response of the device was also investigated. The stable performance of the OFET after poling operation makes it reliable in temperature sensor applications. Such High-ε CuO/PVDF gate dielectric appears to be highly promising candidates for organic non-volatile memory and sensor field-effect transistors (FETs).

Keywords: organic field effect transistors, thin film transistor, gate dielectric, organic semiconductor

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Authors: Hee-Guk Chae, Bo-Bae Song, Kyoung-Il Do, Jeong-Yun Seo, Yong-Seo Koo

Abstract:

In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

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Authors: Yu Li, Dongyao Wang, Xiaobao Sun, Wei Ni

Abstract:

In long-term evolution (LTE), the carriers around 5GHz are planned to be utilized without licenses to further enlarge system capacity. This feature is termed licensed assisted access (LAA). The channel sensing (clean channel assessment, CCA) is required before any transmission on these unlicensed carriers, in order to make sure the harmonious co-existence of LAA with other radio access technology in the unlicensed band. Obviously, the CCA threshold is very critical, which decides whether the transmission right following CCA is delivered in time and without collisions. An improper CCA threshold may cause buffer overflow of some eNodeBs if the eNodeBs are heavily loaded with the traffic. Thus, to solve these problems, we propose an adaptive threshold adjustment method for CCA in the LAA downlink. Both the load and transmission opportunities are concerned. The trend of the LAA throughput as the threshold varies is obtained, which guides the threshold adjustment. The co-existing between LAA and Wi-Fi is particularly tested. The results from system-level simulation confirm the merits of our design, especially in heavy traffic cases.

Keywords: LTE, LAA, CCA, threshold adjustment

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Authors: Sun-Ki Hong, Nam-HeeByeon, Jung-Seop Lee, Tae-Sam Kang

Abstract:

For Common R or R-L load to apply arbitrary voltage, the bridge traditional inverters don’t have any difficulties by PWM method. However for driving some piezoelectric actuator, arbitrary voltage not a pulse but a steady voltage should be applied. Piezoelectric load is considered as R-C load and its voltage does not decrease even though the applied voltage decreases. Therefore it needs some special inverter with circuit that can discharge the capacitive energy. Especially for unidirectional arbitrary voltage driving like as sine wave, it becomes more difficult problem. In this paper, a charge and discharge circuit for unidirectional arbitrary voltage driving for piezoelectric actuator is proposed. The circuit has charging and discharging switches for increasing and decreasing output voltage. With the proposed simple circuit, the load voltage can have any unidirectional level with tens of bandwidth because the load voltage can be adjusted by switching the charging and discharging switch appropriately. The appropriateness is proved from the simulation of the proposed circuit.

Keywords: DC-DC converter, analog output voltage, sinusoidal drive, piezoelectric load, discharging circuit

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Authors: Zahira Anane, Abdelhafid Bayadi

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Corona in the HV overhead transmission lines is an important source of attenuation and distortion of overvoltage surges. This phenomenon of distortion, which is superimposed on the distortion by skin effect, is due to the dissipation of energy by injection of space charges around the conductor, this process with place as soon as the instantaneous voltage exceeds the threshold voltage of the corona effect conductors. This paper presents a mathematical model to determine the corona inception voltage, the critical electric field and the corona radius, to predict the capacitive changes at conductor of transmission line due to corona. This model has been incorporated into the Alternative Transients Program version of the Electromagnetic Transients Program (ATP/EMTP) as a user defined component, using the MODELS interface with NORTON TYPE94 of this program and using the foreign subroutine. For obtained the displacement of corona charge hell, dichotomy mathematical method is used for this computation. The present corona model can be used for computing of distortion and attenuation of transient overvoltage waves being propagated in a transmission line of the very high voltage electric power.

Keywords: high voltage, corona, Type94 NORTON, dichotomy, ATP/EMTP, MODELS, distortion, foreign model

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Authors: Junhong Feng, Wenyu Lu, Xinhong Cheng, Li Zheng, Yuehui Yu

Abstract:

The effects of proton irradiation on the properties of gate oxide were evaluated by monitoring the static parameters (such as threshold voltage and on-resistance) and dynamic parameters (Miller plateau time) of 1700V SiC VDMOS before and after proton irradiation. The incident proton energy was 3MeV, and the doses were 5 × 10¹² P / cm², 1 × 10¹³ P / cm², respectively. The results show that the threshold voltage of MOS exhibits negative drift under proton irradiation, and the near-interface traps in the gate oxide layer are occupied by holes generated by the ionization effect of irradiation, thus forming more positive charges. The basis for selecting TMiller is that the change time of Vgs is the time when Vds just shows an upward trend until it rises to a stable value. The degradation of the turn-off time of the Miller platform verifies that the capacitance Cgd becomes larger, reflecting that the gate oxide layer is introduced into the trap by the displacement effect caused by proton irradiation, and the interface state deteriorates. As a more sensitive area in the irradiation process, the gate oxide layer will be optimized for its parameters (such as thickness, type, etc.) in subsequent studies.

Keywords: SiC VDMOS, proton radiation, Miller time, gate oxide

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Authors: Hyun Young Kim, Chung Kwang Lee, Han Hee Cho, Sang Woon Cho, Yong Seo Koo

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In this paper, we proposed a novel SCR (Silicon Controlled Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O and power clamp. The proposed device has a higher holding voltage characteristic than conventional SCR. These characteristics enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in term of individual design parameters (D1, D2, D3). They are investigated by using the Synopsys TCAD simulator. As a result of simulation, holding voltage increased with different design parameters. The holding voltage of the proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD device with the high holding voltage is proposed. In the simulation results, 2-stack has holding voltage of 6.8V and 3-stack has holding voltage of 10.5V. The simulation results show that holding voltage of stacking structure can be larger than the operation voltage of high-voltage application.

Keywords: ESD, SCR, holding voltage, stack, power clamp

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Authors: Kwan-Ho Kim, Jin-Hong Park

Abstract:

The multi-valued logic (MVL) circuits, which can handle more than two logic states, are one of the promising solutions to overcome the bit density limitations of conventional binary logic systems. Recently, tunneling devices such as Esaki diode and resonant tunneling diode (RTD) have been extensively explored to construct the MVL circuits. These tunneling devices present a negative differential resistance (NDR) phenomenon in which a current decreases as a voltage increases in a specific applied voltage region. Due to this non-monotonic current behavior, the tunneling devices have more than two threshold voltages, consequently enabling construction of MVL circuits. Recently, the emergence of two dimensional (2D) van der Waals (vdW) crystals has opened up the possibility to fabricate such tunneling devices easily. Owing to the defect-free surface of the 2D crystals, a very abrupt junction interface could be formed through a simple stacking process, which subsequently allowed the implementation of a high-performance tunneling device. Here, we report a vdW heterostructure based tunneling device with multiple threshold voltages, which was fabricated with black phosphorus (BP) and hafnium diselenide (HfSe₂). First, we exfoliated BP on the SiO₂ substrate and then transferred HfSe₂ on BP using dry transfer method. The BP and HfSe₂ form type-Ⅲ heterojunction so that the highly doped n+/p+ interface can be easily implemented without additional electrical or chemical doping process. Owing to high natural doping at the junction, record high peak to valley ratio (PVCR) of 16 was observed to the best our knowledge in 2D materials based NDR device. Furthermore, based on this, we first demonstrate the feasibility of the ternary latch by connecting two multi-threshold voltage devices in series.

Keywords: two dimensional van der Waals crystal, multi-valued logic, negative differential resistnace, tunneling device

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Authors: Karandeep Kaur

Abstract:

This paper presents the design of power amplifier (PA) for mmWave communication systems. The designed amplifier uses GlobalFoundries 22 FDX technology and works at an operational frequency of 140 GHz in the D-Band. With a supply voltage of 0.8V for the super low threshold voltage transistors, the amplifier is biased in class AB and has a total current consumption of 50 mA. The measured saturated output power from the power amplifier is 5.6 dBm with an output-referred 1dB-compression point of 1.6dBm. The measured gain of PA is 19 dB with 3 dB-bandwidth ranging from 120 GHz to 140 GHz. The chip occupies an area of 795µm × 410µm.

Keywords: mmWave communication system, power amplifiers, 22FDX, D-Band, cross-coupled capacitive neutralization

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Authors: Jing Nan

Abstract:

The air breakdown voltage in compact circuit breakers is a critical factor in the design and reliability of electrical distribution systems. This voltage determines the threshold at which the air insulation between conductors will fail or 'break down,' leading to an arc. This phenomenon is highly sensitive to the conditions within the breaker, such as the temperature and the distance between electrodes. Typically, air breakdown voltage models have been reliable for predicting failure under standard operational temperatures. However, in conditions post-arcing, where temperatures can soar above 2000K, these models face challenges due to the complex physics of ionization and electron behaviour at such high-energy states. Building upon the foundational understanding that the breakdown mechanism is initiated by free electrons and propelled by electric fields, which lead to ionization and, potentially, to avalanche or streamer formation, we acknowledge the complexity introduced by high-temperature environments. Recognizing the limitations of existing experimental data, a notable research gap exists in the accurate prediction of breakdown voltage at elevated temperatures, typically observed post-arcing, where temperatures exceed 2000K.To bridge this knowledge gap, we present a method that integrates gap distance and high-temperature effects into air breakdown voltage assessment. The proposed model is grounded in the physics of ionization, accounting for the dynamic behaviour of free electrons which, under intense electric fields at elevated temperatures, lead to thermal ionization and potentially reach the threshold for streamer formation as Meek's criterion. Employing the Saha equation, our model calculates equilibrium electron densities, adapting to the atmospheric pressure and the hot temperature regions indicative of post-arc temperature conditions. Our model is rigorously validated against established experimental data, demonstrating substantial improvements in predicting air breakdown voltage in the high-temperature regime. This work significantly improves the predictive power for air breakdown voltage under conditions that closely mimic operational stressors in compact circuit breakers. Looking ahead, the proposed methods are poised for further exploration in alternative insulating media, like SF6, enhancing the model's utility for a broader range of insulation technologies and contributing to the future of high-temperature electrical insulation research.

Keywords: air breakdown voltage, high-temperature insulation, compact circuit breakers, electrical discharge, saha equation

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Authors: Yong Seo Koo, Jong Ho Nam, Yong Nam Choi, Dae Yeol Yoo, Jung Woo Han

Abstract:

This paper presents a silicon controller rectifier (SCR) based ESD protection circuit for IC. The proposed ESD protection circuit has low trigger voltage and high holding voltage compared with conventional SCR ESD protection circuit. Electrical characteristics of the proposed ESD protection circuit are simulated and analyzed using TCAD simulator. The proposed ESD protection circuit verified effective low voltage ESD characteristics with low trigger voltage and high holding voltage.

Keywords: electro-static discharge (ESD), silicon controlled rectifier (SCR), holding voltage, protection circuit

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Authors: Kyoung-il Do, Byung-seok Lee, Hee-guk Chae, Jeong-yun Seo Yong-seo Koo

Abstract:

In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.

Keywords: ESD, SCR, latch-up, power clamp, holding voltage

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Authors: Sun-Ki Hong, Yong-Ho Cho, Ki-Seok Kim, Tae-Sam Kang

Abstract:

Piezoelectric actuator is treated as RC load when it is modeled electrically. For some piezoelectric actuator applications, arbitrary voltage is required to actuate. Especially for unidirectional arbitrary voltage driving like as sine wave, some special inverter with circuit that can charge and discharge the capacitive energy can be used. In this case, the difference between power supply level and the object voltage level for RC load is varied. Because the control gain is constant, the controlled output is not uniform according to the voltage difference. In this paper, for charge and discharge circuit for unidirectional arbitrary voltage driving for piezoelectric actuator, the controller gain is controlled according to the voltage difference. With the proposed simple idea, the load voltage can have controlled smoothly although the voltage difference is varied. The appropriateness is proved from the simulation of the proposed circuit.

Keywords: analog voltage inverter, capacitive load, gain control, dc-dc converter, piezoelectric, voltage waveform

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Authors: H. H. Goh, Q. S. Chua, S. W. Lee, B. C. Kok, K. C. Goh, K. T. K. Teo

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At present, the evaluation of voltage stability assessment experiences sizeable anxiety in the safe operation of power systems. This is due to the complications of a strain power system. With the snowballing of power demand by the consumers and also the restricted amount of power sources, therefore, the system has to perform at its maximum proficiency. Consequently, the noteworthy to discover the maximum ability boundary prior to voltage collapse should be undertaken. A preliminary warning can be perceived to evade the interruption of power system’s capacity. The effectiveness of line voltage stability indices (LVSI) is differentiated in this paper. The main purpose of the indices is used to predict the proximity of voltage instability of the electric power system. On the other hand, the indices are also able to decide the weakest load buses which are close to voltage collapse in the power system. The line stability indices are assessed using the IEEE 14 bus test system to validate its practicability. Results demonstrated that the implemented indices are practically relevant in predicting the manifestation of voltage collapse in the system. Therefore, essential actions can be taken to dodge the incident from arising.

Keywords: critical line, line outage, line voltage stability indices (LVSI), maximum loadability, voltage collapse, voltage instability, voltage stability analysis

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