Search results for: field effect transistors

Authors: Mehdi Saeidmanesh, Razali Ismail

Abstract:

Recently, Graphene Nanoribbon Field Effect Transistors (GNR FETs) attract a great deal of attention due to their better performance in comparison with conventional devices. In this paper, channel length Modulation (CLM) effect on the electrical characteristics of GNR FETs is analytically studied and modeled. To this end, the special distribution of the electric potential along the channel and current-voltage characteristic of the device is modeled. The obtained results of analytical model are compared to the experimental data of published works. As a result, it is observable that considering the effect of CLM, the current-voltage response of GNR FET is more realistic.

Keywords: graphene nanoribbon, field effect transistors, short channel effects, channel length modulation

Procedia PDF Downloads 372

Authors: Pejman Hosseinioun, Ali Safari, Hamed Sarbazi

Abstract:

Graphene is a one-atom-thick sheet of carbon with numerous impressive properties. It is a promising material for future high-speed nanoelectronics due to its intrinsic superior carrier mobility and very high saturation velocity. These exceptional carrier transport properties suggest that graphene field effect transistors (G-FETs) can potentially outperform other FET technologies. In this paper, detailed discussions are introduced for Graphene Transistors Based Microwave Amplifiers.

Keywords: graphene, microwave FETs, microwave amplifiers, transistors

Procedia PDF Downloads 456

Authors: Jingqi Li

Abstract:

A new vertical carbon nanotube field effect transistor (CNTFET) has been developed. The source, drain and gate are vertically stacked in this structure. The carbon nanotubes are put on the side wall of the vertical stack. Unique transfer characteristics which depend on both silicon type and the sign of drain voltage have been observed in silicon integrated CNTFETs. The significant advantage of this CNTFET is that the short channel of the transistor can be fabricated without using complicate lithography technique.

Keywords: carbon nanotubes, field-effect transistors, electrical property, short channel fabrication

Procedia PDF Downloads 318

Authors: Lin Gong, Holger Göbel

Abstract:

In the present study, we have investigated the influence of UV/ozone treatment on pentacene-based organic field effect transistors (OFETs) with a bilayer gate dielectric. The OFETs for this study were fabricated on heavily n-doped Si substrates with a thermally deposited SiO2 dielectric layer (300nm). On the SiO2 dielectric a very thin (≈ 15nm) buffer layer of polystyrene (PS) was first spin-coated and then treated by UV/ozone to modify the surface prior to the deposition of pentacene. We found out that by extending the UV/ozone treatment time the threshold voltage of the OFETs was monotonically shifted towards positive values, whereas the field effect mobility first decreased but eventually reached a stable value after a treatment time of approximately thirty seconds. Since the field effect mobility of the UV/ozone treated bilayer OFETs was found to be higher than the value of a comparable transistor with a single layer dielectric, we propose that the bilayer (SiO2/PS) structure can be used to shift the threshold voltage to a desired value without sacrificing field effect mobility.

Keywords: buffer layer, organic field effect transistors, threshold voltage, UV/ozone treatment

Procedia PDF Downloads 297

Authors: Robert Setekera, Ramses van der Toorn

Abstract:

We present an extensive analysis of the temperature dependence of the local avalanche model used in most of the modern compact models for bipolar transistors. This local avalanche model uses the Chynoweth's empirical law for ionization coefficient to define the generation of the avalanche current in terms of the local electric field. We carry out the model analysis using DC-measurements taken on both Si and advanced SiGe bipolar transistors. For the advanced industrial SiGe-HBTs, we consider both high-speed and high-power devices (both NPN and PNP transistors). The limitations of the local avalanche model in modeling the temperature dependence of the avalanche current mostly in the weak avalanche region are demonstrated. In addition, the model avalanche parameters are analyzed to see if they are in agreement with semiconductor device physics.

Keywords: avalanche multiplication, avalanche current, bipolar transistors, compact modeling, electric field, impact ionization, local avalanche

Procedia PDF Downloads 590

Authors: Yanan Zhu

Abstract:

Based on the previous work about the influence mechanism of the mobility difference of phenyl and thienyl substituent semiconductors, we have made further exploration towards to design high-performance organic thin-film transistors. The substituent groups effect plays a significant role in materials properties and device performance as well. For the theoretical study, simulation of materials property and crystal packing can supply scientific guidance for materials synthesis in experiments. This time, we have taken the computational methods to design a new material substituent with furan groups, which are the potential to be used in organic thin-film transistors and organic single-crystal transistors. The reorganization energy has been calculated and much lower than 2,6-diphenyl anthracene (DPAnt), which performs large mobility as more than 30 cm²V⁻¹s⁻¹. Moreover, the other important parameter, charge transfer integral is larger than DPAnt, which suggested the furan substituent material may get a much better charge transport data. On the whole, the mechanism investigation based on phenyl and thienyl assisted in designing novel materials with furan substituent, which is predicted to be an outperformed organic field-effect transistors.

Keywords: theoretical calculation, mechanism, mobility, organic transistors

Procedia PDF Downloads 105

Authors: Fatima Zohra Rahou, A. Guen Bouazza, B. Bouazza

Abstract:

Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect.

Keywords: SOI technology, PDSOI MOSFET, FDSOI MOSFET, kink effect

Procedia PDF Downloads 219

Authors: Tomas Vincze, Michal Micjan, Milan Pavuk, Martin Weis

Abstract:

In recent years, alternative materials are gaining attention to replace polycrystalline and amorphous silicon, which are a standard for low requirement devices, where silicon is unnecessarily and high cost. For that reason, metal oxides are envisioned as the new materials for these low-requirement applications such as sensors, solar cells, energy storage devices, or field-effect transistors. Their most common way of layer growth is sputtering; however, this is a high-cost fabrication method, and a more industry-suitable alternative is the sol-gel method. In this group of materials, many oxides exhibit a semiconductor-like behavior with sufficiently high mobility to be applied as transistors. The sol-gel method is a cost-effective deposition technique for semiconductor-based devices. Copper oxides, as p-type semiconductors with free charge mobility up to 1 cm2/Vs., are suitable replacements for poly-Si or a-Si:H devices. However, to reach the potential of silicon devices, a fine-tuning of material properties is needed. Here we focus on the optimization of the electrical parameters of copper oxide-based field-effect transistors by modification of precursor solvent (usually 2-methoxy ethanol). However, to achieve solubility and high-quality films, a better solvent is required. Since almost no solvents have both high dielectric constant and high boiling point, an alternative approach was proposed with blend solvents. By mixing isopropyl alcohol (IPA) and 2-methoxy ethanol (2ME) the precursor reached better solubility. The quality of the layers fabricated using mixed solutions was evaluated in accordance with the surface morphology and electrical properties. The IPA:2ME solution mixture reached optimum results for the weight ratio of 1:3. The cupric oxide layers for optimal mixture had the highest crystallinity and highest effective charge mobility.

Keywords: copper oxide, field-effect transistor, semiconductor, sol-gel method

Procedia PDF Downloads 98

Authors: Debabrata Bhadra, B. K. Chaudhuri

Abstract:

The operation of organic thin film transistors (OFETs) with low voltage is currently a prevailing issue. We have fabricated anthracene thin-film transistor (TFT) with an ultrathin layer (~450nm) of Poly-vinylidene fluoride (PVDF)/CuO nanocomposites as a gate insulator. We obtained a device with excellent electrical characteristics at low operating voltages (<1V). Different layers of the film were also prepared to achieve the best optimization of ideal gate insulator with various static dielectric constant (εr ). Capacitance density, leakage current at 1V gate voltage and electrical characteristics of OFETs with a single and multi layer films were investigated. This device was found to have highest field effect mobility of 2.27 cm2/Vs, a threshold voltage of 0.34V, an exceptionally low sub threshold slope of 380 mV/decade and an on/off ratio of 106. Such favorable combination of properties means that these OFETs can be utilized successfully as voltages below 1V. A very simple fabrication process has been used along with step wise poling process for enhancing the pyroelectric effects on the device performance. The output characteristic of OFET after poling were changed and exhibited linear current-voltage relationship showing the evidence of large polarization. The temperature dependent response of the device was also investigated. The stable performance of the OFET after poling operation makes it reliable in temperature sensor applications. Such High-ε CuO/PVDF gate dielectric appears to be highly promising candidates for organic non-volatile memory and sensor field-effect transistors (FETs).

Keywords: organic field effect transistors, thin film transistor, gate dielectric, organic semiconductor

Procedia PDF Downloads 212

Authors: Peihao Huang, Chun Zhao

Abstract:

Thin-film transistors(TFTs) have the advantages of low power consumption, short reaction time, and have high research value in the field of semiconductors, based on this reason, people have focused on gallium oxide-indium oxide thin-film transistors, a relatively common thin-film transistor, elaborated and analyzed his production process, "aqueous solution method", explained the purpose of each step of operation, and finally explored the influence of potassium ions doped in the channel layer on the electrical properties of the device, as well as the effect of oxygen vacancies on its switching ratio and memory, and summarized the conclusions.

Keywords: aqueous solution, oxygen vacancies, switch ratio, thin-film transistor(TFT)

Procedia PDF Downloads 57

Authors: Nikhil Jain, Bin Yu

Abstract:

We explore the potential of using ultra-thin hexagonal boron nitride (h-BN) as both supporting substrate and gate dielectric for graphene-channel field effect transistors (GFETs). Different from commonly used oxide-based dielectric materials which are typically amorphous, very rough in surface, and rich with surface traps, h-BN is layered insulator free of dangling bonds and surface states, featuring atomically smooth surface. In a graphene-channel-last device structure with local buried metal gate electrode (TiN), thin h-BN multilayer is employed as both supporting “substrate” and gate dielectric for graphene active channel. We observed superior carrier mobility and electrical conduction, significantly improved from that in GFETs with SiO2 as substrate/gate insulator. In addition, we report excellent dielectric behavior of layered h-BN, including ultra-low leakage current and high critical electric field for breakdown.

Keywords: graphene, field-effect transistors, hexagonal boron nitride, dielectric strength, tunneling

Procedia PDF Downloads 396

Authors: Daniel Bülz, Franziska Lüttich, Sreetama Banerjee, Georgeta Salvan, Dietrich R. T. Zahn

Abstract:

For the development of electronics, organic semiconductors are of great interest due to their adjustable optical and electrical properties. Especially for spintronic applications they are interesting because of their weak spin scattering, which leads to longer spin life times compared to inorganic semiconductors. It was shown that some organic materials change their resistance if an external magnetic field is applied. Pentacene is one of the materials which exhibit the so called photoinduced magnetoresistance which results in a modulation of photocurrent when varying the external magnetic field. Also the soluble derivate of pentacene, the 6,13-bis (triisopropylsilylethynyl)-pentacene (TIPS-pentacene) exhibits the same negative magnetoresistance. Aiming for simpler fabrication processes, in this work, we compare TIPS-pentacene organic field effect transistors (OFETs) made from solution with those fabricated by thermal evaporation. Because of the different processing, the TIPS-pentacene thin films exhibit different morphologies in terms of crystal size and homogeneity of the substrate coverage. On the other hand, the interface treatment is known to have a high influence on the threshold voltage, eliminating trap states of silicon oxide at the gate electrode and thereby changing the electrical switching response of the transistors. Therefore, we investigate the influence of interface treatment using octadecyltrichlorosilane (OTS) or using a simple cleaning procedure with acetone, ethanol, and deionized water. The transistors consist of a prestructured OFET substrates including gate, source, and drain electrodes, on top of which TIPS-pentacene dissolved in a mixture of tetralin and toluene is deposited by drop-, spray-, and spin-coating. Thereafter we keep the sample for one hour at a temperature of 60 °C. For the transistor fabrication by thermal evaporation the prestructured OFET substrates are also kept at a temperature of 60 °C during deposition with a rate of 0.3 nm/min and at a pressure below 10-6 mbar. The OFETs are characterized by means of optical microscopy in order to determine the overall quality of the sample, i.e. crystal size and coverage of the channel region. The output and transfer characteristics are measured in the dark and under illumination provided by a white light LED in the spectral range from 450 nm to 650 nm with a power density of (8±2) mW/cm2.

Keywords: organic field effect transistors, solution processed, surface treatment, TIPS-pentacene

Procedia PDF Downloads 413

Authors: Y. Lu, L. Liu, J. Guo

Abstract:

Monolayer graphene and dichaclogenide semiconductor materials attract extensive research interest for potential nanoelectronics applications. The ultimate scaling limit of double gate MoS2 Field-Effect-Transistors (FETs) with a monolayer thin body is examined and compared with ultra-thin-body Si FETs by using self-consistent quantum transport simulation in the presence of phonon scattering. Modelling of phonon scattering, quantum mechanical effects, and self-consistent electrostatics allows us to accurately assess the performance potential of monolayer MoS2 FETs. The results revealed that monolayer MoS2 FETs show 52% smaller Drain Induced Barrier Lowering (DIBL) and 13% Smaller Sub-Threshold Swing (SS) than 3 nm-thick-body Si FETs at a channel length of 10 nm with the same gating. With a requirement of SS<100mV/dec, the scaling limit of monolayer MoS2 FETs is assessed to be 5 nm, comparing with 8nm of the ultra-thin-body Si counterparts due to the monolayer thin body and higher effective mass which reduces direct source-to-drain tunnelling. By comparing with the ITRS target for high performance logic devices of 2023; double gate monolayer MoS2 FETs can fulfil the ITRS requirements.

Keywords: nanotransistors, monolayer 2D materials, quantum transport, scaling limit

Procedia PDF Downloads 203

Authors: Tae Kyu An

Abstract:

We demonstrate repurposing linear micropatterns on the CD as a master mold to fabricate TIPS-PEN microwires. From the micropatterns on CDs, we replicated polyurethane acrylate (PUA) templates which are robust and flexible until submicrometer scale patterns. Subsequently, 1.5 μm TIPS-PEN microwires separated by 1.5 μm were grown. Using crystal analysis tools with polarized optical microscopy and X-ray diffraction measurement, it was revealed that each TIPS-PEN microwires are highly crystalline and uniform compared to spin-coated films. It is attributed to the template-guided growth of TIPS-PEN crystals along the linear template, thus the OFETs comprised of TIPS-PEN microwires displayed the high field-effect mobility.

Keywords: compact disk, macro patterning, OFET, soft lithography

Procedia PDF Downloads 201

Authors: C. S Lee, W. C. Hsu, H. Y. Liu, C. J. Lin, S. C. Yao, Y. T. Shen, Y. C. Lin

Abstract:

In₀.₁₈Al₀.₈₂N/AlN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) having Al₂O₃ gate-dielectric and backside metal-trench structure are investigated. The Al₂O₃ gate oxide was formed by using a cost-effective non-vacuum ultrasonic spray pyrolysis deposition (USPD) method. In order to enhance the heat dissipation efficiency, metal trenches were etched 3-µm deep and evaporated with a 150-nm thick Ni film on the backside of the Si substrate. The present In₀.₁₈Al₀.₈₂N/AlN/GaN MOS-HFET (Schottky-gate HFET) has demonstrated improved maximum drain-source current density (IDS, max) of 1.08 (0.86) A/mm at VDS = 8 V, gate-voltage swing (GVS) of 4 (2) V, on/off-current ratio (Ion/Ioff) of 8.9 × 10⁸ (7.4 × 10⁴), subthreshold swing (SS) of 140 (244) mV/dec, two-terminal off-state gate-drain breakdown voltage (BVGD) of -191.1 (-173.8) V, turn-on voltage (Von) of 4.2 (1.2) V, and three-terminal on-state drain-source breakdown voltage (BVDS) of 155.9 (98.5) V. Enhanced power performances, including saturated output power (Pout) of 27.9 (21.5) dBm, power gain (Gₐ) of 20.3 (15.5) dB, and power-added efficiency (PAE) of 44.3% (34.8%), are obtained. Superior breakdown and RF power performances are achieved. The present In₀.₁₈Al₀.₈₂N/AlN/GaN MOS-HFET design with backside metal-trench is advantageous for high-power circuit applications.

Keywords: backside metal-trench, InAlN/AlN/GaN, MOS-HFET, non-vacuum ultrasonic spray pyrolysis deposition

Procedia PDF Downloads 226

Authors: Wei-Chou Hsu, Ching-Sung Lee, Han-Yin Liu

Abstract:

This work uses H2O2 oxidation technique to improve the pH sensitivity of the AlGaN/GaN-based ion-sensitive field-effect transistors (ISFETs). 10-nm-thick Al2O3 was grown on the surface of the AlGaN. It was found that the pH sensitivity was improved from 41.6 mV/pH to 55.2 mV/pH. Since the H2O2-grown Al2O3 was served as a passivation layer and the problem of Fermi-level pinning was suppressed for the ISFET with the H2O2 oxidation process. Hysteresis effect in the ISFET with the H2O2 treatment also became insignificant. The hysteresis effect was observed by dipping the ISFETs into different pH value solutions and comparing the voltage difference between the initial and final conditions. The hysteresis voltage (Vhys) of the ISFET with the H2O2 oxidation process was improved from 8.7 mV to 4.8 mV. The hysteresis effect is related to the buried binding sites which are related to the material defects like threading dislocations in the AlGaN/GaN heterostructure which was grown by the hetero-epitaxy technique. The H2O2-grown Al2O3 passivate these material defects and the Al2O3 has less material defects. The long-term stability of the ISFET is estimated by the drift effect measurement. The drift measurement was conducted by dipping the ISFETs into a specific pH value solution for 12 hours and the ISFETs were operating at a specific quiescent point. The drift rate is estimated by the drift voltage divided by the total measuring time. It was found that the drift rate of the ISFET was improved from 10.1 mV/hour to 1.91 mV/hour in the pH 7 solution, from 14.06 mV/hour to 6.38 mV/pH in the pH 2 solution, and from 12.8 mV/hour to 5.48 mV/hour in the pH 12 solution. The drift effect results from the capacitance variation in the electric double layer. The H2O2-grown Al2O3 provides an additional capacitance connection in series with the electric double layer. Therefore, the capacitance variation of the electric double layer became insignificant. Generally, the H2O2 oxidation process is a simple, fast, and cost-effective method for the AlGaN/GaN-based ISFET. Furthermore, the performance of the AlGaN/GaN ISFET was improved effectively and the non-ideal effects were suppressed.

Keywords: AlGaN/GaN, Al2O3, hysteresis effect, drift effect, reliability, passivation, pH sensors

Procedia PDF Downloads 290

Authors: Nikhil Jain, Yang Xu, Bin Yu

Abstract:

Hexagonal boron nitride (h-BN) has been used as a substrate and gate dielectric for graphene field effect transistors (GFETs). Using a graphene/h-BN/TiN (channel/dielectric/gate) stack, key material properties of h-BN were investigated i.e. dielectric strength and tunneling behavior. Work function difference between graphene and TiN results in spontaneous p-doping of graphene through a multi-layer h-BN flake. However, at high levels of current stress, n-doping of graphene is observed, possibly due to the charge transfer across the thin h-BN multi layer. Neither Direct Tunneling (DT) nor Fowler-Nordheim Tunneling (FNT) was observed in TiN/h-BN/Au hetero structures with h-BN showing two distinct volatile conduction states before breakdown. Hexagonal boron nitride emerges as a material of choice for gate dielectrics in GFETs because of robust dielectric properties and high tunneling barrier.

Keywords: graphene, transistors, conduction, hexagonal boron nitride, dielectric strength, tunneling

Procedia PDF Downloads 325

Authors: MeiBo, ZhaoXing, LuoLei, YuQingkui, TangMin, HanZhengsheng

Abstract:

The Single Event Transients (SETs) were investigated on 0.18μm PDSOI transistors and 100 series CMOS inverter chain using pulse laser. The effect of different laser energy and device bias for waveform on SET was characterized experimentally, as well as the generation and propagation of SET in inverter chain. In this paper, the effects of struck transistors type and struck locations on SETs were investigated. The results showed that when irradiate NMOSFETs from 100th to 2nd stages, the SET pulse width measured at the output terminal increased from 287.4 ps to 472.9 ps; and when irradiate PMOSFETs from 99th to 1st stages, the SET pulse width increased from 287.4 ps to 472.9 ps. When struck locations were close to the output of the chain, the SET pulse was narrow; however, when struck nodes were close to the input, the SET pulse was broadening. SET pulses were progressively broadened up when propagating along inverter chains. The SET pulse broadening is independent of the type of struck transistors. Through analysis, history effect induced threshold voltage hysteresis in PDSOI is the reason of pulse broadening. The positive pulse observed by oscilloscope, contrary to the expected results, is because of charging and discharging of capacitor.

Keywords: single event transients, pulse laser, partially-depleted silicon-on-insulator, propagation-induced pulse broadening effect

Procedia PDF Downloads 379

Authors: T. Bielewicz, S. Dogan, C. Klinke

Abstract:

Two-dimensional, solution-processable semiconductor materials are interesting for low-cost electronic applications [1]. We demonstrate the synthesis of lead sulfide nanosheets and how their size, shape and height can be tuned by varying concentrations of pre-cursors, ligands and by varying the reaction temperature. Especially, the charge carrier confinement in the nanosheets’ height adjustable from 2 to 20 nm has a decisive impact on their electronic properties. This is demonstrated by their use as conduction channel in a field effect transistor [2]. Recently we also showed that especially thin nanosheets show a high carrier multiplication (CM) efficiency [3] which could make them, through the confinement induced band gap and high photoconductivity, very attractive for application in photovoltaic devices. We are already able to manufacture photovoltaic devices out of single nanosheets which show promising results.

Keywords: physical sciences, chemistry, materials, chemistry, colloids, physics, condensed-matter physics, semiconductors, two-dimensional materials

Procedia PDF Downloads 270

Authors: Suruchi Saini, Hitender Kumar Tyagi

Abstract:

With the rapid progress of the nanotechnology industry, it is becoming increasingly important to have compact semiconductor devices to function and offer the best results at various technology nodes. While performing the scaling of the device, several short-channel effects occur. To minimize these scaling limitations, some device architectures have been developed in the semiconductor industry. FinFET is one of the most promising structures. Also, the double-gate 2D Fin field effect transistor has the benefit of suppressing short channel effects (SCE) and functioning well for less than 14 nm technology nodes. In the present research, the MuGFET simulation tool is used to analyze and explain the electrical behaviour of a double-gate 2D Fin field effect transistor. The drift-diffusion and Poisson equations are solved self-consistently. Various models, such as Fermi-Dirac distribution, bandgap narrowing, carrier scattering, and concentration-dependent mobility models, are used for device simulation. The transfer and output characteristics of the double-gate 2D Fin field effect transistor are determined at 10 nm technology node. The performance parameters are extracted in terms of threshold voltage, trans-conductance, leakage current and current on-off ratio. In this paper, the device performance is analyzed at different structure parameters. The utilization of the Id-Vg curve is a robust technique that holds significant importance in the modeling of transistors, circuit design, optimization of performance, and quality control in electronic devices and integrated circuits for comprehending field-effect transistors. The FinFET structure is optimized to increase the current on-off ratio and transconductance. Through this analysis, the impact of different channel widths, source and drain lengths on the Id-Vg and transconductance is examined. Device performance was affected by the difficulty of maintaining effective gate control over the channel at decreasing feature sizes. For every set of simulations, the device's features are simulated at two different drain voltages, 50 mV and 0.7 V. In low-power and precision applications, the off-state current is a significant factor to consider. Therefore, it is crucial to minimize the off-state current to maximize circuit performance and efficiency. The findings demonstrate that the performance of the current on-off ratio is maximum with the channel width of 3 nm for a gate length of 10 nm, but there is no significant effect of source and drain length on the current on-off ratio. The transconductance value plays a pivotal role in various electronic applications and should be considered carefully. In this research, it is also concluded that the transconductance value of 340 S/m is achieved with the fin width of 3 nm at a gate length of 10 nm and 2380 S/m for the source and drain extension length of 5 nm, respectively.

Keywords: current on-off ratio, FinFET, short-channel effects, transconductance

Procedia PDF Downloads 34

Authors: Chhavi Saxena

Abstract:

FinFETs can be a replacement for bulk-CMOS transistors in many different designs. Its low leakage/standby power property makes FinFETs a desirable option for memory sub-systems. Memory modules are widely used in most digital and computer systems. Leakage power is very important in memory cells since most memory applications access only one or very few memory rows at a given time. As technology scales down, the importance of leakage current and power analysis for memory design is increasing. In this paper, we discover an option for low power interconnect synthesis at the 32nm node and beyond, using Fin-type Field-Effect Transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a mechanism for improving FinFETs efficiency, called variable supply voltage schemes. In this paper, we’ve illustrated the design and implementation of FinFET based 4x4 SRAM cell array by means of one bit 7T SRAM. FinFET based 7T SRAM has been designed and analysis have been carried out for leakage current, dynamic power and delay. For the validation of our design approach, the output of FinFET SRAM array have been compared with standard CMOS SRAM and significant improvements are obtained in proposed model.

Keywords: FinFET, 7T SRAM cell, leakage current, delay

Procedia PDF Downloads 421

Authors: L. Giraudet, O. Simonetti, G. de Tournadre, N. Dumelié, B. Clarenc, F. Reisdorffer

Abstract:

In this paper we intend to give a comprehensive view of the saturation misbehavior of thin film transistors (TFTs) based on disordered semiconductors, such as most organic TFTs, and its link to the field activation of the mobility. Experimental evidence of the field activation of the mobility is given for disordered semiconductor based TFTs, when reducing the gate length. Saturation misbehavior is observed simultaneously. Advanced transport models have been implemented in a quasi-2D numerical TFT simulation software. From the numerical simulations it is clearly established that field activation of the mobility alone cannot explain the saturation misbehavior. Evidence is given that high longitudinal field gradient at the drain end of the channel is responsible for an excess charge accumulation, preventing saturation. The two combined effects allow reproducing the experimental output characteristics of short channel TFTs, with S-shaped characteristics and saturation failure.

Keywords: mobility field activation, numerical simulation, OTFT, saturation failure

Procedia PDF Downloads 484

Authors: S. Boorboor, S. A. H. Feghhi, H. Jafari

Abstract:

The ionizing radiations cause different kinds of damages in electronic components. MOSFETs, most common transistors in today’s digital and analog circuits, are severely sensitive to TID damage. In this work, the threshold voltage shift of CD4007 device, which is an integrated circuit including P-channel and N-channel MOS transistors, was investigated for low dose gamma irradiation under different gate bias voltages. We used linear extrapolation method to extract threshold voltage from I_D-V_G characteristic curve. The results showed that the threshold voltage shift was approximately 27.5 mV/Gy for N-channel and 3.5 mV/Gy for P-channel transistors at the gate bias of |9 V| after irradiation by Co-60 gamma ray source. Although the sensitivity of the devices under test were strongly dependent to biasing condition and transistor type, the threshold voltage shifted linearly versus accumulated dose in all cases. The overall results show that the application of CD4007 as an electronic buffer in a radiation therapy system is limited by TID damage. However, this integrated circuit can be used as a cheap and sensitive radiation dosimeter for accumulated dose measurement in radiation therapy systems.

Keywords: threshold voltage shift, MOS transistor, linear extrapolation, gamma irradiation

Procedia PDF Downloads 244

Authors: Yu-Hsien Lin, Yu-Ru Lin, Yung-Chun Wu

Abstract:

This work demonstrates the ultra-thin poly-Si (polycrystalline Silicon) nanowire junctionless thin film transistors (NWs JL-TFT) with nickel silicide contact. For nickel silicide film, this work designs to use two-step annealing to form ultra-thin, uniform and low sheet resistance (Rs) Ni silicide film. The NWs JL-TFT with nickel silicide contact exhibits the good electrical properties, including high driving current (>10⁷ Å), subthreshold slope (186 mV/dec.), and low parasitic resistance. In addition, this work also compares the electrical characteristics of NWs JL-TFT with nickel silicide and non-silicide contact. Nickel silicide techniques are widely used for high-performance devices as the device scaling due to the source/drain sheet resistance issue. Therefore, the self-aligned silicide (salicide) technique is presented to reduce the series resistance of the device. Nickel silicide has several advantages including low-temperature process, low silicon consumption, no bridging failure property, smaller mechanical stress, and smaller contact resistance. The junctionless thin-film transistor (JL-TFT) is fabricated simply by heavily doping the channel and source/drain (S/D) regions simultaneously. Owing to the special doping profile, JL-TFT has some advantages such as lower thermal the budget which can integrate with high-k/metal-gate easier than conventional MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), longer effective channel length than conventional MOSFETs, and avoidance of complicated source/drain engineering. To solve JL-TFT has turn-off problem, JL-TFT needs ultra-thin body (UTB) structure to reach fully depleted channel region in off-state. On the other hand, the drive current (Iᴅ) is declined as transistor features are scaled. Therefore, this work demonstrates ultra thin poly-Si nanowire junctionless thin film transistors with nickel silicide contact. This work investigates the low-temperature formation of nickel silicide layer by physical-chemical deposition (PVD) of a 15nm Ni layer on the poly-Si substrate. Notably, this work designs to use two-step annealing to form ultrathin, uniform and low sheet resistance (Rs) Ni silicide film. The first step was promoted Ni diffusion through a thin interfacial amorphous layer. Then, the unreacted metal was lifted off after the first step. The second step was annealing for lower sheet resistance and firmly merged the phase.The ultra-thin poly-Si nanowire junctionless thin film transistors NWs JL-TFT with nickel silicide contact is demonstrated, which reveals high driving current (>10⁷ Å), subthreshold slope (186 mV/dec.), and low parasitic resistance. In silicide film analysis, the second step of annealing was applied to form lower sheet resistance and firmly merge the phase silicide film. In short, the NWs JL-TFT with nickel silicide contact has exhibited a competitive short-channel behavior and improved drive current.

Keywords: poly-Si, nanowire, junctionless, thin-film transistors, nickel silicide

Procedia PDF Downloads 209

Authors: Rajesh Kumar Ulaganathan, Yi-Ying Lu, Chia-Jung Kuo, Srinivasa Reddy Tamalampudi, Raman Sankar, Fang Cheng Chou, Yit-Tsong Chen

Abstract:

In this paper, we report the optoelectronic properties of multi-layered GeS nanosheets (~28 nm thick)-based field-effect transistors (called GeS-FETs). The multi-layered GeS-FETs exhibit remarkably high photoresponsivity of Rλ ~ 206 AW-1 under illumination of 1.5 µW/cm2 at  = 633 nm, Vg = 0 V, and Vds = 10 V. The obtained Rλ ~ 206 AW-1 is excellent as compared with a GeS nanoribbon-based and the other family members of group IV-VI-based photodetectors in the two-dimensional (2D) realm, such as GeSe and SnS2. The gate-dependent photoresponsivity of GeS-FETs was further measured to be able to reach Rλ ~ 655 AW-1 operated at Vg = -80 V. Moreover, the multi-layered GeS photodetector holds high external quantum efficiency (EQE ~ 4.0 × 104 %) and specific detectivity (D* ~ 2.35 × 1013 Jones). The measured D* is comparable to those of the advanced commercial Si- and InGaAs-based photodiodes. The GeS photodetector also shows an excellent long-term photoswitching stability with a response time of ~7 ms over a long period of operation (>1 h). These extraordinary properties of high photocurrent generation, broad spectral range, fast response, and long-term stability make the GeS-FET photodetector a highly qualified candidate for future optoelectronic applications.

Keywords: germanium sulfide, photodetector, photoresponsivity, external quantum efficiency, specific detectivity

Procedia PDF Downloads 502

Authors: Olfat A. Fadali, Mohamed S. Mahmoud, Omnia H. Abdelraheem, Shimaa G. Mohammed

Abstract:

The effect of electromagnetic field (EMF) on the removal of edible oil from oil-in-water emulsion by means of electrocoagulation was investigated in rectangular batch electrochemical cell with DC current. Iron (Fe) plate anodes and stainless steel cathodes were employed as electrodes. The effect of different magnetic field intensities (1.9, 3.9 and 5.2 tesla), three different positions of EMF (below, perpendicular and parallel to the electrocoagulation cell), as well as operating time; had been investigated. The application of electromagnetic field (5.2 tesla) raises percentage of oil removal from 72.4% for traditional electrocoagulation to 90.8% after 20 min.

Keywords: electrocoagulation, electromagnetic field, Oil-water emulsion, edible oil

Procedia PDF Downloads 498

Authors: L. Boyaci

Abstract:

Two basic equipment of electrical power subsystem of space satellites are Power Conditioning Unit (PCU) and Power Distribution Unit (PDU). Today, the main switching element used in power equipment in satellites is silicon (Si) based radiation-hardened MOSFET. GaNFETs have superior performances over MOSFETs in terms of their conduction and switching characteristics. GaNFET has started to take MOSFET’s place in many applications in industry especially by virtue of its switching performances. If GaNFET can also be used in equipment for space applications, this would be great revolution for future space power subsystem designs. In this study, the effect of proton irradiation on Gallium Nitride based power transistors was investigated. Four commercial enhancement mode GaN power transistors from Efficient Power Conversion Corporation (EPC) are irradiated with 30MeV protons while devices are switching. Flux of 8.2x10⁹ protons/cm²/s is applied for 12.5 seconds to reach ultimate fluence of 10¹¹ protons/cm². Vgs-Ids characteristics are measured and recorded for each device before, during and after irradiation. It was observed that if there would be destructive events. Proton induced permanent damage on devices is not observed. All the devices remained healthy and continued to operate. For two of these devices, further irradiation is applied with same flux for 30 minutes up to a total fluence level of 1.476x10¹³ protons/cm². We observed that GaNFETs are fully functional under this high level of radiation and no destructive events and irreversible failures took place for transistors. Results reveal that irradiated GaNFET in this experiment has radiation tolerance under proton testing and very important candidate for being one of the future power switching element in space.

Keywords: enhancement mode GaN power transistors, proton irradiation effects, radiation tolerance

Procedia PDF Downloads 119

Authors: Khimmatali Nomozovich Juraev

Abstract:

Silicon carbide is one of the promising materials with potential applications in electronic devices using high power, high frequency and high electric field. Currently, silicon carbide is used to manufacture high power and frequency diodes, transistors, radiation detectors, light emitting diodes (LEDs) and other functional devices. In this work, the effects of magnetic field on p-n junctions based on 4H-SiC were experimentally studied. As a research material, monocrystalline silicon carbide wafers (Cree Research, Inc., USA) with relatively few growth defects grown by physical vapor transport (PVT) method were used: Nd dislocations 104 cm², Nm micropipes ~ 10–10² cm-², thickness ~ 300-600 μm, surface ~ 0.25 cm², resistivity ~ 3.6–20 Ωcm, the concentration of background impurities Nd − Na ~ (0.5–1.0)×1017cm-³. The initial parameters of the samples were determined on a Hall Effect Measurement System HMS-7000 (Ecopia) measuring device. Diffusing Ni nickel atoms were covered to the silicon surface of silicon carbide in a Universal Vacuum Post device at a vacuum of 10-⁵ -10-⁶ Torr by thermal sputtering and kept at a temperature of 600-650°C for 30 minutes. Then Ni atoms were diffused into the silicon carbide 4H-SiC sample at a temperature of 1150-1300°C by low temperature diffusion method in an air atmosphere, and the effects of the magnetic field on the I-V characteristics of the samples were studied. I-V characteristics of silicon carbide 4H-SiC p-n junction sample were measured in the magnetic field and in the absence of a magnetic field. The measurements were carried out under conditions where the magnitude of the magnetic field induction vector was 0.5 T. In the state, the direction of the current flowing through the diode is perpendicular to the direction of the magnetic field. From the obtained results, it can be seen that the magnetic field significantly affects the I-V characteristics of the p-n junction in the magnetic field when it is measured in the forward direction. Under the influence of the magnetic field, the change of the magnetic resistance of the sample of silicon carbide 4H-SiC p-n junction was determined. It was found that changing the magnetic field poles increases the direct forward current of the p-n junction or decreases it when the field direction changes. These unique electrical properties of the 4H-SiC p-n junction sample of silicon carbide, that is, the change of the sample's electrical properties in a magnetic field, makes it possible to fabricate magnetic field sensing devices based on silicon carbide to use at harsh environments in future. So far, the productions of silicon carbide magnetic detectors are not available in the industry.

Keywords: 4H-SiC, diffusion Ni, effects of magnetic field, I-V characteristics

Procedia PDF Downloads 58

Authors: Hani Baek, Gwang Min Sun, Chansun Shin, Sung Ho Ahn

Abstract:

Fast neutron irradiation using nuclear reactors is an effective method to improve switching loss and short circuit durability of power semiconductor (insulated gate bipolar transistors (IGBT) and insulated gate transistors (IGT), etc.). However, not only fast neutrons but also thermal neutrons, epithermal neutrons and gamma exist in the nuclear reactor. And the electrical properties of the IGBT may be deteriorated by the irradiation of gamma. Gamma irradiation damages are known to be caused by Total Ionizing Dose (TID) effect and Single Event Effect (SEE), Displacement Damage. Especially, the TID effect deteriorated the electrical properties such as leakage current and threshold voltage of a power semiconductor. This work can confirm the effect of the gamma irradiation on the electrical properties of 600 V NPT-IGBT. Irradiation of gamma forms lattice defects in the gate oxide and Si-SiO₂ interface of the IGBT. It was confirmed that this lattice defect acts on the center of the trap and affects the threshold voltage, thereby negatively shifted the threshold voltage according to TID. In addition to the change in the carrier mobility, the conductivity modulation decreases in the n-drift region, indicating a negative influence that the forward voltage drop decreases. The turn-off delay time of the device before irradiation was 212 ns. Those of 2.5, 10, 30, 70 and 100 kRad(Si) were 225, 258, 311, 328, and 350 ns, respectively. The gamma irradiation increased the turn-off delay time of the IGBT by approximately 65%, and the switching characteristics deteriorated.

Keywords: NPT-IGBT, gamma irradiation, switching, turn-off delay time, recombination, trap center

Procedia PDF Downloads 124

Authors: Sibani Bisoyi, Ute Zschieschang, Alexander Hoyer, Hagen Klauk

Abstract:

Abstract— Organic thin-film transistors (TFTs) have great potential to be used for various applications such as flexible displays or sensors. For some of these applications, the TFTs must be able to withstand temperatures in excess of 100 °C, for example to permit the integration with devices or components that require high process temperatures, or to make it possible that the devices can be subjected to the standard sterilization protocols required for biomedical applications. In this work, we have investigated how the thermal stability of low-voltage small-molecule semiconductor dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]thiophene (DNTT) TFTs is affected by the encapsulation of the TFTs and by the ambient in which the thermal stress is performed. We also studied to which extent the thermal stability of the TFTs depends on the channel length. Some of the TFTs were encapsulated with a layer of vacuum-deposited Teflon, while others were left without encapsulation, and the thermal stress was performed either in nitrogen or in air. We found that the encapsulation with Teflon has virtually no effect on the thermal stability of our TFTs. In contrast, the ambient in which the thermal stress is conducted was found to have a measurable effect, but in a surprising way: When the thermal stress is carried out in nitrogen, the mobility drops to 70% of its initial value at a temperature of 160 °C and to close to zero at 170 °C, whereas when the stress is performed in air, the mobility remains at 75% of its initial value up to a temperature of 160 °C and at 60% up to 180 °C. To understand this behavior, we studied the effect of the thermal stress on the semiconductor thin-film morphology by scanning electron microscopy. While the DNTT films remain continuous and conducting when the heating is carried out in air, the semiconductor morphology undergoes a dramatic change, including the formation of large, thick crystals of DNTT and a complete loss of percolation, when the heating is conducted in nitrogen. We also found that when the TFTs are heated to a temperature of 200 °C in air, all TFTs with a channel length greater than 50 µm are destroyed, while TFTs with a channel length of less than 50 µm survive, whereas when the TFTs are heated to the same temperature (200 °C) in nitrogen, only the TFTs with a channel smaller than 8 µm survive. This result is also linked to the thermally induced changes in the semiconductor morphology.

Keywords: organic thin-film transistors, encapsulation, thermal stability, thin-film morphology

Procedia PDF Downloads 313