Search results for: Thermoelectric chip

Authors: Saleh Alshehri

Abstract:

Thermoelectric technology is currently being used in many industrial applications for cooling, heating and generating electricity. This research mainly focuses on using thermoelectric to cool down high-speed computer chips at different operating conditions. A previously developed and validated three-dimensional model for optimizing and assessing the performance of cascaded thermoelectric and non-cascaded thermoelectric is used in this study to investigate the possibility of decreasing the hotspot temperature of computer chip. Additionally, a test assembly is built and tested at steady-state and transient conditions. The obtained optimum thermoelectric current at steady-state condition is used to conduct a number of pulsed tests (i.e. transient tests) with different shapes to cool the computer chips hotspots. The results of the steady-state tests showed that at hotspot heat rate of 15.58 W (5.97 W/cm²), using thermoelectric current of 4.5 A has resulted in decreasing the hotspot temperature at open circuit condition (89.3 °C) by 50.1 °C. Maximum and minimum hotspot temperatures have been affected by ON and OFF duration of the electrical current pulse. Maximum hotspot temperature was resulted by longer OFF pulse period. In addition, longer ON pulse period has generated the minimum hotspot temperature.

Keywords: Thermoelectric generator, thermoelectric cooler, chip hotspots, electronic cooling.

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Authors: Hsin-Hung Chang, Jin-Lung Guan, Ming-Ta Yang

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This paper presents a compact thermoelectric power generator system based on temperature difference across the element. The system can transfer the burning heat energy to electric energy directly. The proposed system has a thermoelectric generator and a power control box. In the generator, there are 4 thermoelectric modules (TEMs), each of which uses 2 thermoelectric chips (TEs) and 2 cold sinks, 1 thermal absorber, and 1 thermal conduction flat board. In the power control box, there are 1 storing energy device, 1 converter, and 1 inverter. The total net generating power is about 11W. This system uses commercial portable gas stoves or burns timber or the coal as the heat source, which is easily obtained. It adopts solid-state thermoelectric chips as heat inverter parts. The system has the advantages of being light-weight, quite, and mobile, requiring no maintenance, and havng easily-supplied heat source. The system can be used a as long as burning is allowed. This system works well for highly-mobilized outdoors situations by providing a power for illumination, entertainment equipment or the wireless equipment at refuge. Under heavy storms such as typhoon, when the solar panels become ineffective and the wind-powered machines malfunction, the thermoelectric power generator can continue providing the vital power.

Keywords: Thermoelectric chip, seekback effect, thermo electric power generator.

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Authors: Y. Li, K. Buddharaju, N. Singh, G. Q. Lo, S. J. Lee

Abstract:

Silicon nanowire (SiNW) based thermoelectric device (TED) has potential applications in areas such as chip level cooling/ energy harvesting. It is a great challenge however, to assemble an efficient device with these SiNW. The presence of parasitic in the form of interfacial electrical resistance will have a significant impact on the performance of the TED. In this work, we explore the effect of the electrical contact resistance on the performance of a TED. Numerical simulations are performed on SiNW to investigate such effects on its cooling performance. Intrinsically, SiNW individually without the unwanted parasitic effect has excellent cooling power density. However, the cooling effect is undermined with the contribution of the electrical contact resistance.

Keywords: Thermoelectric, silicon, nanowire, electrical contact resistance, parasitics.

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Authors: G. Korotcenkov, V. Brinzari, B. K. Cho

Abstract:

The thermoelectric properties of nano-scaled In₂O₃:Sn films deposited by spray pyrolysis are considered in the present report. It is shown that multicomponent In₂O₃:Sn-based films are promising material for the application in thermoelectric devices. It is established that the increase in the efficiency of thermoelectric conversion at C_Sn~5% occurred due to nano-scaled structure of the films studied and the effect of the grain boundary filtering of the low energy electrons. There are also analyzed the limitations that may appear during such material using in devices developed for the market of thermoelectric generators and refrigerators. Studies showed that the stability of nano-scaled film’s parameters is the main problem which can limit the application of these materials in high temperature thermoelectric converters.

Keywords: Energy conversion technologies, thermoelectricity, In2O3-based films, power factor, nanocomposites, stability.

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Authors: Muthana Saleh Alalaki, Michael Opoku Agyeman

Abstract:

The growth in the number of Intellectual Properties (IPs) or the number of cores on the same chip becomes a critical issue in System-on-Chip (SoC) due to the intra-communication problem between the chip elements. As a result, Network-on-Chip (NoC) has emerged as a system architecture to overcome intra-communication issues. This paper presents a study of recent contributions on simulation tools for NoC. Furthermore, an overview of NoC is covered as well as a comparison between some NoC simulators to help facilitate research in on-chip communication.

Keywords: Network-on-Chip, System-on-Chip, embedded systems, computer architecture.

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Authors: L. C. Ding, Bradley. G. Orr, K. Rahaoui, S. Truza, A. Date, A. Akbarzadeh

Abstract:

The research on thermoelectric has been a blooming field of research for the latest decade, owing to large amount of heat source available to be harvested, being eco-friendly and static in operation. This paper provides the performance of thermoelectric generator (TEG) with bulk material of bismuth telluride, Bi₂Te₃. Later, the performance of the TEGs is evaluated by considering attaching the TEGs on a plastic (polyethylene sheet) in contrast to the common method of attaching the TEGs on the metal surface.

Keywords: Electric power, heat transfer, renewable energy, thermoelectric generator.

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Authors: Jae Young Park, Soongyu Kwon, Kyu Han Kim, Hyeong Geon Lee, Jong Tae Kim

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This paper considers the problem of finding low cost chip set for a minimum cost partitioning of a large logic circuits. Chip sets are selected from a given library. Each chip in the library has a different price, area, and I/O pin. We propose a low cost chip set selection algorithm. Inputs to the algorithm are a netlist and a chip information in the library. Output is a list of chip sets satisfied with area and maximum partitioning number and it is sorted by cost. The algorithm finds the sorted list of chip sets from minimum cost to maximum cost. We used MCNC benchmark circuits for experiments. The experimental results show that all of chip sets found satisfy the multiple partitioning constraints.

Keywords: lowest cost chip set, MCNC benchmark, multi-way partitioning.

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Authors: Thomas Canhao Xu, Bo Yang, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen

Abstract:

With the increasing number of on-chip components and the critical requirement for processing power, Chip Multiprocessor (CMP) has gained wide acceptance in both academia and industry during the last decade. However, the conventional bus-based onchip communication schemes suffer from very high communication delay and low scalability in large scale systems. Network-on-Chip (NoC) has been proposed to solve the bottleneck of parallel onchip communications by applying different network topologies which separate the communication phase from the computation phase. Observing that the memory bandwidth of the communication between on-chip components and off-chip memory has become a critical problem even in NoC based systems, in this paper, we propose a novel 3D NoC with on-chip Dynamic Random Access Memory (DRAM) in which different layers are dedicated to different functionalities such as processors, cache or memory. Results show that, by using our proposed architecture, average link utilization has reduced by 10.25% for SPLASH-2 workloads. Our proposed design costs 1.12% less execution cycles than the traditional design on average.

Keywords: 3D integration, network-on-chip, memory-on-chip, DRAM, chip multiprocessor.

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Authors: Rohaya Abdul Wahab, Raja Mohd Fuad Tengku Aziz, Nazaliza Othman, Sharifah Saleh, Nabihah Razali, Rozaimah Baharim, Md Hanif Md Nasir

Abstract:

This paper will discuss flip chip methodology, in which I/O pads, standard cells, macros and bump cells array are placed in the floorplan, then routed using Astro place and route tool. Final DRC and LVS checking is done using Calibre verification tool. The design vehicle to run this methodology is an OpenRISC design targeted to Silterra 0.18 micrometer technology with 6 metal layers for routing. Astro has extensive support for flip chip placement and routing. Astro tool commands for flip chip are straightforward approach like the conventional standard wire bond packaging. However since we do not have flip chip commands in our Astro tool, no LEF file for bump cell and no LEF file for flip chip I/O pad, we create our own methodology to prepare for future flip chip tapeout. 

Keywords: Astro, bump cell, Calibre, flip chip, LEF, methodology, SCHEME, TCL.

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Authors: Yannick Verbelen, Sam De Winne, Niek Blondeel, Ann Peeters, An Braeken, Abdellah Touhafi

Abstract:

The growing popularity of solid state thermoelectric devices in cooling applications has sparked an increasing diversity of thermoelectric coolers (TECs) on the market, commonly known as “Peltier modules”. They can also be used as generators, converting a temperature difference into electric power, and opportunities are plentiful to make use of these devices as thermoelectric generators (TEGs) to supply energy to low power, autonomous embedded electronic applications. Their adoption as energy harvesters in this new domain of usage is obstructed by the complex thermoelectric models commonly associated with TEGs. Low cost TECs for the consumer market lack the required parameters to use the models because they are not intended for this mode of operation, thereby urging an alternative method to obtain electric power estimations in specific operating conditions. The design of the test setup implemented in this paper is specifically targeted at benchmarking commercial, off-the-shelf TECs for use as energy harvesters in domestic environments: applications with limited temperature differences and space available. The usefulness is demonstrated by testing and comparing single and multi stage TECs with different sizes. The effect of a boost converter stage on the thermoelectric end-to-end efficiency is also discussed.

Keywords: Thermoelectric cooler, TEC, complementary balanced energy harvesting, step-up converter, DC/DC converter, embedded systems, energy harvesting, thermal harvesting.

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Authors: V.Sivaraman, S. Sankaran, L. Vijayaraghavan

Abstract:

Machining through turning was carried out in a lathe to study the chip formation of Multiphase Ferrite (F-B-M) microalloyed steel. Taguchi orthogonal array was employed to perform the machining. Continuous and discontinuous chips were formed for different cutting parameters like speed, feed and depth of cut. Optical and scanning electron microscope was employed to identify the chip morphology.

Keywords: Multiphase microalloyed steel, chip formation, Taguchi technique, turning, cutting parameters

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Authors: Haiyi Zhang, Jianli Guo, Daqian Yang

Abstract:

This Classifying Bird Sounds (chip notes) project-s purpose is to reduce the unwanted noise from recorded bird sound chip notes, design a scheme to detect differences and similarities between recorded chip notes, and classify bird sound chip notes. The technologies of determining the similarities of sound waves have been used in communication, sound engineering and wireless sound applications for many years. Our research is focused on the similarity of chip notes, which are the sounds from different birds. The program we use is generated by Microsoft Cµ.

Keywords: Classify Bird Sounds, Noise Filter, High-pass, Lowpass, Band-pass, Band-stop Filter, FIR.

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Authors: Ziaddin Daie Koozekanani, Mina Zolfy Lighvan

Abstract:

One of the most challengeable issues in ESL (Electronic System Level) design is the lack of a general modeling scheme for on chip communication architecture. In this paper some of the mostly used methodologies for modeling and representation of on chip communication are investigated. Our goal is studying the existing methods to extract the requirements of a general representation scheme for communication architecture synthesis. The next step, will be introducing a modeling and representation method for being used in automatically synthesis process of on chip communication architecture.

Keywords: Communication architecture, System on Chip, Communication Modeling and Representation

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Authors: AL.AL, M. B. I. Reaz, S. M. A. Motakabber, Mohd Alauddin Mohd Ali

Abstract:

Nowadays it is a trend for electronic circuit designers to integrate all system components on a single-chip. This paper proposed the design of a single-chip proportional to absolute temperature (PTAT) sensor including a voltage reference circuit using CEDEC 0.18m CMOS Technology. It is a challenge to design asingle-chip wide range linear response temperature sensor for many applications. The channel widths between the compensation transistor and the reference transistor are critical to design the PTAT temperature sensor circuit. The designed temperature sensor shows excellent linearity between -100°C to 200° and the sensitivity is about 0.05mV/°C. The chip is designed to operate with a single voltage source of 1.6V.

Keywords: PTAT, single-chip circuit, linear temperature sensor, CMOS technology.

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Authors: Jinkyu Park, Yungjin Kim, Byungdeok In, Sangki Park, Kihyung Lee

Abstract:

Internal combustion engines rejects 30-40% of the energy supplied by fuel to the environment through exhaust gas. thus, there is a possibility for further significant improvement of efficiency with the utilization of exhaust gas energy and its conversion to mechanical energy or electrical energy. The Thermo-Electric Generator (TEG) will be located in the exhaust system and will make use of an energy flow between the warmer exhaust gas and the external environment. Predict to th optimum position of temperature distribution and the performance of TEG through numerical analysis. The experimental results obtained show that the power output significantly increases with the temperature difference between cold and hot sides of a thermoelectric generator.

Keywords: Thermoelectric generator, Numerical analysis, Seebeck coefficient, Figure of merit

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Authors: J. Y. Jang, C. Y. Tseng

Abstract:

A three-dimensional numerical model of thermoelectric generator (TEG) modules attached to a large chimney plate is proposed and solved numerically using a control volume based finite difference formulation. The TEG module consists of a thermoelectric generator, an elliptical pin-fin heat sink, and a cold plate for water cooling. In the chimney, the temperature of flue gases is 450-650K. Although the TEG hot-side temperature and thus the electric power output can be increased by inserting an elliptical pin-fin heat sink into the chimney tunnel to increase the heat transfer area, the pin fin heat sink would cause extra pumping power at the same time. The main purpose of this study is to analyze the effects of geometrical parameters on the electric power output and chimney pressure drop characteristics. The effects of different operating conditions, including various inlet velocities (Vin= 1, 3, 5 m/s), inlet temperatures (Tgas = 450, 550, 650K) and different fin height (0 to 150 mm) are discussed in detail. The predicted numerical data for the power vs. current (P-I) curve are in good agreement (within 11%) with the experimental data.

Keywords: Thermoelectric generator, Waste heat recovery, Elliptical pin-fin heat sink.

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Authors: D. Czurratis, Y. Beyl, S. Zinober, R. Zengerle, F. Lärmer

Abstract:

A new concept for long-term reagent storage for Labon- a-Chip (LoC) devices is described. Here we present a polymer multilayer stack with integrated stick packs for long-term storage of several liquid reagents, which are necessary for many diagnostic applications. Stick packs are widely used in packaging industry for storing solids and liquids for long time. The storage concept fulfills two main requirements: First, a long-term storage of reagents in stick packs without significant losses and interaction with surroundings, second, on demand releasing of liquids, which is realized by pushing a membrane against the stick pack through pneumatic pressure. This concept enables long-term on-chip storage of liquid reagents at room temperature and allows an easy implementation in different LoC devices.

Keywords: Lab-on-a-Chip, long-term storage, reagent storage, stick pack.

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Authors: Reza Hadjiaghaie Vafaie, Aysan Madanpasandi, Behrooz Zare Desari, Seyedmohammad Mousavi

Abstract:

High lamination in microchannel is one of the main challenges in on-chip components like micro total analyzer systems and lab-on-a-chips. Electro-osmotic force is highly effective in chip-scale. This research proposes a microfluidic-based micropump for low ionic strength solutions. Narrow microchannels are designed to generate an efficient electroosmotic flow near the walls. Microelectrodes are embedded in the lateral sides and actuated by low electric potential to generate pumping effect inside the channel. Based on the simulation study, the fluid velocity increases by increasing the electric potential amplitude. We achieve a net flow velocity of 100 µm/s, by applying +/- 2 V to the electrode structures. Our proposed low voltage design is of interest in conventional lab-on-a-chip applications.

Keywords: Integration, electrokinetic, on-chip, fluid pumping, microfluidic.

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Authors: Doshi N. A., Dhobale S. B., Kakade S. R.

Abstract:

As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance, LFSR (Linear Feedback Shift Register) is implemented in layout level which develops the low power consumption chip, using recent CMOS, sub-micrometer layout tools. Thus LFSR counter can be a new trend setter in cryptography and is also beneficial as compared to GRAY & BINARY counter and variety of other applications. This paper compares 3 architectures in terms of the hardware implementation, CMOS layout and power consumption, using Microwind CMOS layout tool. Thus it provides solution to a low power architecture implementation of LFSR in CMOS VLSI.

Keywords: Chip technology, Layout level, LFSR, Pass transistor

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Authors: Muhammad Ali, Awais Adnan

Abstract:

Network on a chip (NoC) has been proposed as a viable solution to counter the inefficiency of buses in the current VLSI on-chip interconnects. However, as the silicon chip accommodates more transistors, the probability of transient faults is increasing, making fault tolerance a key concern in scaling chips. In packet based communication on a chip, transient failures can corrupt the data packet and hence, undermine the accuracy of data communication. In this paper, we present a comparative analysis of transient fault tolerant techniques including end-to-end, node-by-node, and stochastic communication based on flooding principle.

Keywords: NoC, fault-tolerance, transient faults.

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Authors: Minsoo Lee, Yearn Jeong Kim, Yun-mi Kim, Sujeung Cheong, Sookyung Song

Abstract:

Bio-chips are used for experiments on genes and contain various information such as genes, samples and so on. The two-dimensional bio-chips, in which one axis represent genes and the other represent samples, are widely being used these days. Instead of experimenting with real genes which cost lots of money and much time to get the results, bio-chips are being used for biological experiments. And extracting data from the bio-chips with high accuracy and finding out the patterns or useful information from such data is very important. Bio-chip analysis systems extract data from various kinds of bio-chips and mine the data in order to get useful information. One of the commonly used methods to mine the data is classification. The algorithm that is used to classify the data can be various depending on the data types or number characteristics and so on. Considering that bio-chip data is extremely large, an algorithm that imitates the ecosystem such as the ant algorithm is suitable to use as an algorithm for classification. This paper focuses on finding the classification rules from the bio-chip data using the Ant Colony algorithm which imitates the ecosystem. The developed system takes in consideration the accuracy of the discovered rules when it applies it to the bio-chip data in order to predict the classes.

Keywords: Ant Colony System, DNA chip data, Classification.

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Authors: Sin J. Chen, Jyh J. Chen

Abstract:

This study describes a micro device integrated with multi-chamber for polymerase chain reaction (PCR) with different annealing temperatures. The device consists of the reaction polydimethylsiloxane (PDMS) chip, a cover glass chip, and is equipped with cartridge heaters, fans, and thermocouples for temperature control. In this prototype, commercial software is utilized to determine the geometric and operational parameters those are responsible for creating the denaturation, annealing, and extension temperatures within the chip. Two cartridge heaters are placed at two sides of the chip and maintained at two different temperatures to achieve a thermal gradient on the chip during the annealing step. The temperatures on the chip surface are measured via an infrared imager. Some thermocouples inserted into the reaction chambers are used to obtain the transient temperature profiles of the reaction chambers during several thermal cycles. The experimental temperatures compared to the simulated results show a similar trend. This work should be interesting to persons involved in the high-temperature based reactions and genomics or cell analysis.

Keywords: Polymerase chain reaction, thermal cycles, temperature gradient, micro-fabrication.

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Authors: Eduardo Sant'Ana da Silva, Andre Luiz Pires Guedes, Eduardo Todt

Abstract:

Independent spanning trees (ISTs) provide a number of advantages in data broadcasting. One can cite the use in fault tolerance network protocols for distributed computing and bandwidth. However, the problem of constructing multiple ISTs is considered hard for arbitrary graphs. In this paper we present an efficient algorithm to construct ISTs on hypercubes that requires minimum resources to be performed.

Keywords: Hypercube, Independent Spanning Trees, Networks On Chip, Systems On Chip.

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Authors: Mansi Jhamb, R. K. Sharma, A. K. Gupta

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The distribution of a single global clock across a chip has become the major design bottleneck for high performance VLSI systems owing to the power dissipation, process variability and multicycle cross-chip signaling. A Network-on-Chip (NoC) architecture partitioned into several synchronous blocks has become a promising approach for attaining fine-grain power management at the system level. In a NoC architecture the communication between the blocks is handled asynchronously. To interface these blocks on a chip operating at different frequencies, an asynchronous FIFO interface is inevitable. However, these asynchronous FIFOs are not required if adjacent blocks belong to the same clock domain. In this paper, we have designed and analyzed a 16-bit asynchronous micropipelined FIFO of depth four, with the awareness of place and route on an FPGA device. We have used a commercially available Spartan 3 device and designed a high speed implementation of the asynchronous 4-phase micropipeline. The asynchronous FIFO implemented on the FPGA device shows 76 Mb/s throughput and a handshake cycle of 109 ns for write and 101.3 ns for read at the simulation under the worst case operating conditions (voltage = 0.95V) on a working chip at the room temperature.

Keywords: Asynchronous, FIFO, FPGA, GALS, Network-on- Chip (NoC), VHDL.

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Authors: Li Long, Thomas Ortlepp

Abstract:

The transport properties of carriers in polycrystalline silicon film affect the performance of polycrystalline silicon-based devices. They depend strongly on the grain structure, grain boundary trap properties and doping concentration, which in turn are determined by the film deposition and processing conditions. Based on the properties of charge carriers, phonons, grain boundaries and their interactions, the thermoelectric properties of polycrystalline silicon are analyzed with the relaxation time approximation of the Boltzmann transport equation. With this approach, thermal conductivity, electrical conductivity and Seebeck coefficient as a function of grain size, trap properties and doping concentration can be determined. Experiment on heavily doped polycrystalline silicon is carried out and measurement results are compared with the model.

Keywords: Conductivity, polycrystalline silicon, relaxation time approximation, Seebeck coefficient, thermoelectric property.

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Authors: Samy E. Oraby, Ayman M. Alaskari

Abstract:

The importance of machining process in today-s industry requires the establishment of more practical approaches to clearly represent the intimate and severe contact on the tool-chipworkpiece interfaces. Mathematical models are developed using the measured force signals to relate each of the tool-chip friction components on the rake face to the operating cutting parameters in rough turning operation using multilayers coated carbide inserts. Nonlinear modeling proved to have high capability to detect the nonlinear functional variability embedded in the experimental data. While feedrate is found to be the most influential parameter on the friction coefficient and its related force components, both cutting speed and depth of cut are found to have slight influence. Greater deformed chip thickness is found to lower the value of friction coefficient as the sliding length on the tool-chip interface is reduced.

Keywords: Mathematical modeling, Cutting forces, Frictionforces, Friction coefficient and Chip ratio.

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Authors: Yu-Wei Chang, Chiao-Hung Cheng, Wen-Fang Wu, Sih-Li Chen

Abstract:

This article experimentally investigates the thermal performance of thermoelectric air-cooling module which comprises a thermoelectric cooler (TEC) and an air-cooling heat sink. The influences of input current and heat load are determined. And performances under each situation are quantified by thermal resistance analysis. Since TEC generates Joule heat, this nature makes construction of thermal resistance network difficult. To simplify the analysis, this article emphasizes on the resistance heat load might meet when passing through the device. Therefore, the thermal resistances in this paper are to divide temperature differences by heat load. According to the result, there exists an optimum input current under every heating power. In this case, the optimum input current is around 6A or 7A. The performance of the heat sink would be improved with TEC under certain heating power and input current, especially at a low heat load. According to the result, the device can even make the heat source cooler than the ambient. However, TEC is not always effective at every heat load and input current. In some situation, the device works worse than the heat sink without TEC. To determine the availability of TEC, this study figures out the effective operating region in which the TEC air-cooling module works better than the heat sink without TEC. The result shows that TEC is more effective at a lower heat load. If heat load is too high, heat sink with TEC will perform worse than without TEC. The limit of this device is 57W. Besides, TEC is not helpful if input current is too high or too low. There is an effective range of input current, and the range becomes narrower when the heat load grows.

Keywords: Thermoelectric cooler, TEC, electronic cooling, heat sink.

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Authors: Ahmad M. Shafiee, Mehrdad Montazeri, Mahdi Nikdast

Abstract:

Every day human life experiences new equipments more automatic and with more abilities. So the need for faster processors doesn-t seem to finish. Despite new architectures and higher frequencies, a single processor is not adequate for many applications. Parallel processing and networks are previous solutions for this problem. The new solution to put a network of resources on a chip is called NOC (network on a chip). The more usual topology for NOC is mesh topology. There are several routing algorithms suitable for this topology such as XY, fully adaptive, etc. In this paper we have suggested a new algorithm named Intermittent X, Y (IX/Y). We have developed the new algorithm in simulation environment to compare delay and power consumption with elders' algorithms.

Keywords: Computer architecture, parallel computing, NOC, routing algorithm.

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Authors: Pedro Acevedo, Carlos Díaz, Mónica Vázquez, Joel Durán

Abstract:

This paper describes the design of a pulse generator based on the Programmable System-on-Chip (PSoC) module. In this module, using programmable logic is possible to implement different pulses which are required for ultrasonic applications, either in a single channel or multiple channels. This module can operate with programmable frequencies from 3-74 MHz; its programming may be versatile covering a wide range of ultrasonic applications. It is ideal for low-power ultrasonic applications where PZT or PVDF transducers are used.

Keywords: pulse generator, PVDF, Programmable System-on-Chip (PSoC), ultrasonic transducer

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Authors: Michal Spilacek, Marian Brazdil, Otakar Stelcl, Jiri Pospisil

Abstract:

This paper shows an experimental testing of a small unit for combustion of solid fuels, such as charcoal and wood logs, that can provide electricity. One of the concepts is that the unit does not require qualified personnel for its operation. The unit itself is composed of two main parts. The design requires a heat producing stove and electricity producing thermoelectric generator. After the construction the unit was tested and the results show that the emission release is within the legislative requirements for emission production and environmental protection. That qualifies such unit for indoor application.

Keywords: Micro-cogeneration, thermoelectric generator, biomass combustion, wood stove.

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