%0 Journal Article
	%A Rohaya Abdul Wahab and  Raja Mohd Fuad Tengku Aziz and  Nazaliza Othman and  Sharifah Saleh and  Nabihah Razali and  Rozaimah Baharim and  Md Hanif Md Nasir
	%D 2013
	%J International Journal of Electrical and Computer Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 84, 2013
	%T The Methodology of Flip Chip Using Astro Place and Route Tool
	%U https://publications.waset.org/pdf/9996624
	%V 84
	%X This paper will discuss flip chip methodology, in which I/O pads, standard cells, macros and bump cells array are placed in the floorplan, then routed using Astro place and route tool. Final DRC and LVS checking is done using Calibre verification tool. The design vehicle to run this methodology is an OpenRISC design targeted to Silterra 0.18 micrometer technology with 6 metal layers for routing. Astro has extensive support for flip chip placement and routing. Astro tool commands for flip chip are straightforward approach like the conventional standard wire bond packaging. However since we do not have flip chip commands in our Astro tool, no LEF file for bump cell and no LEF file for flip chip I/O pad, we create our own methodology to prepare for future flip chip tapeout. 

	%P 1572 - 1575