An Innovational Intermittent Algorithm in Networks-On-Chip (NOC)

Authors: Ahmad M. Shafiee, Mehrdad Montazeri, Mahdi Nikdast

Abstract:

Every day human life experiences new equipments more automatic and with more abilities. So the need for faster processors doesn-t seem to finish. Despite new architectures and higher frequencies, a single processor is not adequate for many applications. Parallel processing and networks are previous solutions for this problem. The new solution to put a network of resources on a chip is called NOC (network on a chip). The more usual topology for NOC is mesh topology. There are several routing algorithms suitable for this topology such as XY, fully adaptive, etc. In this paper we have suggested a new algorithm named Intermittent X, Y (IX/Y). We have developed the new algorithm in simulation environment to compare delay and power consumption with elders' algorithms.

Keywords: Computer architecture, parallel computing, NOC, routing algorithm.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1333178

References:

[1] Andrew Hamilton. Brains that click. Popular mechanic, 91(3): 162-167, 256, 258, march 1949.
[2] Luca Benini and Giovanni De Micheli, Networks on Chips: A New SoC Paradigm., DATE, Design, Automation and Test in Europe, Paris, March 3 - 7, 2002.
[3] P.Guerrier and A.Greiner .A generic architecture for on-chip packet switched interconnections, In Proc. Of DATE 2000, March 2000.
[4] Shashi Kumar, Axel Jantsch, Juha-Pekka Soininen, Martti Forsell. A Network on Chip Architecture and Design Methodology. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI.02) 0-7695-1486-3/02.
[5] Jingcao Hu, Radu Marculescu, "DyAD - Smart Routing for Networkson- Chip", DAC 2004.
[6] Chiu Ge-Ming. "The Odd-Even Turn Model for Adaptive Routing", IEEE Transactions on Parallel and Distributed Systems, Vol. 11. July 2000, pp. 729-738. 2000.
[7] Z. Guz, I. Walter, E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny. "Efficient Link Capacity and QoS Design for Network-on-Chip".In DATE 2006.
[8] E. Nilsson, M. Millberg, J. Oberg and A. Jantsch, "Load distribution with the proximity congestion awareness in a network on chip," DATE, Germany, 2003, pp. 1126-1127.
[9] J. Hu, R. Marculescu, "DyAD - Smart routing for networks-on-chip," DAC, USA, 2004, pp. 260-263.