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A Study of Recent Contribution on Simulation Tools for Network-on-Chip

Authors: Muthana Saleh Alalaki, Michael Opoku Agyeman


The growth in the number of Intellectual Properties (IPs) or the number of cores on the same chip becomes a critical issue in System-on-Chip (SoC) due to the intra-communication problem between the chip elements. As a result, Network-on-Chip (NoC) has emerged as a system architecture to overcome intra-communication issues. This paper presents a study of recent contributions on simulation tools for NoC. Furthermore, an overview of NoC is covered as well as a comparison between some NoC simulators to help facilitate research in on-chip communication.

Keywords: Network-on-Chip, System-on-Chip, embedded systems, computer architecture.

Digital Object Identifier (DOI):

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[1] C. Zeferino and A. Susin, "SoCIN: a parametric and scalable network-on-chip," in Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th Symposium on, Itajai, 2003.
[2] N. Genko, D. Atienza, G. D. Micheli, L. Benini, J. Mendias, R. Hermida and F. Catthoor, "A novel approach for network on chip emulation," in Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, Bologna, 2005.
[3] P. C. Diniz, Reconfigurable Computing: Architectures, Tools and Applications, Mangaratiba: Springer Science & Business Media, 2007.
[4] S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja and A. Hemani, "A network on chip architecture and design methodology," in VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on, Pittsburgh, 2002.
[5] E. Salminen, V. Lahtinen, K. Kuusilinna and T. Hamalainen, "Overview of bus-based system-on-chip interconnections," in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, Phoenix-Scottsdal, 2002.
[6] R. Hofmann and B. Drerup, "Next Generation CoreConnect (TM) Processor Local Bus architecture," in Annual IEEE International ASIC/SOC Conference, Rochester, 2002.
[7] J. Henkely, W. Wolfz and S. Chakradhary, "On-chip networks: A scalable, communication-centric embedded system design paradigm," in VLSI Design, 2004. Proceedings. 17th International Conference on, Princeton, 2004.
[8] L. Benini and D. Bertozzi, "Network-on-chip architectures and design methods," in IEE Proceedings - Computers and Digital Techniques, 2005.
[9] P. Guerrier and A. Greiner, "A gentic architecture for on-chip packet-switched interconnections," in Design, Automation, and Test in Europe, New York, 2000.
[10] G. D. Micheli, C. Seiculescu, S. Murali, L. Benini, F. Angiolini and A. Pullini, "Networks on Chips: From research to products," in Design Automation Conference (DAC), 2010 47th ACM/IEEE, Lausanne, 2010.
[11] A. Agarwal, C. Iskander and R. Shankar, "Survey of Network on Chip (NoC) Architectures & Contributions," Journal of Engineering, Computing and Architecture, vol. 4, no. 1, 2009.
[12] N. Ashokkumar, P. Nagarajan and S.Ravanaraja3, "Survey Exploration of Network-on-Chip Architecture," Dindigul, 2009.
[13] G. D. Micheli and L. Benini, Networks on Chips: Technology and Tools, Academic Press, 2006.
[14] T. Bjerregaard and S. Mahadevan, "A survey of research and practices of Network-on-chip," ACM Computing Surveys (CSUR), vol. 38, no. 1, 2006.
[15] G. Ascia, V. Catania, M. Palesi and D. Patti, "Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip," in IEEE Transactions on Computers, 2008.
[16] P. Pande, C. Grecu, A. Ivanov, R. Saleh and G. D. Micheli, "Design, synthesis, and test of networks on chips," IEEE Design & Test of Computers, vol. 22, no. 5, pp. 404 - 413, 2005.
[17] A. B. Achballah and S. B. Saoud, "A Survey of Network-On-Chip Tools," International Journal of Advanced Computer Science and Applications (IJACSA), vol. 4, no. 9, 2013.
[18] G.-M. Chiu, "The Odd-Even Turn Model for Adaptive Routing," IEEE Transactions on Parallel and Distributed Systems, vol. 11, no. 7, pp. 729 - 738, 2000.
[19] D. Linder and J. Harden, "An adaptive and fault tolerant wormhole routing strategy for k-ary n-cubes," IEEE Transactions on Computers, vol. 40, no. 1, pp. 2-12, 2002.
[20] J. Wang, X. Wang, L. Huang, T. Mak and G. Li, "A Fault-Tolerant Routing Algorithm for NoC Using Farthest Reachable Routers," in IEEE 11th International Conference on Dependable, Autonomic and Secure Computing, Chengdu, 2013.
[21] B. B. Sayankar, P. Agrawal and S. S. Dorle, "Routing Algorithms for NoC Architecture: A Relative Analysis," in 6th International Conference on Emerging Trends in Engineering and Technology, Nagpur, 2013.
[22] Y. Dong, Z. Lin and T. Watanabe, "An efficient hardware routing algorithms for NoC," in IEEE Region 10 Conference, Fukuoka, 2010.
[23] Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang and A. Choudhary, "Firefly: illuminating future network-on-chip with nanophotonics," in Proceedings of the 36th International Symposium on Computer, 2009.
[24] N. Jiang, J. Kim and W. J. Dally, "Indirect adaptive routing on large scale interconnection networks," in Proceedings of the 36th International Symposium on Computer Architecture,, 2009.
[25] N. Jiang, J. Balfour, D. U. Becker, B. Towles, W. J. Dally, G. Michelogiannakis and J. Kim, "A detailed and flexible cycle-accurate Network-on-Chip simulator," in Performance Analysis of Systems and Software (ISPASS), 2013 IEEE International Symposium on, Austin, 2013.
[26] M. Lis, K. S. Shim, M. H. Cho, P. Ren, O. Khan and S. Devadas, "DARSIM: a parallel cycle-level NoC simulator," in IEEE Asian Solid-State Circuits Conference, Saint Malo, 2010.
[27] N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish and D. A. Wood, "The gem5 Simulator," ACM SIGARCH Computer Architecture News , vol. 39, no. 2, pp. 1-7, 2011.
[28] D. J. S., B. M. B., M. R. M., M. X., A. R. A., K. E. M., M. D. H., D. A. W. and Milo M.K. Martin, "Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset," Computer Architecture News (CAN), vol. 33, no. 4, pp. 92 - 99, 2005.
[29] N. L. Binkert, R. G. Dreslinski, L. R. H. K. T. Lim, A. G. Saidi and S. K. Reinhardt, "The M5 Simulator: Modeling Networked Systems," in IEEE Micro, 2006.
[30] J. Power, J. Hestness, M. S. Orr, M. D. Hill and D. A. Wood, "gem5-gpu: A Heterogeneous CPU-GPU Simulator," IEEE Computer Architecture Letters, vol. 14, no. 1, pp. 34 - 36, 2014.
[31] S. H. Nikounia and S. M. author, "Gem5v: a modified gem5 for simulating virtualized systems," The Journal of Supercomputing, vol. 71, no. 4, p. 1484–1504, 2015.
[32] M. Amoretti, "Modeling and Simulation of Network-on-Chip Systems with DEVS and DEUS," Scientific World Journal, 2014.
[33] V. Catania, A. Mineo, S. Monteleone, M. Palesi and D. Patti, "Noxim: An Open, Extensible and Cycle-accurate Network on Chip Simulator," in Application-specific Systems, Architectures and Processors (ASAP), 2015 IEEE 26th International Conference on, Toronto, 2015.
[34] Y. Ben-Itzhak, E. Zahavi, I. Cidon and A. Kolodny, "HNOCS: Modular open-source simulator for Heterogeneous NoCs," in Embedded Computer Systems (SAMOS), 2012 International Conference on, Samos, 2013.
[35] H. Hossain, M. Ahmed, A. Al-Nayeem, T. Z. Islam and M. M. Akbar, "Gpnocsim - A General Purpose Simulator for Network-On-Chip," in Information and Communication Technology, 2007. ICICT '07. International Conference on, Dhaka, 2008.
[36] H. M. Kamali and S. Hessabi, "AdapNoC: A fast and flexible FPGA-based NoC simulator," in Field Programmable Logic and Applications (FPL), 2016 26th International Conference on, Lausanne, 2016.
[37] P. W. Viglucci and A. Carpenter, "ENoCS: An Interactive Educational Network-on-Chip Simulator," in ASEE Annual Conference & Exposition, New Orleans, 2016.
[38] P. Wehner, J. Rettkowski, T. Kleinschmidt and D. Göhringe, "MPSoCSim: An extended OVP Simulator for Modeling and Evaluation of Network-on-Chip based heterogeneous MPSoCs," in Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Samos, 2015.
[39] D. Wang, C. Lo, J. Vasiljevic, N. E. Jerger and G. Steffan, "DART: A programmable architecture for NoC simulation on FPGAs," IEEE Transactions on Computers, vol. 63, no. 3, pp. 664 - 678, 2014.
[40] T. Carlson, W. Heirman and L. Eeckhout, "Sniper: Exploring the Level of Abstraction for Scalable and Accurate Parallel Multi-Core Simulation," Intel Labs Europe, 2015.
[41] K. Swaminathan, D. Thakyal, S. G. Nambiar, G. Lakshminarayanan and S.-B. Ko, "Enhanced Noxim Simulator for Performance Evaluation of Network on Chip Topologies," in Engineering and Computational Sciences (RAECS), 2014 Recent Advances in, Chandigarh, 2014.
[42] H.-Y. Wang, C.-H. Chao, T.-C. Yin and A.-Y. Wu, "Buffer Depth Allocation for Thermal-Aware 3D Network-on-Chip Design," in Routing Algorithms in Networks-on-Chip, Springer, 2013, pp. 307-338.
[43] K. Manna, S. Chattopadhyay and I. Sengupta, "Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip," in Very Large Scale Integration (VLSI-SoC), 2014 22nd International Conference on, Playa del Carmen, 2014.