Search results for: Hardware pipeline
Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 520

Search results for: Hardware pipeline

280 An Authoring Tool for Vibrotactile Images

Authors: Da-Hye Kim, Won-Hyung Park, In-Ho Yun, Jeong Cheol Kim, Sang-Youn Kim

Abstract:

This paper presents an authoring tool which makes a user easily and intuitively design vibrotactile sensation. A mobile hardware platform powered by ANDROID, a multi-purpose haptic driver and a linear resonance actuator are used to implement the system of the presented authoring tool. The tool allows users to easily and simply create a vibrotactile sensation by drawing vibrotactile images and to feel the sensation by rubbing drawn images on the touch screen of a mobile device. The tool supports a graphical interface for designing, editing and playing vibrotactile images as well as a pre-defined file format for save and open.

Keywords: authoring tool, mobile device, vibrotactile pattern, vibrotactile sensation

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279 FPGA Implementation of RSA Encryption Algorithm for E-Passport Application

Authors: Khaled Shehata, Hanady Hussien, Sara Yehia

Abstract:

Securing the data stored on E-passport is a very important issue. RSA encryption algorithm is suitable for such application with low data size. In this paper the design and implementation of 1024 bit-key RSA encryption and decryption module on an FPGA is presented. The module is verified through comparing the result with that obtained from MATLAB tools. The design runs at a frequency of 36.3 MHz on Virtex-5 Xilinx FPGA. The key size is designed to be 1024-bit to achieve high security for the passport information. The whole design is achieved through VHDL design entry which makes it a portable design and can be directed to any hardware platform.

Keywords: RSA, VHDL, FPGA, modular multiplication, modular exponential.

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278 Surveillance of Super-Extended Objects: Bimodal Approach

Authors: Andrey V. Timofeev, Dmitry Egorov

Abstract:

This paper describes an effective solution to the task of a remote monitoring of super-extended objects (oil and gas pipeline, railways, national frontier). The suggested solution is based on the principle of simultaneously monitoring of seismoacoustic and optical/infrared physical fields. The principle of simultaneous monitoring of those fields is not new but in contrast to the known solutions the suggested approach allows to control super-extended objects with very limited operational costs. So-called C-OTDR (Coherent Optical Time Domain Reflectometer) systems are used to monitor the seismoacoustic field. Far-CCTV systems are used to monitor the optical/infrared field. A simultaneous data processing provided by both systems allows effectively detecting and classifying target activities, which appear in the monitored objects vicinity. The results of practical usage had shown high effectiveness of the suggested approach.

Keywords: Bimodal processing, C-OTDR monitoring system, LPboost, SVM.

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277 Hardware Description Language Design of Σ-Δ Fractional-N Phase-Locked Loop for Wireless Applications

Authors: Ahmed El Oualkadi, Abdellah Ait Ouahman

Abstract:

This paper discusses a systematic design of a Σ-Δ fractional-N Phase-Locked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed behavior of this PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different specifications of the PLL. The effect of different noise sources has been efficiently introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models for wireless applications in the frequency range around 2.45 GHz.

Keywords: Phase-locked loop, frequency synthesizer, fractional-N PLL, Σ-Δ modulator, HDL models

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276 A Novel Transmission Scheme for Reliable Cooperative Communication

Authors: Won-Jun Choi, Seung-Jun Yu, Jung-In Baik, Hyoung-Kyu Song

Abstract:

Cooperative communication scheme can be substituted for multiple-input multiple-output (MIMO) technique when it may not be able to support multiple antennas due to size, cost or hardware limitations. In other words, cooperative communication scheme is an efficient method to achieve spatial diversity without multiple antennas. For satisfaction of rising QoS, we propose a reliable cooperative communication scheme with M-QAM based Dual Carrier Modulation (M-DCM), which can increase diversity gain. Although our proposed scheme is very simple method, it gives us frequency and spatial diversity. Simulation result shows our proposed scheme obtains diversity gain more than the conventional cooperative communication scheme.

Keywords: cooperation, diversity, M-DCM, OFDM.

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275 A Study on the Least Squares Reduced Parameter Approximation of FIR Digital Filters

Authors: S. Seyedtabaii, E. Seyedtabaii

Abstract:

Rounding of coefficients is a common practice in hardware implementation of digital filters. Where some coefficients are very close to zero or one, as assumed in this paper, this rounding action also leads to some computation reduction. Furthermore, if the discarded coefficient is of high order, a reduced order filter is obtained, otherwise the order does not change but computation is reduced. In this paper, the Least Squares approximation to rounded (or discarded) coefficient FIR filter is investigated. The result also succinctly extended to general type of FIR filters.

Keywords: Digital filter, filter approximation, least squares, model order reduction.

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274 A Middleware Management System with Supporting Holonic Modules for Reconfigurable Management System

Authors: Roscoe McLean, Jared Padayachee, Glen Bright

Abstract:

There is currently a gap in the technology covering the rapid establishment of control after a reconfiguration in a Reconfigurable Manufacturing System. This gap involves the detection of the factory floor state and the communication link between the factory floor and the high-level software. In this paper, a thin, hardware-supported Middleware Management System (MMS) is proposed and its design and implementation are discussed. The research found that a cost-effective localization technique can be combined with intelligent software to speed up the ramp-up of a reconfigured system. The MMS makes the process more intelligent, more efficient and less time-consuming, thus supporting the industrial implementation of the RMS paradigm.

Keywords: Intelligent systems, middleware, reconfigurable manufacturing.

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273 Grid Learning; Computer Grid Joins to e- Learning

Authors: A. Nassiry, A. Kardan

Abstract:

According to development of communications and web-based technologies in recent years, e-Learning has became very important for everyone and is seen as one of most dynamic teaching methods. Grid computing is a pattern for increasing of computing power and storage capacity of a system and is based on hardware and software resources in a network with common purpose. In this article we study grid architecture and describe its different layers. In this way, we will analyze grid layered architecture. Then we will introduce a new suitable architecture for e-Learning which is based on grid network, and for this reason we call it Grid Learning Architecture. Various sections and layers of suggested architecture will be analyzed; especially grid middleware layer that has key role. This layer is heart of grid learning architecture and, in fact, regardless of this layer, e-Learning based on grid architecture will not be feasible.

Keywords: Distributed learning, Grid Learning, Grid network, SCORM standard.

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272 A New Efficient Scalable BIST Full Adder using Polymorphic Gates

Authors: M. Mashayekhi, H. H. Ardakani, A. Omidian

Abstract:

Among various testing methodologies, Built-in Self- Test (BIST) is recognized as a low cost, effective paradigm. Also, full adders are one of the basic building blocks of most arithmetic circuits in all processing units. In this paper, an optimized testable 2- bit full adder as a test building block is proposed. Then, a BIST procedure is introduced to scale up the building block and to generate a self testable n-bit full adders. The target design can achieve 100% fault coverage using insignificant amount of hardware redundancy. Moreover, Overall test time is reduced by utilizing polymorphic gates and also by testing full adder building blocks in parallel.

Keywords: BIST, Full Adder, Polymorphic Gate

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271 The Possibility of Solving a 3x3 Rubik’s Cube under 3 Seconds

Authors: Chung To Kong, Siu Ming Yiu

Abstract:

Rubik's cube was invented in 1974. Since then, speedcubers all over the world try their best to break the world record again and again. The newest record is 3.47 seconds. There are many factors that affect the timing including turns per second (tps), algorithm, finger trick, and hardware of the cube. In this paper, the lower bound of the cube solving time will be discussed using convex optimization. Extended analysis of the world records will be used to understand how to improve the timing. With the understanding of each part of the solving step, the paper suggests a list of speed improvement technique. Based on the analysis of the world record, there is a high possibility that the 3 seconds mark will be broken soon.

Keywords: Rubik’s cube, convex optimization, speed cubing, CFOP.

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270 GPU-Based Volume Rendering for Medical Imagery

Authors: Hadjira Bentoumi, Pascal Gautron, Kadi Bouatouch

Abstract:

We present a method for fast volume rendering using graphics hardware (GPU). To our knowledge, it is the first implementation on the GPU. Based on the Shear-Warp algorithm, our GPU-based method provides real-time frame rates and outperforms the CPU-based implementation. When the number of slices is not sufficient, we add in-between slices computed by interpolation. This improves then the quality of the rendered images. We have also implemented the ray marching algorithm on the GPU. The results generated by the three algorithms (CPU-based and GPU-based Shear- Warp, GPU-based Ray Marching) for two test models has proved that the ray marching algorithm outperforms the shear-warp methods in terms of speed up and image quality.

Keywords: Volume rendering, graphics processors

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269 Development of Configuration Software of Space Environment Simulator Control System Based on Linux

Authors: Zhan Haiyang, Zhang Lei, Ning Juan

Abstract:

This paper presents a configuration software solution in Linux, which is used for the control of space environment simulator. After introducing the structure and basic principle, it is said that the developing of QT software frame and the dynamic data exchanging between PLC and computer. The OPC driver in Linux is also developed. This driver realizes many-to-many communication between hardware devices and SCADA software. Moreover, an algorithm named “Scan PRI” is put forward. This algorithm is much more optimizable and efficient compared with "Scan in sequence" in Windows. This software has been used in practical project. It has a good control effect and can achieve the expected goal.

Keywords: Linux OS, configuration software, OPC server driver, MYSQL database.

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268 Access Control System: Monitoring Tool for Fiber to the Home Passive Optical Network

Authors: Aswir Premadi, Mohammad Syuhaimi Ab. Rahman, Mohamad Najib Moh. Saupe, KasmiranJumari

Abstract:

An optical fault monitoring in FTTH-PON using ACS is demonstrated. This device can achieve real-time fault monitoring for protection feeder fiber. In addition, the ACS can distinguish optical fiber fault from the transmission services to other customers in the FTTH-PON. It is essential to use a wavelength different from the triple-play services operating wavelengths for failure detection. ACS is using the operating wavelength 1625 nm for monitoring and failure detection control. Our solution works on a standard local area network (LAN) using a specially designed hardware interfaced with a microcontroller integrated Ethernet.

Keywords: ACS, monitoring tool, FTTH-PON.

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267 LFSR Counter Implementation in CMOS VLSI

Authors: Doshi N. A., Dhobale S. B., Kakade S. R.

Abstract:

As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance, LFSR (Linear Feedback Shift Register) is implemented in layout level which develops the low power consumption chip, using recent CMOS, sub-micrometer layout tools. Thus LFSR counter can be a new trend setter in cryptography and is also beneficial as compared to GRAY & BINARY counter and variety of other applications. This paper compares 3 architectures in terms of the hardware implementation, CMOS layout and power consumption, using Microwind CMOS layout tool. Thus it provides solution to a low power architecture implementation of LFSR in CMOS VLSI.

Keywords: Chip technology, Layout level, LFSR, Pass transistor

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266 Analysis and Experimentation of Interleaved Boost Converter with Ripple Steering for Power Factor Correction

Authors: A. Inba Rexy, R. Seyezhai

Abstract:

Through the fast growing technologies, design of power factor correction (PFC) circuit is facing several challenges. In this paper, a two-phase interleaved boost converter with ripple steering technique is proposed. Among the various topologies, Interleaved Boost converter (IBC) is considered as superior due to enriched performance, lower ripple content, compact weight and size. A thorough investigation is presented here for the proposed topology. Simulation study for the IBC has been carried out using MATLAB/SIMULINK. Theoretical analysis and hardware prototype has been performed to validate the results.

Keywords: Interleaved Boost Converter (IBC), Power Factor Correction (PFC), Ripple Steering Technique, Ripple, and Simulation.

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265 The Experiences of South-African High-School Girls in a Fab Lab Environment

Authors: Nomusa Dlodlo, Ronald Noel Beyers

Abstract:

This paper reports on an effort to address the issue of inequality in girls- and women-s access to science, engineering and technology (SET) education and careers through raising awareness on SET among secondary school girls in South Africa. Girls participated in hands-on high-tech rapid prototyping environment of a fabrication laboratory that was aimed at stimulating creativity and innovation as part of a Fab Kids initiative. The Fab Kids intervention is about creating a SET pipeline as part of the Young Engineers and Scientists of Africa Initiative.The methodology was based on a real world situation and a hands-on approach. In the process, participants acquired a number of skills including computer-aided design, research skills, communication skills, teamwork skills, technical drawing skills, writing skills and problem-solving skills. Exposure to technology enhanced the girls- confidence in being able to handle technology-related tasks.

Keywords: Girls, design engineering, gender, science, women.

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264 Design and Implementation of an Intelligent System for Detection of Hazardous Gases using PbPc Sensor Array

Authors: Mahmoud Z. Iskandarani, Nidal F. Shilbayeh

Abstract:

The voltage/current characteristics and the effect of NO2 gas on the electrical conductivity of a PbPc gas sensor array is investigated. The gas sensor is manufactured using vacuum deposition of gold electrodes on sapphire substrate with the leadphathalocyanine vacuum sublimed on the top of the gold electrodes. Two versions of the PbPc gas sensor array are investigated. The tested types differ in the gap sizes between the deposited gold electrodes. The sensors are tested at different temperatures to account for conductivity changes as the molecular adsorption/desorption rate is affected by heat. The obtained results found to be encouraging as the sensors shoed stability and sensitivity towards low concentration of applied NO2 gas.

Keywords: Intelligent System, PbPc, Gas Sensor, Hardware, Software, Neural.

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263 Cloud Computing Databases: Latest Trends and Architectural Concepts

Authors: Tarandeep Singh, Parvinder S. Sandhu

Abstract:

The Economic factors are leading to the rise of infrastructures provides software and computing facilities as a service, known as cloud services or cloud computing. Cloud services can provide efficiencies for application providers, both by limiting up-front capital expenses, and by reducing the cost of ownership over time. Such services are made available in a data center, using shared commodity hardware for computation and storage. There is a varied set of cloud services available today, including application services (salesforce.com), storage services (Amazon S3), compute services (Google App Engine, Amazon EC2) and data services (Amazon SimpleDB, Microsoft SQL Server Data Services, Google-s Data store). These services represent a variety of reformations of data management architectures, and more are on the horizon.

Keywords: Data Management in Cloud, AWS, EC2, S3, SQS, TQG.

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262 Design for Reliability and Manufacturing Yield (Study and Modeling of Defects in Integrated Circuits for their Reliability Analysis)

Authors: G. Ait Abdelmalek, R. Ziani

Abstract:

In this document, we have proposed a robust conceptual strategy, in order to improve the robustness against the manufacturing defects and thus the reliability of logic CMOS circuits. However, in order to enable the use of future CMOS technology nodes this strategy combines various types of design: DFR (Design for Reliability), techniques of tolerance: hardware redundancy TMR (Triple Modular Redundancy) for hard error tolerance, the DFT (Design for Testability. The Results on largest ISCAS and ITC benchmark circuits show that our approach improves considerably the reliability, by reducing the key factors, the area costs and fault tolerance probability.

Keywords: Design for reliability, design for testability, fault tolerance, manufacturing yield.

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261 Supporting Embedded Medical Software Development with MDevSPICE® and Agile Practices

Authors: Surafel Demissie, Frank Keenan, Fergal McCaffery

Abstract:

Emerging medical devices are highly relying on embedded software that runs on the specific platform in real time. The development of embedded software is different from ordinary software development due to the hardware-software dependency. MDevSPICE® has been developed to provide guidance to support such development. To increase the flexibility of this framework agile practices have been introduced. This paper outlines the challenges for embedded medical device software development and the structure of MDevSPICE® and suggests a suitable combination of agile practices that will help to add flexibility and address corresponding challenges of embedded medical device software development.

Keywords: Agile practices, challenges, embedded software, MDevSPICE®, medical device.

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260 Artificial Neural Network Model for a Low Cost Failure Sensor: Performance Assessment in Pipeline Distribution

Authors: Asar Khan, Peter D. Widdop, Andrew J. Day, Aliaster S. Wood, Steve, R. Mounce, John Machell

Abstract:

This paper describes an automated event detection and location system for water distribution pipelines which is based upon low-cost sensor technology and signature analysis by an Artificial Neural Network (ANN). The development of a low cost failure sensor which measures the opacity or cloudiness of the local water flow has been designed, developed and validated, and an ANN based system is then described which uses time series data produced by sensors to construct an empirical model for time series prediction and classification of events. These two components have been installed, tested and verified in an experimental site in a UK water distribution system. Verification of the system has been achieved from a series of simulated burst trials which have provided real data sets. It is concluded that the system has potential in water distribution network management.

Keywords: Detection, leakage, neural networks, sensors, water distribution networks

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259 An E-Retailing System Architecture Based on Cloud Computing

Authors: Chanchai Supaartagorn

Abstract:

E-retailing is the sale of goods online that takes place over the Internet. The Internet has shrunk the entire World. World eretailing is growing at an exponential rate in the Americas, Europe and Asia. However, e-retailing costs require expensive investment, such as hardware, software, and security systems. Cloud computing technology is internet-based computing for the management and delivery of applications and services. Cloud-based e-retailing application models allow enterprises to lower their costs with their effective implementation of e-retailing activities. In this paper, we describe the concept of cloud computing and present the architecture of cloud computing, combining the features of e-retailing. In addition, we propose a strategy for implementing cloud computing with e-retailing. Finally, we explain the benefits from the architecture.

Keywords: Architecture, cloud computing, e-retailing, internet-based.

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258 Effect of Temperature on the Performance of Multi-Stage Distillation

Authors: A. Diaf, H. Aburideh, Z.Tigrine, D. Tassalit, F.Alaoui

Abstract:

The tray/multi-tray distillation process is a topic that has been investigated to great detail over the last decade by many teams such as Jubran et al. [1], Adhikari et al. [2], Mowla et al. [3], Shatat et al. [4] and Fath [5] to name a few. A significant amount of work and effort was spent focusing on modeling and/simulation of specific distillation hardware designs. In this work, we have focused our efforts on investigating and gathering experimental data on several engineering and design variables to quantify their influence on the yield of the multi-tray distillation process. Our goals are to generate experimental performance data to bridge some existing gaps in the design, engineering, optimization and theoretical modeling aspects of the multi-tray distillation process.

Keywords: Distillation, Desalination, Multi-Stage still, Solar Energy

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257 Speedup of Data Vortex Network Architecture

Authors: Qimin Yang

Abstract:

In this paper, 3X3 routing nodes are proposed to provide speedup and parallel processing capability in Data Vortex network architectures. The new design not only significantly improves network throughput and latency, but also eliminates the need for distributive traffic control mechanism originally embedded among nodes and the need for nodal buffering. The cost effectiveness is studied by a comparison study with the previously proposed 2- input buffered networks, and considerable performance enhancement can be achieved with similar or lower cost of hardware. Unlike previous implementation, the network leaves small probability of contention, therefore, the packet drop rate must be kept low for such implementation to be feasible and attractive, and it can be achieved with proper choice of operation conditions.

Keywords: Data Vortex, Packet Switch, Interconnection network, deflection, Network-on-chip

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256 Scanning Device for Sampling the Spatial Distribution of the E-field

Authors: Juan Blas, Alfonso Bahillo, Santiago Mazuelas, David Bullido, Patricia Fernandez, Ruben M. Lorenzo, Evaristo J. Abril

Abstract:

This paper presents a low cost automatic system for sampling the electric field in a limited area. The scanning area is a flat surface parallel to the ground at a selected height. We discuss in detail the hardware, software and all the arrangements involved in the system operation. In order to show the system performance we include a campaign of narrow band measurements with 6017 sample points in the surroundings of a cellular base station. A commercial isotropic antenna with three orthogonal axes was used as sampling device. The results are analyzed in terms of its space average, standard deviation and statistical distribution.

Keywords: measurement device, propagation, spatial sampling.

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255 High Level Synthesis of Kahn Process Networks(KPN) for Streaming Applications

Authors: Attiya Mahmood, Syed Ali Abbas, Shoab A. Khan

Abstract:

Streaming Applications usually run in parallel or in series that incrementally transform a stream of input data. It poses a design challenge to break such an application into distinguishable blocks and then to map them into independent hardware processing elements. For this, there is required a generic controller that automatically maps such a stream of data into independent processing elements without any dependencies and manual considerations. In this paper, Kahn Process Networks (KPN) for such streaming applications is designed and developed that will be mapped on MPSoC. This is designed in such a way that there is a generic Cbased compiler that will take the mapping specifications as an input from the user and then it will automate these design constraints and automatically generate the synthesized RTL optimized code for specified application.

Keywords: KPN, DFG, FPGA

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254 FPGA Implementation of a Vision-Based Blind Spot Warning System

Authors: Yu Ren Lin, Yu Hong Li

Abstract:

Vision-based intelligent vehicle applications often require large amounts of memory to handle video streaming and image processing, which in turn increases complexity of hardware and software. This paper presents an FPGA implement of a vision-based blind spot warning system. Using video frames, the information of the blind spot area turns into one-dimensional information. Analysis of the estimated entropy of image allows the detection of an object in time. This idea has been implemented in the XtremeDSP video starter kit. The blind spot warning system uses only 13% of its logic resources and 95k bits block memory, and its frame rate is over 30 frames per sec (fps).

Keywords: blind-spot area, image, FPGA

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253 Self-Propelled Intelligent Robotic Vehicle Based on Octahedral Dodekapod to Move in Active Branched Pipelines with Variable Cross-Sections

Authors: Sergey N. Sayapin, Anatoly P. Karpenko, Suan H. Dang

Abstract:

Comparative analysis of robotic vehicles for pipe inspection is presented in this paper. The promising concept of self-propelled intelligent robotic vehicle (SPIRV) based on octahedral dodekapod for inspection and operation in active branched pipelines with variable cross-sections is reasoned. SPIRV is able to move in pipeline, regardless of its spatial orientation. SPIRV can also be used to move along the outside of the pipelines as well as in space between surfaces of annular tubes. Every one of faces of the octahedral dodekapod can clamp/unclamp a thing with a closed loop surface of various forms as well as put pressure on environmental surface of contact. These properties open new possibilities for its applications in SPIRV. We examine design principles of octahedral dodekapod as future intelligent building blocks for various robotic vehicles that can self-move and self-reconfigure.

Keywords: Modular robot, octahedral dodekapod, pipe inspection robot, spatial parallel structure.

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252 Wireless Healthcare Monitoring System for Home

Authors: T. Hui Teo, Wee Tiong Tan, Pradeep K. Gopalakrishnan, Victor K. H. Phay, Ma Su M. M. Shwe

Abstract:

A healthcare monitoring system is presented in this paper. This system is based on ultra-low power sensor nodes and a personal server, which is based on hardware and software extensions to a Personal Digital Assistant (PDA)/Smartphone. The sensor node collects data from the body of a patient and sends it to the personal server where the data is processed, displayed and made ready to be sent to a healthcare network, if necessary. The personal server consists of a compact low power receiver module and equipped with a Smartphone software. The receiver module takes less than 30 × 30 mm board size and consumes approximately 25 mA in active mode.

Keywords: healthcare monitoring, sensor node, personal server, wireless.

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251 FPGA Implement of a Vision Based Lane Departure Warning System

Authors: Yu Ren Lin, Yi Feng Su

Abstract:

Using vision based solution in intelligent vehicle application often needs large memory to handle video stream and image process which increase complexity of hardware and software. In this paper, we present a FPGA implement of a vision based lane departure warning system. By taking frame of videos, the line gradient of line is estimated and the lane marks are found. By analysis the position of lane mark, departure of vehicle will be detected in time. This idea has been implemented in Xilinx Spartan6 FPGA. The lane departure warning system used 39% logic resources and no memory of the device. The average availability is 92.5%. The frame rate is more than 30 frames per second (fps).

Keywords: Lane departure warning system, image, FPGA.

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