High Level Synthesis of Kahn Process Networks(KPN) for Streaming Applications

Authors: Attiya Mahmood, Syed Ali Abbas, Shoab A. Khan

Abstract:

Streaming Applications usually run in parallel or in series that incrementally transform a stream of input data. It poses a design challenge to break such an application into distinguishable blocks and then to map them into independent hardware processing elements. For this, there is required a generic controller that automatically maps such a stream of data into independent processing elements without any dependencies and manual considerations. In this paper, Kahn Process Networks (KPN) for such streaming applications is designed and developed that will be mapped on MPSoC. This is designed in such a way that there is a generic Cbased compiler that will take the mapping specifications as an input from the user and then it will automate these design constraints and automatically generate the synthesized RTL optimized code for specified application.

Keywords: KPN, DFG, FPGA

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1055549

References:

[1] Gilles Kahn, "The semantics of a simple language for parallel programming". In Jack L. Rosenfeld, editor, Information Processing 74: Proceedings of the IFIP Congress 74, pages 471-475. IFIP, North- Holland, August 1974.
[2] Edward A. Lee and Thomas M. Parks, "Dataflow process networks," Proceedings of the IEEE, vol. 83, no. 5, pp. 773-799, May 1995.
[3] Eric Cheung, Harry Hsieh, and Feris Baralin, "Automatic Buffer Sizing for Rate-Constrained KPNApplications on Multiprocessor System-on- Chip," Proceedings of IEEE, pages 37-44, 2007.
[4] Marc Geilen and Twan Basten, "Requirements on the execution of kahn process networks," In Programming Languages and Systems, 12th European Symposium on Programming, ESOP 2003, pages 319-334, Warsaw, Poland, April 2003. Lecture Notes in Computer Science vol. 2618.
[5] Twan Basten and Jan Hoogerbrugge, "Efficient execution of process networks". In A. Chalmers, M. Mirmehdi, and H. Muller, editors, Proc. Communicating Process Architectures, pages 1-14, Bristol, UK, September 2001. IOS Press
[6] Thomas M. Parks, "Bounded Scheduling of Process Networks," PhD Thesis, EECS Department, University of California, Berkeley, CA, December 1995.
[7] Bharath N., S.K. Nandy, and Nagaraju Bussa, "Artificial Deadlock Detection in Process Networks for Eclipse", Proceedings of 16th International Conference on Application-Specific Systems, Architectures and Processors, IEEE Computer Society, 1063-6862/05, 2005
[8] Ceponis J., Kazanavicius E., Mikuckas A., "Design and Analysis of DSP systems using Kahn process Networks," DSP Lab, Kaunas University of technology, ISSN 1392-2114Ultragarsas, Nr .4(45), 2002.
[9] Zvironas A., Kazanavicius E. Partitioning of DSP tasks to Kahn network. KTU. Kaunas. Ultragarsas. ISSN1392-2114, 2002. Nr. 2(43).
[10] Javed DULLOO, Philippe MARQUET, "Design of a Real-Time Scheduler for Kahn Process Networks on Multiprocessor systems," Rapport LIFL # 2003-06, september 2003.
[11] Todor Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart Kienhuis, and Ed Deprettere, "System Design using Kahn Process Netwroks: The Compaan/Laura Approach," Presented at DATE-04, Paris 16-20 Feb 2004.
[12] E. A. de Kock, W. J. M. Smits, P. van der Wolf, J.-Y. Brunel, W. M. Kruijtzer, P. Lieverse, K. A. Vissers, and G. Essink, "Yapi: application modeling for signal processing systems," in DAC -00: Proceedings of the 37th conference on Design automation. New York, NY, USA: ACM Press, 2000, pp. 402-405.
[13] P. Lieverse, T. Stefanov, P. van der Wolf, and E. Deprettere, "System level design with spade: an m-jpeg case study," in ICCAD -01: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design. Piscataway, NJ, USA: IEEE Press, 2001, pp. 31-38.
[14] Dr. Shoab A. Khan, Book: "Digital Design for Signal Processing Systems" to be published.