Search results for: Field Programmable gate array (FPGA)

Authors: Ala'eddin A. Saif , Z. A. Z. Jamal, Z. Sauli, P. Poopalan

Abstract:

The ferroelectric behavior of barium strontium titanate (BST) in thin film form has been investigated in order to study the possibility of using BST for ferroelectric gate-field effect transistor (FeFET) for memory devices application. BST thin films have been fabricated as Al/BST/Pt/SiO2/Si-gate configuration. The variation of the dielectric constant (ε) and tan δ with frequency have been studied to ensure the dielectric quality of the material. The results show that at low frequencies, ε increases as the Ba content increases, whereas at high frequencies, it shows the opposite variation, which is attributed to the dipole dynamics. tan δ shows low values with a peak at the mid-frequency range. The ferroelectric behavior of the Al/BST/Pt/SiO2/Si has been investigated using C-V characteristics. The results show that the strength of the ferroelectric hysteresis loop increases as the Ba content increases; this is attributed to the grain size and dipole dynamics effect.

Keywords: BST thin film, Electrical properties, Ferroelectrichysteresis, Ferroelectric FET.

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Authors: Jurij Tasinkiewicz

Abstract:

The aim of this work is to present a theoretical analysis of a 2D ultrasound transducer comprised of crossed arrays of metal strips placed on both sides of thin piezoelectric layer (a). Such a structure is capable of electronic beam-steering of generated wavebeam both in elevation and azimuth. In this paper a semi-analytical model of the considered transducer is developed. It is based on generalization of the well-known BIS-expansion method. Specifically, applying the electrostatic approximation, the electric field components on the surface of the layer are expanded into fast converging series of double periodic spatial harmonics with corresponding amplitudes represented by the properly chosen Legendre polynomials. The problem is reduced to numerical solving of certain system of linear equations for unknown expansion coefficients.

Keywords: Beamforming, transducer array, BIS-expansion.

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Authors: Xia Liu, Marek E. Bialkowski

Abstract:

This paper reports on investigations into capacity of a Multiple Input Multiple Output (MIMO) wireless communication system employing a uniform linear array (ULA) at the transmitter and either a uniform linear array (ULA) or a uniform circular array (UCA) antenna at the receiver. The transmitter is assumed to be surrounded by scattering objects while the receiver is postulated to be free from scattering objects. The Laplacian distribution of angle of arrival (AOA) of a signal reaching the receiver is postulated. Calculations of the MIMO system capacity are performed for two cases without and with the channel estimation errors. For estimating the MIMO channel, the scaled least square (SLS) and minimum mean square error (MMSE) methods are considered.

Keywords: MIMO, channel capacity, channel estimation, ULA, UCA, spatial correlation

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Authors: Kureshi Abdul Kadir, Mohd. Hasan

Abstract:

Each new semiconductor technology node brings smaller transistors and wires. Although this makes transistors faster, wires get slower. In nano-scale regime, the standard copper (Cu) interconnect will become a major hurdle for FPGA interconnect due to their high resistivity and electromigration. This paper presents the comprehensive evaluation of mixed CNT bundle interconnects and investigates their prospects as energy efficient and high speed interconnect for future FPGA routing architecture. All HSPICE simulations are carried out at operating frequency of 1GHz and it is found that mixed CNT bundle implemented in FPGAs as interconnect can potentially provide a substantial delay and energy reduction over traditional interconnects at 32nm process technology.

Keywords: CMOS, Copper Interconnect, Mixed CNT Bundle Interconnect, FPGAs.

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Authors: Imron Rosyadi, Ridha A. Djemal, Saleh A. Alshebeili

Abstract:

Design and implementation of a novel B-ACOSD CFAR algorithm is presented in this paper. It is proposed for detecting radar target in log-normal distribution environment. The BACOSD detector is capable to detect automatically the number interference target in the reference cells and detect the real target by an adaptive threshold. The detector is implemented as a System on Chip on FPGA Altera Stratix II using parallelism and pipelining technique. For a reference window of length 16 cells, the experimental results showed that the processor works properly with a processing speed up to 115.13MHz and processing time0.29 ┬Ás, thus meets real-time requirement for a typical radar system.

Keywords: CFAR, FPGA, radar.

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Authors: Badar Muneer, Waseem Shabir, Faisal Karim Shaikh

Abstract:

Substrate Integrated waveguide based 6-element array of Planar Inverted F antenna (PIFA) has been presented and analyzed parametrically in this paper. The antenna is fed with coupled transverse slots on a plate laminated waveguide cavity to ensure wide bandwidth and simplicity of feeding network. The two-layer structure has one layer dedicated for feeding network and the top layer dedicated for radiating elements. It has been demonstrated that the presented feeding technique for feeding such class of array antennas can be far simple in structure and miniaturized in size when it comes to designing large phased array antenna systems. A good return loss and standing wave ratio of 2:1 has been achieved while maintaining properties of typical PIFA.

Keywords: Feeding network, laminated waveguide, PIFA, transverse slots.

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Authors: Wang Jing, Liu Shouwen, Pei Yifei

Abstract:

A satellite is being integrated and tested by BISEE (Beijing Institute of Spacecraft Environment Engineering). This paper describes the infrared lamp array simulation technology used for satellite thermal balance and thermal vacuum test. These tests were performed in KM6 space environmental simulator in Beijing, China. New software and hardware developed by BISEE, along with enhanced heat flux uniformity, provided for well accomplished thermal balance and thermal vacuum tests. The flux uniformity of lamp array was satisfied with test requirement. Monitored background radiometer offered reliable heat flux measurements with remarkable repeatability. Simulation software supplied accurate thermal flux distribution predictions.

Keywords: Satellite, Thermal test, Infrared lamp array, Heatflux

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Authors: Fatma Belghith, Hassen Loukil, Nouri Masmoudi

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This paper presents the hardware design of a unified architecture to compute the 4x4, 8x8 and 16x16 efficient twodimensional (2-D) transform for the HEVC standard. This architecture is based on fast integer transform algorithms. It is designed only with adders and shifts in order to reduce the hardware cost significantly. The goal is to ensure the maximum circuit reuse during the computing while saving 40% for the number of operations. The architecture is developed using FIFOs to compute the second dimension. The proposed hardware was implemented in VHDL. The VHDL RTL code works at 240 MHZ in an Altera Stratix III FPGA. The number of cycles in this architecture varies from 33 in 4-point- 2D-DCT to 172 when the 16-point-2D-DCT is computed. Results show frequency improvements reaching 96% when compared to an architecture described as the direct transcription of the algorithm.

Keywords: HEVC, Modified Integer Transform, FPGA.

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Authors: Olesya Bolkhovskaya, Alexey Davydov, Alexander Maltsev

Abstract:

In this paper two approaches to joint signal detection, time of arrival (ToA) and angle of arrival (AoA) estimation in multi-element antenna array are investigated. Two scenarios were considered: first one, when the waveform of the useful signal is known a priori and, second one, when the waveform of the desired signal is unknown. For first scenario, the antenna array signal processing based on multi-element matched filtering (MF) with the following non-coherent detection scheme and maximum likelihood (ML) parameter estimation blocks is exploited. For second scenario, the signal processing based on the antenna array elements covariance matrix estimation with the following eigenvector analysis and ML parameter estimation blocks is applied. The performance characteristics of both signal processing schemes are thoroughly investigated and compared for different useful signals and noise parameters.

Keywords: Antenna array, signal detection, ToA, AoA estimation.

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Authors: Tetsuki Taniguchi, Yoshio Karasawa

Abstract:

This paper describes a subarray based low computational design method of multiuser massive multiple input multiple output (MIMO) system. In our previous works, use of large array is assumed only in transmitter, but this study considers the case both of transmitter and receiver sides are equipped with large array antennas. For this aim, receive arrays are also divided into several subarrays, and the former proposed method is modified for the synthesis of a large array from subarrays in both ends. Through computer simulations, it is verified that the performance of the proposed method is degraded compared with the original approach, but it can achieve the improvement in the aspect of complexity, namely, significant reduction of the computational load to the practical level.

Keywords: Massive multiple input multiple output (MIMO), multiuser, large array, subarray, zero forcing, singular value decomposition.

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Authors: Z. Dibi, F. Djeffal, N. Lakhdar

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In this paper, we have developed an explicit analytical drain current model comprising surface channel potential and threshold voltage in order to explain the advantages of the proposed Gate Stack Double Diffusion (GSDD) MOSFET design over the conventional MOSFET with the same geometric specifications that allow us to use the benefits of the incorporation of the high-k layer between the oxide layer and gate metal aspect on the immunity of the proposed design against the self-heating effects. In order to show the efficiency of our proposed structure, we propose the simulation of the power chopper circuit. The use of the proposed structure to design a power chopper circuit has showed that the (GSDD) MOSFET can improve the working of the circuit in terms of power dissipation and self-heating effect immunity. The results so obtained are in close proximity with the 2D simulated results thus confirming the validity of the proposed model.

Keywords: Double-Diffusion, modeling, MOSFET, power.

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Authors: Wee Leong Son, Hasmayadi Abdul Majid, Rohana Musa

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This paper study the segmented split capacitor Digital-to-Analog Converter (DAC) implemented in a differentialtype 12-bit Successive Approximation Analog-to-Digital Converter (SA-ADC). The series capacitance split array method employed as it reduced the total area of the capacitors required for high resolution DACs. A 12-bit regular binary array structure requires 2049 unit capacitors (Cs) while the split array needs 127 unit Cs. These results in the reduction of the total capacitance and power consumption of the series split array architectures as to regular binary-weighted structures. The paper will show the 12-bit DAC series split capacitor with 4-bit thermometer coded DAC architectures as well as the simulation and measured results.

Keywords: Successive Approximation Register Analog-to- Digital Converter, SAR ADC, Low voltage ADC.

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Authors: Naser Ojaroudi Parchin, Atta Ullah, Haleh Jahanbakhsh Basherlou, Raed A. Abd-Alhameed, Peter S. Excell

Abstract:

A design of beam-steerable antenna array for the future cellular communication (5G) is presented. The proposed design contains eight elements of compact end-fire antennas arranged on the top edge of smartphone printed circuit board (PCB). Configuration of the antenna element consists of the conductive patterns on the top and bottom copper foil layers and a substrate layer with a via-hole. The simulated results including input-impedance and also fundamental radiation properties have been presented and discussed. The impedance bandwidth (S₁₁ ≤ -10 dB) of the antenna spans from 17.5 to 21 GHz (more than 3 GHz bandwidth) with a resonance at 19 GHz. The antenna exhibits end-fire (directional) radiation beams with wide-angle scanning property and could be used for the future 5G beam-forming. Furthermore, the characteristics of the array design in the vicinity of user-hand are studied.

Keywords: Beam-steering, end-fire radiation mode, mobile-phone antenna, phased array.

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Authors: H. Loukil, A. Ben Atitallah, F. Ghozzi, M. A. Ben Ayed, N. Masmoudi

Abstract:

In MPEG and H.26x standards, to eliminate the temporal redundancy we use motion estimation. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a re-configurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present hardware architecture for motion estimation based on "Full Search Block Matching" (FSBM) algorithm. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources such as embedded memory blocks, and combining both pipelining and parallel processing techniques. Our design is described in VHDL language, verified by simulation and implemented in a Stratix II EP2S130F1020C4 FPGA circuit. The experiment result show that the optimum operating clock frequency of the proposed design is 89MHz which achieves 160M pixels/sec.

Keywords: SAD, FSBM, Hardware Implementation, FPGA.

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Authors: Hyun-Ho Lee, Kee-Won Kim

Abstract:

The arithmetic operations over GF(2m) have been extensively used in error correcting codes and public-key cryptography schemes. Finite field arithmetic includes addition, multiplication, division and inversion operations. Addition is very simple and can be implemented with an extremely simple circuit. The other operations are much more complex. The multiplication is the most important for cryptosystems, such as the elliptic curve cryptosystem, since computing exponentiation, division, and computing multiplicative inverse can be performed by computing multiplication iteratively. In this paper, we present a parallel computation algorithm that operates Montgomery multiplication over finite field using redundant basis. Also, based on the multiplication algorithm, we present an efficient semi-systolic multiplier over finite field. The multiplier has less space and time complexities compared to related multipliers. As compared to the corresponding existing structures, the multiplier saves at least 5% area, 50% time, and 53% area-time (AT) complexity. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as inversion and division operation.

Keywords: Finite field, Montgomery multiplication, systolic array, cryptography.

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Authors: Mojtaba Valinataj

Abstract:

Reversible logic as a new favorable design domain can be used for various fields especially creating quantum computers because of its speed and intangible power consumption. However, its susceptibility to a variety of environmental effects may lead to yield the incorrect results. In this paper, because of the importance of multiplication operation in various computing systems, some novel reversible logic array multipliers are proposed with error detection capability by incorporating the parity-preserving gates. The new designs are presented for two main parts of array multipliers, partial product generation and multi-operand addition, by exploiting the new arrangements of existing gates, which results in two signed parity-preserving array multipliers. The experimental results reveal that the best proposed 4×4 multiplier in this paper reaches 12%, 24%, and 26% enhancements in the number of constant inputs, number of required gates, and quantum cost, respectively, compared to previous design. Moreover, the best proposed design is generalized for n×n multipliers with general formulations to estimate the main reversible logic criteria as the functions of the multiplier size.

Keywords: Array multipliers, Baugh-Wooley method, error detection, parity-preserving gates, quantum computers, reversible logic.

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Authors: Naoto Suzuki

Abstract:

Many ophthalmologists can examine declines in visual sensitivity at arbitrary points on the retina using a precise perimetry device with a fundus camera function. However, the retinal layer causing the decline in visual sensitivity cannot be identified by this method. We studied an electroretinogram (ERG) function that can move the center of the multifocal hexagonal stimulus array in order to investigate cryptogenic diseases, such as macular dystrophy, acute zonal occult outer retinopathy, and multiple evanescent white dot syndrome. An electroretinographic optical system, specifically a perimetric optical system, was added to an experimental device carrying the same optical system as a fundus camera. We also added an infrared camera, a cold mirror, a halogen lamp, and a monitor. The software was generated to show the multifocal hexagonal stimulus array on the monitor using C++Builder XE8 and to move the center of the array up and down as well as back and forth. We used a multifunction I/O device and its design platform LabVIEW for data retrieval. The plate electrodes were used to measure electrodermal activities around the eyes. We used a multifocal hexagonal stimulus array with 37 elements in the software. The center of the multifocal hexagonal stimulus array could be adjusted to the same position as the examination target of the precise perimetry. We successfully added the moving ERG function to the experimental ophthalmologic device.

Keywords: Moving ERG, precise perimetry, retinal layers, visual sensitivity.

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Authors: Vasile Marinescu, Ionut Clementin Constantin, Alexandru Epureanu, Virgil Teodor

Abstract:

The Programmable Logic Controller (PLC) plays a vital role in automation and process control. Grafcet is used for representing the control logic, and traditional programming languages are used for describing the pure algorithms. Grafcet is used for dividing the process to be automated in elementary sequences that can be easily implemented. Each sequence represent a step that has associated actions programmed using textual or graphical languages after case. The programming task is simplified by using a set of subroutines that are used in several steps. The paper presents an example of implementation for a punching machine for sheets and plates. The use the graphical languages the programming of a complex sequential process is a necessary solution. The state of Grafcet can be used for debugging and malfunction determination. The use of the method combined with a set of knowledge acquisition for process application reduces the downtime of the machine and improve the productivity.

Keywords: Grafcet, Petrinet, PLC, punching.

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Authors: Mehdi Moayyedian, Kazem Abhary, Romeo Marian

Abstract:

This paper presents an evaluation of a plastic defect in injection molding before it occurs in the process; it is known as the short shot defect. The evaluation of different parameters which affect the possibility of short shot defect is the aim of this paper. The analysis of short shot possibility is conducted via SolidWorks Plastics and Taguchi method to determine the most significant parameters. Finite Element Method (FEM) is employed to analyze two circular flat polypropylene plates of 1 mm thickness. Filling time, part cooling time, pressure holding time, melt temperature and gate type are chosen as process and geometric parameters, respectively. A methodology is presented herein to predict the possibility of the short-shot occurrence. The analysis determined melt temperature is the most influential parameter affecting the possibility of short shot defect with a contribution of 74.25%, and filling time with a contribution of 22%, followed by gate type with a contribution of 3.69%. It was also determined the optimum level of each parameter leading to a reduction in the possibility of short shot are gate type at level 1, filling time at level 3 and melt temperature at level 3. Finally, the most significant parameters affecting the possibility of short shot were determined to be melt temperature, filling time, and gate type.

Keywords: Injection molding, plastic defects, short shot, Taguchi method.

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Authors: Indre Brazauskaite, Vilte Auruskeviciene

Abstract:

The paper explores the Stage-Gate framework application for innovation maturity among small and medium-sized enterprises (SMEs). Innovation management becomes an essential business survival process for all sizes of organizations that can be evaluated and audited systemically. This research systemically defines and assesses the innovation process from the perspective of the company’s top management. Empirical research explores attitudes and existing practices of innovation management in SMEs in Baltic countries. It structurally investigates the current innovation management practices, level of standardization, and potential challenges in the area. Findings allow to structure of existing practices based on an institutionalized model and contribute to a more advanced understanding of the innovation process among SMEs. Practically, findings contribute to advanced decision-making and business planning in the process.

Keywords: innovation measure, innovation process, small and medium-sized enterprises, SMEs, stage-gate framework.

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Authors: Nur Syarafina Binti Othman, Tsubasa Jindo, Makato Yamada, Miho Tsuyama, Hitoshi Nakano

Abstract:

A novel method to produce a fast high voltage solid states switch using Insulated Gate Bipolar Transistors (IGBTs) is presented for discharge-pumped gas lasers. The IGBTs are connected in series to achieve a high voltage rating. An avalanche transistor is used as the gate driver. The fast pulse generated by the avalanche transistor quickly charges the large input capacitance of the IGBT, resulting in a switch out of a fast high-voltage pulse. The switching characteristic of fast-high voltage solid state switch has been estimated in the multi-stage series-connected IGBT with the applied voltage of several tens of kV. Electrical circuit diagram and the mythology of fast-high voltage solid state switch as well as experimental results obtained are presented.

Keywords: High voltage, IGBT, Solid states switch.

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Authors: Mahmoud Z. Iskandarani, Nidal F. Shilbayeh

Abstract:

The voltage/current characteristics and the effect of NO2 gas on the electrical conductivity of a PbPc gas sensor array is investigated. The gas sensor is manufactured using vacuum deposition of gold electrodes on sapphire substrate with the leadphathalocyanine vacuum sublimed on the top of the gold electrodes. Two versions of the PbPc gas sensor array are investigated. The tested types differ in the gap sizes between the deposited gold electrodes. The sensors are tested at different temperatures to account for conductivity changes as the molecular adsorption/desorption rate is affected by heat. The obtained results found to be encouraging as the sensors shoed stability and sensitivity towards low concentration of applied NO2 gas.

Keywords: Intelligent System, PbPc, Gas Sensor, Hardware, Software, Neural.

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Authors: Mohammad Taha, Dia abu al Nadi

Abstract:

In this paper, the phase control antenna array synthesis is presented. The problem is formulated as a constrained optimization problem that imposes nulls with prescribed level while maintaining the sidelobe at a prescribed level. For efficient use of the algorithm memory, compared to the well known Particle Swarm Optimization (PSO), the Accelerated Particle Swarm Optimization (APSO) is used to estimate the phase parameters of the synthesized array. The objective function is formed using a main objective and set of constraints with penalty factors that measure the violation of each feasible solution in the search space to each constraint. In this case the obtained feasible solution is guaranteed to satisfy all the constraints. Simulation results have shown significant performance increases and a decreased randomness in the parameter search space compared to a single objective conventional particle swarm optimization.

Keywords: Array synthesis, Sidelobe level control, Constrainedoptimization, Accelerated Particle Swarm Optimization.

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Authors: Anil Kumar Pandey

Abstract:

Power plane noise is the most significant source of signal integrity (SI) issues in a high-speed digital design. In this paper, power integrity (PI) analysis of multiple power planes in a power delivery system of a 12-layer high-speed FPGA board is presented. All 10 power planes of HSD board are analyzed separately by using 3D Electromagnetic based PI solver, then the transient simulation is performed on combined PI data of all planes along with voltage regulator modules (VRMs) and 70 current drawing chips to get the board level power noise coupling on different high-speed signals. De-coupling capacitors are placed between power planes and ground to reduce power noise coupling with signals.

Keywords: Channel simulation, electromagnetic simulation, power-aware signal integrity analysis, power integrity, PIPro.

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Authors: Hassan M. Elkamchouchi, Samy H. Darwish, Yasser H. Elkamchouchi, M. E. Morsy

Abstract:

Methodology is suggested to design a linear rectangular microstrip array antenna based on Yagi antenna theory. The antenna with different directors' lengths as parasitic elements were designed, simulated, and analyzed using HFSS. The calculus and results illustrate the effectiveness of using specific parasitic elements to improve the directivity and gain for microstrip array antenna. The results have shown that the suggested methodology has the potential to be applied for improving the antenna performance. Maximum radiation intensity (Umax) of the order of 0.47w/st was recorded, directivity of 6.58dB, and gain better than 6.07dB are readily achievable for the antenna that working.

Keywords: Directivity, director, gain improvement, microstrip antenna.

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Authors: M. Lakshmi, J. Senthil Kumar

Abstract:

Digital cameras to reduce cost, use an image sensor to capture color images. Color Filter Array (CFA) in digital cameras permits only one of the three primary (red-green-blue) colors to be sensed in a pixel and interpolates the two missing components through a method named demosaicking. Captured data is interpolated into a full color image and compressed in applications. Color interpolation before compression leads to data redundancy. This paper proposes a new Vector Quantization (VQ) technique to construct a VQ codebook with Differential Evolution (DE) Algorithm. The new technique is compared to conventional Linde- Buzo-Gray (LBG) method.

Keywords: Color Filter Array (CFA), Biorthogonal Wavelet, Vector Quantization (VQ), Differential Evolution (DE).

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Authors: P. Kamphikul, P. Krachodnok, R. Wongsan

Abstract:

This paper presents the gain improvement of a sector antenna for mobile phone base station by using the new technique to enhance its gain for microstrip antenna (MSA) array without construction enlargement. The curved woodpile Electromagnetic Band Gap (EBG) has been utilized to improve the gain instead. The advantages of this proposed antenna are reducing the length of MSAs array but providing the higher gain and easy fabrication and installation. Moreover, it provides a fan-shaped radiation pattern, wide in the horizontal direction and relatively narrow in the vertical direction, which appropriate for mobile phone base station. The paper also presents the design procedures of a 1x8 MSAs array associated with U-shaped reflector for decreasing their back and side lobes. The fabricated curved woodpile EBG exhibits bandgap characteristics at 2.1 GHz and is utilized for realizing a resonant cavity of MSAs array. This idea has been verified by both the Computer Simulation Technology (CST) software and experimental results. As the results, the fabricated proposed antenna achieves a high gain of 20.3 dB and the half-power beam widths in the E- and H-plane of 36.8 and 8.7 degrees, respectively. Good qualitative agreement between measured and simulated results of the proposed antenna was obtained.

Keywords: Gain Improvement, Microstrip Antenna Array, Electromagnetic Band Gap, Base Station.

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Authors: J. G. Batista, L. J. de Bessa Neto, M. A. F. B. Lima, J. R. Leite, J. I. de Andrade Nunes

Abstract:

The robot manipulator is an equipment that stands out for two reasons: Firstly because of its characteristics of movement and reprogramming, resembling the arm; secondly, by adding several areas of knowledge of science and engineering. The present work shows the development of the prototype of a robotic manipulator driven by a Programmable Logic Controller (PLC), having two degrees of freedom, which allows the movement and displacement of mechanical parts, tools, and objects in general of small size, through an electronic system. The aim is to study direct and inverse kinematics of the robotic manipulator to describe the translation and rotation between two adjacent links of the robot through the Denavit-Hartenberg parameters. Currently, due to the many resources that microcomputer systems offer us, robotics is going through a period of continuous growth that will allow, in a short time, the development of intelligent robots with the capacity to perform operations that require flexibility, speed and precision.

Keywords: Direct and inverse kinematics, Denavit-Hartenberg, microcontrollers, robotic manipulator.

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Authors: Youssef Khmou, Said Safi

Abstract:

In this paper, a fifth order propagator operators are proposed for estimating the Angles Of Arrival (AOA) of narrowband electromagnetic waves impinging on antenna array when its number of sensors is larger than the number of radiating sources.

The array response matrix is partitioned into five linearly dependent phases to construct the noise projector using five different propagators from non diagonal blocks of the spectral matrice of the received data; hence, five different estimators are proposed to estimate the angles of the sources. The simulation results proved the performance of the proposed estimators in the presence of white noise comparatively to high resolution eigen based spectra.

Keywords: DOA, narrowband, antenna, propagator, high resolution. Array, operator, angular, spectrum, goniometry.

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Authors: Anatoly D. Pluzhnikov, Elena N. Pribludova, Alexander G. Ryndyk

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In conjunction with the problem of the target selection on a clutter background, the analysis of the scanning rate influence on the spatial-temporal signal structure, the generalized multivariate correlation function and the quality of the resolution with the increase pulse repetition frequency is made. The possibility of the object space-distance resolution, which is conditioned by the range-to-angle conversion with an increased scanning rate, is substantiated. The calculations for the real cylindrical array at high scanning rate are presented. The high scanning rate let to get the signal to noise improvement of the order of 10 dB for the space-time signal processing.

Keywords: Antenna pattern, array, signal processing, spatial resolution.

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