Power Integrity Analysis of Power Delivery System in High Speed Digital FPGA Board
Authors: Anil Kumar Pandey
Power plane noise is the most significant source of signal integrity (SI) issues in a high-speed digital design. In this paper, power integrity (PI) analysis of multiple power planes in a power delivery system of a 12-layer high-speed FPGA board is presented. All 10 power planes of HSD board are analyzed separately by using 3D Electromagnetic based PI solver, then the transient simulation is performed on combined PI data of all planes along with voltage regulator modules (VRMs) and 70 current drawing chips to get the board level power noise coupling on different high-speed signals. De-coupling capacitors are placed between power planes and ground to reduce power noise coupling with signals.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1127122Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 1728
 S. K. Nithin, G. Shanmugam, and S. Chandrasekar. Dynamic voltage (IR) drop analysis and design closure: issues and challenges. In Proc. ISQED, pages 611-617, Mar. 2010.
 W. Prasad Kodali. Engineering Electromagnetic Compatibility. 2nd edition, IEEE Press and John Wiley sons, Inc., 2001.
 A. K. Pandey. Power-aware signal integrity analysis of DDR4 data bus in onboard memory module. 2016 IEEE 20th Workshop on Signal and Power Integrity (SPI), Turin, Italy, 2016, pp. 1-4.
 S. Liu and N. Chang. Challenges in power-ground integrity. In Proc. ICCAD, pages 651-654, Nov. 2001.
 Joong-Ho Kim. Modeling of Multilayered Power Distribution Planes Using Transmission Matrix Method. IEEE Transactions on Advanced Packaging, Vol. 25, No. 2 (2002), pages 189-199.