Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 4

Search results for: H. Loukil

4 Actuator Fault Detection and Fault Tolerant Control of a Nonlinear System Using Sliding Mode Observer

Authors: R. Loukil, M. Chtourou, T. Damak

Abstract:

In this work, we use the Fault detection and isolation and the Fault tolerant control based on sliding mode observer in order to introduce the well diagnosis of a nonlinear system. The robustness of the proposed observer for the two techniques is tested through a physical example. The results in this paper show the interaction between the Fault tolerant control and the Diagnosis procedure.

Keywords: Fault detection and isolation “FDI”, Fault tolerant control “FTC”, sliding mode observer, nonlinear system, robustness, stability.

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3 Efficient Hardware Architecture of the Direct 2- D Transform for the HEVC Standard

Authors: Fatma Belghith, Hassen Loukil, Nouri Masmoudi

Abstract:

This paper presents the hardware design of a unified architecture to compute the 4x4, 8x8 and 16x16 efficient twodimensional (2-D) transform for the HEVC standard. This architecture is based on fast integer transform algorithms. It is designed only with adders and shifts in order to reduce the hardware cost significantly. The goal is to ensure the maximum circuit reuse during the computing while saving 40% for the number of operations. The architecture is developed using FIFOs to compute the second dimension. The proposed hardware was implemented in VHDL. The VHDL RTL code works at 240 MHZ in an Altera Stratix III FPGA. The number of cycles in this architecture varies from 33 in 4-point- 2D-DCT to 172 when the 16-point-2D-DCT is computed. Results show frequency improvements reaching 96% when compared to an architecture described as the direct transcription of the algorithm.

Keywords: HEVC, Modified Integer Transform, FPGA.

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2 A Performance Model for Designing Network in Reverse Logistic

Authors: S. Dhib, S. A. Addouche, T. Loukil, A. Elmhamedi

Abstract:

In this paper, a reverse supply chain network is investigated for a decision making. This decision is surrounded by complex flows of returned products, due to the increasing quantity, the type of returned products and the variety of recovery option products (reuse, recycling, and refurbishment). The most important problem in the reverse logistic network (RLN) is to orient returned products to the suitable type of recovery option. However, returned products orientations from collect sources to the recovery disposition have not well considered in performance model. In this study, we propose a performance model for designing a network configuration on reverse logistics. Conceptual and analytical models are developed with taking into account operational, economic and environmental factors on designing network.

Keywords: Reverse logistics, Network design, Performance model, Open loop configuration.

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1 A Pipelined FSBM Hardware Architecture for HTDV-H.26x

Authors: H. Loukil, A. Ben Atitallah, F. Ghozzi, M. A. Ben Ayed, N. Masmoudi

Abstract:

In MPEG and H.26x standards, to eliminate the temporal redundancy we use motion estimation. Given that the motion estimation stage is very complex in terms of computational effort, a hardware implementation on a re-configurable circuit is crucial for the requirements of different real time multimedia applications. In this paper, we present hardware architecture for motion estimation based on "Full Search Block Matching" (FSBM) algorithm. This architecture presents minimum latency, maximum throughput, full utilization of hardware resources such as embedded memory blocks, and combining both pipelining and parallel processing techniques. Our design is described in VHDL language, verified by simulation and implemented in a Stratix II EP2S130F1020C4 FPGA circuit. The experiment result show that the optimum operating clock frequency of the proposed design is 89MHz which achieves 160M pixels/sec.

Keywords: SAD, FSBM, Hardware Implementation, FPGA.

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