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Design of Parity-Preserving Reversible Logic Signed Array Multipliers
Authors: Mojtaba Valinataj
Abstract:Reversible logic as a new favorable design domain can be used for various fields especially creating quantum computers because of its speed and intangible power consumption. However, its susceptibility to a variety of environmental effects may lead to yield the incorrect results. In this paper, because of the importance of multiplication operation in various computing systems, some novel reversible logic array multipliers are proposed with error detection capability by incorporating the parity-preserving gates. The new designs are presented for two main parts of array multipliers, partial product generation and multi-operand addition, by exploiting the new arrangements of existing gates, which results in two signed parity-preserving array multipliers. The experimental results reveal that the best proposed 4×4 multiplier in this paper reaches 12%, 24%, and 26% enhancements in the number of constant inputs, number of required gates, and quantum cost, respectively, compared to previous design. Moreover, the best proposed design is generalized for n×n multipliers with general formulations to estimate the main reversible logic criteria as the functions of the multiplier size.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1131179Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF Downloads 552
 R. Landauer, “Irreversibility and heat generation in the computing process,” IBM Journal of Research and Development, vol. 5, no. 3, pp. 183–191, 1961.
 M. Perkowski, et al., “A general decomposition for reversible logic,” Proc. RM, pp. 119–138, 2001.
 E. Pouraliakbar, M. Haghparast, and K. Navi, “Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology,” Microelectronics Journal, vol. 42, pp. 973–981, 2011.
 M. Z. Moghadam and K. Navi, “Ultra-area-efficient reversible multiplier,” Microelectronics Journal, vol. 43, pp. 377–385, 2012.
 S. Babazadeh and M. Haghparast, “Design of a nanometric fault tolerant reversible multiplier circuit,” Journal of basic and applied scientific research, vol. 2, no. 2, pp. 1355–1361, 2012.
 X. Qi and F. Chen, “Design of fast fault tolerant reversible signed multiplier,” Intl. Journal of the Physical Sciences, vol. 7, no. 17, pp. 2506–2514, 2012.
 S. Kotiyal, H. Thapliyal, and N. Ranganathan, “Circuit for reversible quantum multiplier based on binary tree optimizing ancilla and garbage bits,” Proc. of 27th Intl. Conf. on VLSI Design (VLSID), pp. 545–550, 2014.
 V. G. Moshnyaga, “Design of minimum complexity reversible multiplier,” Proc. of IEEE Region 10 Conf. (TENCON), pp. 1–4, 2015.
 S. Kotiyal, H. Thapliyal, and N. Ranganathan, “Reversible logic based multiplication computing unit using binary tree data structure,” Journal of Supercomputing, vol. 71, pp. 2668–2693, 2015.
 D. Maslov and G. W. Dueck, “Reversible cascades with minimal garbage,” IEEE Trans. CAD Integr. Circuits Syst., vol. 23, no. 11, pp. 1497–1509, 2004.
 A. K. Biswas, M. M. Hasan, A. R. Chowdhury, and H. M. H. Babu, “Efficient approaches for designing reversible binary coded decimal adders,” Microelectronics Journal, vol. 39, pp. 1693–1703, 2008.
 M. Valinataj, M. Mirshekar, and H. Jazayeri, “Novel low-cost and fault-tolerant reversible logic adders,” Computers and Electrical Engineering, vol. 53, pp. 56–72, 2016.
 B. Parhami, “Fault-tolerant reversible circuits,” 40th Asilomar Conference on Signals, Systems and Computers (ACSSC), pp. 1726–1729, 2006.
 E. Fredkin and T. Toffoli, “Conservative logic,” Intl. Journal of Theoretical Physics, vol. 21, pp. 219–253, 1982.
 M. Hagparast and K. Navi, “A novel fault tolerant reversible gate for nanotechnology based system,” American Journal of Applied Sciences, vol. 5, no. 5, pp. 519–523, 2008.
 M. S. Islam, M. M. Rahman, Z. Begum, and M. Z. Hafiz, “Fault tolerant reversible logic synthesis: carry look-ahead and carry skip adders,” Intl. Conf. on Advances in Computational Tools for Engineering Applications (ACTEA), pp. 396–401, 2009.
 L. Jamal, M. M. Rahman, and H. M. H. Babu, “An optimal design of a fault tolerant reversible multiplier,” IEEE 26th Intl. SOC Conf. (SOCC), pp. 37–42, 2013.
 R. G. Zhou, Y.-C. Li, and M.-Q. Zhang, “Novel design for fault tolerant reversible binary coded decimal adders,” Intl. Journal of Electronics, vol. 101, no. 10, pp.1336–1356, 2014.
 S. K. Mitra and A. R. Chowdhury, “Minimum cost fault tolerant adder circuits in reversible logic synthesis,” 25th IEEE Intl. Conf. VLSI Design (VLSID), pp. 334–339, 2012.
 C. R. Baugh and B. A. Wooley, “A two’s complement parallel array multiplication algorithm,” IEEE Trans. Comput., vol. 22, no. 12, pp. 1045–1047, 1973.