Search results for: Digit-serial systolic multiplier

Authors: Hyun-Ho Lee, Kee-Won Kim

Abstract:

The arithmetic operations over GF(2m) have been extensively used in error correcting codes and public-key cryptography schemes. Finite field arithmetic includes addition, multiplication, division and inversion operations. Addition is very simple and can be implemented with an extremely simple circuit. The other operations are much more complex. The multiplication is the most important for cryptosystems, such as the elliptic curve cryptosystem, since computing exponentiation, division, and computing multiplicative inverse can be performed by computing multiplication iteratively. In this paper, we present a parallel computation algorithm that operates Montgomery multiplication over finite field using redundant basis. Also, based on the multiplication algorithm, we present an efficient semi-systolic multiplier over finite field. The multiplier has less space and time complexities compared to related multipliers. As compared to the corresponding existing structures, the multiplier saves at least 5% area, 50% time, and 53% area-time (AT) complexity. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as inversion and division operation.

Keywords: Finite field, Montgomery multiplication, systolic array, cryptography.

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Authors: Chiou-Yng Lee, Wen-Yo Lee, Chieh-Tsai Wu, Cheng-Chen Yang

Abstract:

Shifted polynomial basis (SPB) is a variation of polynomial basis representation. SPB has potential for efficient bit level and digi -level implementations of multiplication over binary extension fields with subquadratic space complexity. For efficient implementation of pairing computation with large finite fields, this paper presents a new SPB multiplication algorithm based on Karatsuba schemes, and used that to derive a novel scalable multiplier architecture. Analytical results show that the proposed multiplier provides a trade-off between space and time complexities. Our proposed multiplier is modular, regular, and suitable for very large scale integration (VLSI) implementations. It involves less area complexity compared to the multipliers based on traditional decomposition methods. It is therefore, more suitable for efficient hardware implementation of pairing based cryptography and elliptic curve cryptography (ECC) in constraint driven applications.

Keywords: Digit-serial systolic multiplier, elliptic curve cryptography (ECC), Karatsuba algorithm (KA), shifted polynomial basis (SPB), pairing computation.

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Authors: Zulhelmi Zakaria, Shuja A. Abbasi

Abstract:

A new approach has been used for optimized design of multipliers based upon the concepts of Vedic mathematics. The design has been targeted to state-of-the art field-programmable gate arrays (FPGAs). The multiplier generates partial products using Vedic mathematics method by employing basic 4x4 multipliers designed by exploiting 6-input LUTs and multiplexers in the same slices resulting in drastic reduction in area. The multiplier is realized on Xilinx FPGAs using devices Virtex-5 and Virtex-6.Carry Chain Adder was employed to obtain final products. The performance of the proposed multiplier was examined and compared to well-known multipliers such as Booth, Carry Save, Carry ripple, and array multipliers. It is demonstrated that the proposed multiplier is superior in terms of speed as well as power consumption.

Keywords: Multiplier, Vedic Mathematics, LUTs, FPGAs.

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Authors: Shobha Sharma, Amita Dev, Akanksha Kant

Abstract:

Digital signal processor, image signal processor and FIR filters have multipliers as an important part of their design. On the basis of Vedic mathematics, Vedic multipliers have come out to be very fast multipliers. One of the image processing applications is edge detection. This research presents a small area and high speed 8 bit Vedic multiplier system comprising of compressor based adders. This results in faster edge detection. This architecture is tested on Xilinx vertex 4 FPGA board and simulations were carried out using the Xilinx synthesis tool. Comparisons are made and this system is found to be smaller in area with high speed (the lesser propagation delay). This compressor based Vedic multiplier is 1.1 times speedier than a typical Vedic multiplier. Also, this Vedic Multiplier is 2 times speedier than a ‘simple’ multiplier.

Keywords: Detection of edges, Vedic multiplier, image processing, Urdhva Tiryakbhyam sutra.

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Authors: Apratim Roy, A. B. M. H. Rashid

Abstract:

In this paper, a double balanced radio frequency multiplier is presented which is customized for transmitted reference ultra wideband (UWB) receivers. The multiplier uses 90nm model parameters and exploits compensating transistors to provide controllable gain for a Gilbert core. After performing periodic and quasiperiodic non linear analyses the RF mixer (multiplier) achieves a voltage conversion gain of 16 dB and a DSB noise figure of 8.253 dB with very low power consumption. A high degree of LO to RF isolation (in the range of -94dB), RF to IF isolation (in the range of -95dB) and LO to IF isolation (in the range of -143dB) is expected for this design with an input-referred IP3 point of -1.93 dBm and an input referred 1 dB compression point of -10.67dBm. The amount of noise at the output is 7.7 nV/√Hz when the LO input is driven by a 10dBm signal. The mixer manifests better results when compared with other reported multiplier circuits and its Zero-IF performance ensures its applicability as TR-UWB multipliers.

Keywords: UWB, Transmitted Reference, Controllable Gain, RFMixer, Multiplier.

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Authors: Montree Kumngern, Kobchai Dejhan

Abstract:

Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and current mirrors are the basic building blocks in realization scheme. This technique provides; wide dynamic range, wide-bandwidth response and low power consumption. The major advantages of this approach are; its has single ended inputs; since its input is dual translinear loop operate in class-AB mode which make this multiplier configuration interesting for low-power applications; current multiplying, voltage multiplying, or current and voltage multiplying can be obtainable with balanced input. The simulation results of versatile analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth of about 19MHz, a maximum power consumption of 0.46mW, and temperature compensated. Operation of versatile analog multiplier was also confirmed through an experiment using CMOS transistor array.

Keywords: Class-AB, dual-mode CMOS analog multiplier, CMOS analog integrated circuit, CMOS translinear integrated circuit.

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Authors: Tamal Bose, Zhurun Zhang, Miloje Radenkovic, Ojas Chauhan

Abstract:

In this paper, a novel approach is presented for designing multiplier-free state-space digital filters. The multiplier-free design is obtained by finding power-of-2 coefficients and also quantizing the state variables to power-of-2 numbers. Expressions for the noise variance are derived for the quantized state vector and the output of the filter. A “structuretransformation matrix" is incorporated in these expressions. It is shown that quantization effects can be minimized by properly designing the structure-transformation matrix. Simulation results are very promising and illustrate the design algorithm.

Keywords: Digital filters, minimum noise, multiplier-free, quantization, state-space.

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Authors: Soojin Kim, Kyeongsoon Cho

Abstract:

This paper describes the pipeline architecture of high-speed modified Booth multipliers. The proposed multiplier circuits are based on the modified Booth algorithm and the pipeline technique which are the most widely used to accelerate the multiplication speed. In order to implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The speed of the multipliers is greatly improved by properly deciding the number of pipeline stages and the positions for the pipeline registers to be inserted. We described the proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits using 0.13um standard cell library. The resultant multiplier circuits show better performance than others. Since the proposed multipliers operate at GHz ranges, they can be used in the systems requiring very high performance.

Keywords: multiplier, pipeline, high-speed, modified Boothalgorithm.

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Authors: Halil Snopce, Ilir Spahiu

Abstract:

In this paper is investigated a possible optimization of some linear algebra problems which can be solved by parallel processing using the special arrays called systolic arrays. In this paper are used some special types of transformations for the designing of these arrays. We show the characteristics of these arrays. The main focus is on discussing the advantages of these arrays in parallel computation of matrix product, with special approach to the designing of systolic array for matrix multiplication. Multiplication of large matrices requires a lot of computational time and its complexity is O(n3 ). There are developed many algorithms (both sequential and parallel) with the purpose of minimizing the time of calculations. Systolic arrays are good suited for this purpose. In this paper we show that using an appropriate transformation implicates in finding more optimal arrays for doing the calculations of this type.

Keywords: Data dependences, matrix multiplication, systolicarray, transformation matrix.

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Authors: A. Dandapat, S. Ghosal, P. Sarkar, D. Mukhopadhyay

Abstract:

For higher order multiplications, a huge number of adders or compressors are to be used to perform the partial product addition. We have reduced the number of adders by introducing special kind of adders that are capable to add five/six/seven bits per decade. These adders are called compressors. Binary counter property has been merged with the compressor property to develop high order compressors. Uses of these compressors permit the reduction of the vertical critical paths. A 16×16 bit multiplier has been developed using these compressors. These compressors make the multipliers faster as compared to the conventional design that have been used 4-2 compressors and 3-2 compressors.

Keywords: Binary multiplier, Compressors, Counter, Column adder, Low power.

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Authors: Fethi Soltani, Adel Almarashi, Idir Mechai

Abstract:

Tikhonov regularization and reproducing kernels are the most popular approaches to solve ill-posed problems in computational mathematics and applications. And the Fourier multiplier operators are an essential tool to extend some known linear transforms in Euclidean Fourier analysis, as: Weierstrass transform, Poisson integral, Hilbert transform, Riesz transforms, Bochner-Riesz mean operators, partial Fourier integral, Riesz potential, Bessel potential, etc. Using the theory of reproducing kernels, we construct a simple and efficient representations for some class of Fourier multiplier operators Tm on the Paley-Wiener space Hh. In addition, we give an error estimate formula for the approximation and obtain some convergence results as the parameters and the independent variables approaches zero. Furthermore, using numerical quadrature integration rules to compute single and multiple integrals, we give numerical examples and we write explicitly the extremal function and the corresponding Fourier multiplier operators.

Keywords: Fourier multiplier operators, Gauss-Kronrod method of integration, Paley-Wiener space, Tikhonov regularization.

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Authors: Sukhwinder Singh Billing, Sushma Gupta, Sukhjit Singh Dhaliwal

Abstract:

the present paper, using the technique of differential subordination, we obtain certain results for analytic functions defined by a multiplier transformation in the open unit disc E = { z : IzI < 1}. We claim that our results extend and generalize the existing results in this particular direction

Keywords: function, Differential subordination, Multiplier transformation.

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Authors: Soo-young Ye, Gi-Ryon Kim, Dong-Keun Jung, Seong-wan Baik, Gye-rok Jeon

Abstract:

In this paper, algorithm estimating the blood pressure was proposed using the pulse transit time (PTT) as a more convenient method of measuring the blood pressure. After measuring ECG and pressure pulse, and photoplethysmography, the PTT was calculated from the acquired signals. Thereafter, the system to indirectly measure the systolic pressure and the diastolic pressure was composed using the statistic method. In comparison between the blood pressure indirectly measured by proposed algorithm estimating the blood pressure and real blood pressure measured by conventional sphygmomanometer, the systolic pressure indicates the mean error of ±3.24mmHg and the standard deviation of 2.53mmHg, while the diastolic pressure indicates the satisfactory result, that is, the mean error of ±1.80mmHg and the standard deviation of 1.39mmHg. These results are satisfied with the regulation of ANSI/AAMI for certification of sphygmomanometer that real measurement error value should be within the mean error of ±5mmHg and the standard deviation of 8mmHg. These results are suggest the possibility of applying to portable and long time blood pressure monitoring system hereafter.

Keywords: Blood pressure, Systolic, Diastolic, Pulse transit time.

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Authors: Abhijit Chandra, Sudipta Chattopadhyay

Abstract:

In this communication, we have made an attempt to design multiplier-less low-pass finite impulse response (FIR) filter with the aid of various mutation strategies of Differential Evolution (DE) algorithm. Impulse response coefficient of the designed FIR filter has been represented as sums or differences of powers of two. Performance of the proposed filter has been evaluated in terms of its frequency response and associated hardware cost. Supremacy of our approach has been substantiated by comparing our result with many of the existing multiplier-less filter design algorithms of recent interest. It has also been demonstrated that DE-optimized filter outperforms Genetic Algorithm (GA) based design by a large margin.  Hardware efficiency of our algorithm has further been validated by implementing those filters on a Field Programmable Gate Array (FPGA) chip.

Keywords: Convergence speed, Differential Evolution (DE), error histogram, finite impulse response (FIR) filter, total power of two (TPT), zero-valued filter coefficient (ZFC).

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Authors: Sukhwinder Singh Billing, Sushma Gupta, Sukhjit Singh Dhaliwal

Abstract:

In the present paper, we investigate a differential subordination involving multiplier transformation related to a sector in the open unit disk E = {z : |z| < 1}. As special cases to our main result, certain sufficient conditions for strongly starlike and strongly convex functions are obtained.

Keywords: Analytic function, Multiplier transformation, Strongly starlike function, Strongly convex function.

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Authors: M. Aleshams, A. Shahsavandi

Abstract:

This paper describes a CMOS four-quadrant multiplier intended for use in the front-end receiver by utilizing the square-law characteristic of the MOS transistor in the saturation region. The circuit is based on 0.35 um CMOS technology simulated using HSPICE software. The mixer has a third-order inter the power consumption is 271uW from a single 1.2V power supply. One of the features of the proposed design is using two MOS transistors limitation to reduce the supply voltage, which leads to reduce the power consumption. This technique provides a GHz bandwidth response and low power consumption.

Keywords: RF-Mixer, Multiplier, cut-off frequency, power consumption

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Authors: James Patrick A. Diaz, Raul E. Ramboyong

Abstract:

Background: Hypertensive response during maximal exercise test provides important information on the level of blood pressure control and evaluation of treatment. Method: A single center retrospective descriptive study was conducted among 117 young (aged 20 to 40) and middle age (aged 40 to 65) hypertensive patients, who underwent treadmill stress test. Currently on maintenance frontline medication either monotherapy (Angiotensin-converting enzyme inhibitor/Angiotensin receptor blocker [ACEi/ARB], Calcium channel blocker [CCB], Diuretic - Hydrochlorthiazide [HCTZ]) or combination therapy (ARB+CCB, ARB+HCTZ), who attained a maximal exercise on treadmill stress test (TMST) with hypertensive response (systolic blood pressure: male >210 mm Hg, female >190 mm Hg, diastolic blood pressure >100 mmHg, or increase of >10 mm Hg at any time during the test), on Bruce and Modified Bruce protocol. Exaggerated blood pressure response during exercise (systolic [SBP] and diastolic [DBP]), peak exercise blood pressure (SBP and DBP), recovery period (SBP and DBP) and test for ischemia and their antihypertensive medication/s were investigated. Analysis of variance and chi-square test were used for statistical analysis. Results: Hypertensive responses on maximal exercise test were seen mostly among female population (P < 0.000) and middle age (P < 0.000) patients. Exaggerated diastolic blood pressure responses were significantly lower in patients who were taking CCB (P < 0.004). A longer recovery period that showed a delayed decline in SBP was observed in patients taking ARB+HCTZ (P < 0.036). There were no significant differences in the level of exaggerated systolic blood pressure response and during peak exercise (both systolic and diastolic) in patients using either monotherapy or combination antihypertensives. Conclusion: Calcium channel blockers provided lower exaggerated diastolic BP response during maximal exercise test in hypertensive middle age patients. Patients on combination therapy using ARB+HCTZ exhibited a longer recovery period of systolic blood pressure.

Keywords: Antihypertensive, exercise test, hypertension, hypertensive response.

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Authors: Rehana Naz, D. P. Mason, Fazal Mahomed

Abstract:

A systematic way to derive the conserved quantities for the axisymmetric liquid jet, free jet and wall jet using conservation laws is presented. The flow in axisymmetric jets is governed by Prandtl-s momentum boundary layer equation and the continuity equation. The multiplier approach is used to construct a basis of conserved vectors for the system of two partial differential equations for the two velocity components. The basis consists of two conserved vectors. By integrating the corresponding conservation laws across the jet and imposing the boundary conditions, conserved quantities are derived for the axisymmetric liquid and free jet. The multiplier approach applied to the third-order partial differential equation for the stream function yields two local conserved vectors one of which is a non-local conserved vector for the system. One of the conserved vectors gives the conserved quantity for the axisymmetric free jet but the conserved quantity for the wall jet is not obtained from the second conserved vector. The conserved quantity for the axisymmetric wall jet is derived from a non-local conserved vector of the third-order partial differential equation for the stream function. This non-local conserved vector for the third-order partial differential equation for the stream function is obtained by using the stream function as multiplier.

Keywords: Axisymmetric jet, liquid jet, free jet, wall jet, conservation laws, conserved quantity.

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Authors: I. V. Singh, A. Singh

Abstract:

In this paper, mesh-free element free Galerkin (EFG) method is extended to solve two-dimensional potential flow problems. Two ideal fluid flow problems (i.e. flow over a rigid cylinder and flow over a sphere) have been formulated using variational approach. Penalty and Lagrange multiplier techniques have been utilized for the enforcement of essential boundary conditions. Four point Gauss quadrature have been used for the integration on two-dimensional domain (Ω) and nodal integration scheme has been used to enforce the essential boundary conditions on the edges (┌). The results obtained by EFG method are compared with those obtained by finite element method. The effects of scaling and penalty parameters on EFG results have also been discussed in detail.

Keywords: Meshless, EFG method, potential flow, Lagrange multiplier method, penalty method, penalty parameter and scaling parameter

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Authors: M. H. Hussain, I. Musirin, A. F. Abidin, S. R. A. Rahim

Abstract:

This paper presents the implementation of Artificial Bees Colony (ABC) algorithm in solving Directional OverCurrent Relays (DOCRs) coordination problem for near-end faults occurring in fixed network topology. The coordination optimization of DOCRs is formulated as linear programming (LP) problem. The objective function is introduced to minimize the operating time of the associated relay which depends on the time multiplier setting. The proposed technique is to taken as a technique for comparison purpose in order to highlight its superiority. The proposed algorithms have been tested successfully on 8 bus test system. The simulation results demonstrated that the ABC algorithm which has been proved to have good search ability is capable in dealing with constraint optimization problems.

Keywords: Artificial bees colony, directional overcurrent relay coordination problem, relay settings, time multiplier setting.

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Authors: Harpreet Singh Dhillon, Abhijit Mitra

Abstract:

A reduced-bit multiplication algorithm based on the ancient Vedic multiplication formulae is proposed in this paper. Both the Vedic multiplication formulae, Urdhva tiryakbhyam and Nikhilam, are first discussed in detail. Urdhva tiryakbhyam, being a general multiplication formula, is equally applicable to all cases of multiplication. It is applied to the digital arithmetic and is shown to yield a multiplier architecture which is very similar to the popular array multiplier. Due to its structure, it leads to a high carry propagation delay in case of multiplication of large numbers. Nikhilam Sutra, on the other hand, is more efficient in the multiplication of large numbers as it reduces the multiplication of two large numbers to that of two smaller numbers. The framework of the proposed algorithm is taken from this Sutra and is further optimized by use of some general arithmetic operations such as expansion and bit-shifting to take advantage of bit-reduction in multiplication. We illustrate the proposed algorithm by reducing a general 4x4-bit multiplication to a single 2 x 2-bit multiplication operation.

Keywords: Multiplication, algorithm, Vedic mathematics, digital arithmetic, reduced-bit.

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Authors: Dinesh Rao, M.G.M. Khan, Sabiha Khan

Abstract:

Calibration estimation is a method of adjusting the original design weights to improve the survey estimates by using auxiliary information such as the known population total (or mean) of the auxiliary variables. A calibration estimator uses calibrated weights that are determined to minimize a given distance measure to the original design weights while satisfying a set of constraints related to the auxiliary information. In this paper, we propose a new multivariate calibration estimator for the population mean in the stratified sampling design, which incorporates information available for more than one auxiliary variable. The problem of determining the optimum calibrated weights is formulated as a Mathematical Programming Problem (MPP) that is solved using the Lagrange multiplier technique.

Keywords: Calibration estimation, Stratified sampling, Multivariate auxiliary information, Mathematical programming problem, Lagrange multiplier technique.

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Authors: I. Struhár, L. Dovrtělová, M. Kumstát

Abstract:

Regular exercise promotes reduction in blood pressure, reduction in body weight and it also helps to increase in insulin sensitivity. Participation in physical activity should always be linked to medical screening which can reveal serious medical problems. One of them is high blood pressure. Hypertension is risk factor for one billion people worldwide and the highest prevalence is found in Africa. Another component of hypertension is that people who suffer from hypertension have no symptoms. It is estimated that reduction of 3mm Hg in Systolic Blood Pressure decreases cardiac morbidity at least 5%. The most of the guidelines suggest aerobic exercise in a prevention of cardiovascular diseases. On the other hand, it is important to emphasize the impact of resistance training. Even, it was found higher effect for reduction on the level of systolic blood pressure than aerobic exercise.

Keywords: Coronary artery disease, physical activity, prevention, resistance training.

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Authors: C. Kalamani, V. Abishek Karthick, S. Anitha, K. Kavin Kumar

Abstract:

The fault tolerant system plays a crucial role in the critical applications which are being used in the present scenario. A fault may change the functionality of circuits. Aim of this paper is to design multiplier using fault tolerant hybrid full adder. Fault tolerant hybrid full adder is designed to check and repair any fault in the circuit using self-checking circuit and the self-repairing circuit. Further, the use of conventional logic circuits may result in more area, delay as well as power consumption. In order to reduce these parameters of the circuit, GDI (Gate Diffusion Input) techniques with less number of transistors are used compared to conventional full adder circuit. This reduces the area, delay and power consumption. The proposed method solves the major problems occurring in the most crucial and critical applications.

Keywords: Gate diffusion input, hybrid full adder, self-checking, fault tolerant.

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Authors: Amir Badkoubeh, Guchuan Zhu

Abstract:

This paper addresses the problem of asymptotic tracking control of a linear parabolic partial differential equation with indomain point actuation. As the considered model is a non-standard partial differential equation, we firstly developed a map that allows transforming this problem into a standard boundary control problem to which existing infinite-dimensional system control methods can be applied. Then, a combination of energy multiplier and differential flatness methods is used to design an asymptotic tracking controller. This control scheme consists of stabilizing state-feedback derived from the energy multiplier method and feed-forward control based on the flatness property of the system. This approach represents a systematic procedure to design tracking control laws for a class of partial differential equations with in-domain point actuation. The applicability and system performance are assessed by simulation studies.

Keywords: Tracking Control, In-domain point actuation, PartialDifferential Equations.

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Authors: Muhammad H. Rais,

Abstract:

Truncated multiplier is a good candidate for digital signal processing (DSP) applications including finite impulse response (FIR) and discrete cosine transform (DCT). Through truncated multiplier a significant reduction in Field Programmable Gate Array (FPGA) resources can be achieved. This paper presents for the first time a comparison of resource utilization of Spartan-3AN and Virtex-5 implementation of standard and truncated multipliers using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The Virtex-5 FPGA shows significant improvement as compared to Spartan-3AN FPGA device. The Virtex-5 FPGA device shows better performance with a percentage ratio of number of occupied slices for standard to truncated multipliers is increased from 40% to 73.86% as compared to Spartan- 3AN is decreased from 68.75% to 58.78%. Results show that the anomaly in Spartan-3AN FPGA device average connection and maximum pin delay have been efficiently reduced in Virtex-5 FPGA device.

Keywords: Digital Signal Processing (DSP), FieldProgrammable Gate Array (FPGA), Spartan-3AN, TruncatedMultiplier, Virtex-5, VHDL.

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Authors: Vladyslav Povoroznyuk, Galina Dubetska, Roksolana Povoroznyuk

Abstract:

In recent years, the problem of hyperuricemia is getting a particular importance due to its increased incidence in the world population. The aim of this study was to determine uriс acid level in blood serum, incidence of hyperuricemia among women in postmenopausal period and their association with body mass index and some components of metabolic syndrome (triglyceride, cholesterol, systolic and diastolic pressure). We examined 412 women in postmenopausal period. They were divided in to the following groups: I group (BMI = 18,5-24,9), II group (BMI = 25,0-29,9), III group (BMI = 30,0-34,9), IV group (BMI > 35). We determined uric acid level among women during postmenopausal period depending on their body mass index. The higher level of uric acid was found in patients with the maximal body mass index (BMI > 35). In the I group it was 277,52 ± 8,40; in the II group – 286,81 ± 7,79; in the III group – 291,81 ± 7,56; in the IV group – 327,17 ± 12,17. Incidence of hyperuricemia among women in the I group was 10,2%, in the II group – 15,9%; in the III group – 21,2%, in the IV group – 34,2%. We found an interdependence between an uric acid level and BMI in the examined women (r = 0,21, p < 0,05). We determined that the highest level of triglyceride (F = 18,62, p < 0,05), cholesterol (F = 3,64, p < 0,05), atherogenic coefficient (F = 22,64, p < 0,05), systolic (F = 10,5, p < 0,05) and diastolic pressure (F = 4,30, p < 0,05) was among women with hyperuricemia. It was an interdependence between an uric acid level and triglyceride (r = 0,26, p < 0,05), atherogenic coefficient (r = 0,24, p < 0,05) among women in postmenopausal period.

Keywords: Hyperuricemia, uric acid, body mass index, metabolic syndrome, triglyceride, cholesterol, atherogenic coefficient, systolic and diastolic pressure, women.

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Authors: C. Paramasivam, K. B. Jayanthi

Abstract:

An innovative approach to develop modified scaling free CORDIC based two parallel pipelined Multipath Delay Commutator (MDC) FFT and IFFT architectures for radix 2² FFT algorithm is presented. Multipliers and adders are the most important data paths in FFT and IFFT architectures. Multipliers occupy high area and consume more power. In order to optimize the area and power overhead, modified scaling-free CORDIC based complex multiplier is utilized in the proposed design. In general twiddle factor values are stored in RAM block. In the proposed work, modified scaling-free CORDIC based twiddle factor generator unit is used to generate the twiddle factor and efficient switching units are used. In addition to this, four point FFT operations are performed without complex multiplication which helps to reduce area and power in the last two stages of the pipelined architectures. The design proposed in this paper is based on multipath delay commutator method. The proposed design can be extended to any radix 2ⁿ based FFT/IFFT algorithm to improve the throughput. The work is synthesized using Synopsys design Compiler using TSMC 90-nm library. The proposed method proves to be better compared to the reference design in terms of area, throughput and power consumption. The comparative analysis of the proposed design with Xilinx FPGA platform is also discussed in the paper.

Keywords: Coordinate Rotational Digital Computer(CORDIC), Complex multiplier, Fast Fourier transform (FFT), Inverse fast Fourier transform (IFFT), Multipath delay Commutator (MDC), modified scaling free CORDIC, complex multiplier, pipelining, parallel processing, radix-2^2.

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Authors: M.Machhout, M.Zeghid, W.El hadj youssef, B.Bouallegue, A.Baganne, R.Tourki

Abstract:

Long number multiplications (n ≥ 128-bit) are a primitive in most cryptosystems. They can be performed better by using Karatsuba-Ofman technique. This algorithm is easy to parallelize on workstation network and on distributed memory, and it-s known as the practical method of choice. Multiplying long numbers using Karatsuba-Ofman algorithm is fast but is highly recursive. In this paper, we propose different designs of implementing Karatsuba-Ofman multiplier. A mixture of sequential and combinational system design techniques involving pipelining is applied to our proposed designs. Multiplying large numbers can be adapted flexibly to time, area and power criteria. Computationally and occupation constrained in embedded systems such as: smart cards, mobile phones..., multiplication of finite field elements can be achieved more efficiently. The proposed designs are compared to other existing techniques. Mathematical models (Area (n), Delay (n)) of our proposed designs are also elaborated and evaluated on different FPGAs devices.

Keywords: finite field, Karatsuba-Ofman, long numbers, multiplication, mathematical model, recursivity.

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Authors: Sakol Udomsiri, Masahiro Iwahashi

Abstract:

This paper presents comparative study on recent integer DCTs and a new method to construct a low sensitive structure of integer DCT for colored input signals. The method refers to sensitivity of multiplier coefficients to finite word length as an indicator of how word length truncation effects on quality of output signal. The sensitivity is also theoretically evaluated as a function of auto-correlation and covariance matrix of input signal. The structure of integer DCT algorithm is optimized by combination of lower sensitive lifting structure types of IRT. It is evaluated by the sensitivity of multiplier coefficients to finite word length expression in a function of covariance matrix of input signal. Effectiveness of the optimum combination of IRT in integer DCT algorithm is confirmed by quality improvement comparing with existing case. As a result, the optimum combination of IRT in each integer DCT algorithm evidently improves output signal quality and it is still compatible with the existing one.

Keywords: DCT, sensitivity, lossless, wordlength.

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