%0 Journal Article
	%A A. Dandapat and  S. Ghosal and  P. Sarkar and  D. Mukhopadhyay
	%D 2010
	%J International Journal of Electronics and Communication Engineering
	%B World Academy of Science, Engineering and Technology
	%I Open Science Index 39, 2010
	%T A 1.2-ns16×16-Bit Binary Multiplier Using High Speed Compressors
	%U https://publications.waset.org/pdf/7631
	%V 39
	%X For higher order multiplications, a huge number of
adders or compressors are to be used to perform the partial product
addition. We have reduced the number of adders by introducing
special kind of adders that are capable to add five/six/seven bits per
decade. These adders are called compressors. Binary counter
property has been merged with the compressor property to develop
high order compressors. Uses of these compressors permit the
reduction of the vertical critical paths. A 16×16 bit multiplier has
been developed using these compressors. These compressors make
the multipliers faster as compared to the conventional design that
have been used 4-2 compressors and 3-2 compressors.
	%P 485 - 490