Commenced in January 2007
Paper Count: 29978
An Efficient Implementation of High Speed Vedic Multiplier Using Compressors for Image Processing Applications
Abstract:Digital signal processor, image signal processor and FIR filters have multipliers as an important part of their design. On the basis of Vedic mathematics, Vedic multipliers have come out to be very fast multipliers. One of the image processing applications is edge detection. This research presents a small area and high speed 8 bit Vedic multiplier system comprising of compressor based adders. This results in faster edge detection. This architecture is tested on Xilinx vertex 4 FPGA board and simulations were carried out using the Xilinx synthesis tool. Comparisons are made and this system is found to be smaller in area with high speed (the lesser propagation delay). This compressor based Vedic multiplier is 1.1 times speedier than a typical Vedic multiplier. Also, this Vedic Multiplier is 2 times speedier than a ‘simple’ multiplier.
Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1123568Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF
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