Commenced in January 2007
Frequency: Monthly
Edition: International
Paper Count: 29978
An Efficient Implementation of High Speed Vedic Multiplier Using Compressors for Image Processing Applications

Authors: Shobha Sharma, Amita Dev, Akanksha Kant

Abstract:

Digital signal processor, image signal processor and FIR filters have multipliers as an important part of their design. On the basis of Vedic mathematics, Vedic multipliers have come out to be very fast multipliers. One of the image processing applications is edge detection. This research presents a small area and high speed 8 bit Vedic multiplier system comprising of compressor based adders. This results in faster edge detection. This architecture is tested on Xilinx vertex 4 FPGA board and simulations were carried out using the Xilinx synthesis tool. Comparisons are made and this system is found to be smaller in area with high speed (the lesser propagation delay). This compressor based Vedic multiplier is 1.1 times speedier than a typical Vedic multiplier. Also, this Vedic Multiplier is 2 times speedier than a ‘simple’ multiplier.

Keywords: Detection of edges, Vedic multiplier, image processing, Urdhva Tiryakbhyam sutra.

Digital Object Identifier (DOI): doi.org/10.5281/zenodo.1123568

Procedia APA BibTeX Chicago EndNote Harvard JSON MLA RIS XML ISO 690 PDF

References:


[1] Yogita Bansal, Charu Madhu and Pardeep Kaur, “High Speed Vedic Multiplier Designs- A Review”, Proceedings of 2014 RAECS UIET Punjab University Chandigarh, 06 – 08 March, 2014.
[2] Aravind E Vijayan, Arlene John and Deepak Sen, “Efficient Implementation of 8-bit Vedic Multipliers for Image Processing Application”, International Conference on Contemporary Computing and Informatics (IC3I), 2014.
[3] Gonzalez and Woods, “Digital Image processing” 3rd Ed. Addison Weslet Pub.
[4] S. S. Kerur, Prakash Narchi, Harish M Kittur, Girish V. A, “Implementation of Vedic Multiplier in Image Compression using DCT Algorithm”, 2nd International Conference on Devices, Circuits and Systems (ICDCS), 2014.
[5] J. Vinoth Kumar and Dr. C. Kumar Charlie Paul, “Design of Modified Vedic Multiplier and FPGA implementation in Multilevel 2d-DWT for Image Processing Applications”, 2nd International Conference on Current Trends in Engineering and Technology, ICCTET’14.
[6] Sushma R. Huddar, S. Rao, Rupanagudi, Kalpana M., Surabhi Mohan, “Novel High Speed Vedic Mathematics Multiplier using Compressors”, IEEE 2013.
[7] Deepthi P, V. Chakravarthi, “Design of Novel Vedic Asynchronous Digital Signal Processor Core”, 2nd International Conference on Devices, Circuits and Systems (ICDCS), IEEE 2014
[8] A. Naaz.S, Pradeep N, S. Bhairannawar, Srinivas H., “FPGA Implementation of High Speed Vedic Multiplier Using CSLA for Parallel FIR Architecture”, 2nd International Conference on Devices, Circuits and Systems (ICDCS), IEEE 2014.
[9] Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat, “High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics”, Proceeding of the 2011 IEEE Students' Technology Symposium, 2011, lIT Kharagpur.
[10] Nidhi Pokhriyal, H. Kaur1, Dr. N. Prakash, “Compressor Based Area-Efficient Low-Power 8x8 Vedic Multiplier”, Int. Journal of Engineering Research and Applications, Vol. 3, Issue 6, Nov-Dec 2013, pp.1469-1472.
[11] N Rajasekhar, T. Shanmuganantham, “A Modified Novel Compressor based Urdhwa Tiryakbhyam Multiplier”, 2014 International Conference on Computer Communication and Informatics (ICCCI -2014), Jan. 03 – 05, 2014, Coimbatore, India.
[12] Chaithra. M., K.V. Reddy “Implementation of Canny Edge Detection Algorithm on FPGA and displaying Image through VGA Interface”, International Journal of Engineering and Advanced Technology (IJEAT, Volume-2, Issue-6, August 2013
[13] Dhanabal R, Bharathi V, S. Kartika, “Digital Image Processing Using Sobel Edge Detection Algorithm in FPGA”, Journal of Theoretical and Applied Information Technology, Volume 58, 2013.
[14] Hardik Sangani, Tanay M. Modi and V.S. Kanchana Bhaaskaran,” Low Power Vedic Multiplier Using Energy Recovery Logic”, International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2014.